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Stelian Pop8e429b32008-05-08 18:52:23 +02001/*
2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian.pop@leadtechdesign.com>
4 * Lead Tech Design <www.leadtechdesign.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
Stelian Pop56a24792008-05-08 14:52:31 +020026#include <asm/sizes.h>
Stelian Pop8e429b32008-05-08 18:52:23 +020027#include <asm/arch/at91sam9263.h>
Stelian Pop8e429b32008-05-08 18:52:23 +020028#include <asm/arch/at91sam9_smc.h>
Jean-Christophe PLAGNIOL-VILLARD1332a2a2009-03-21 21:07:59 +010029#include <asm/arch/at91_common.h>
Stelian Pop8e429b32008-05-08 18:52:23 +020030#include <asm/arch/at91_pmc.h>
31#include <asm/arch/at91_rstc.h>
Jens Scharsig1b34f002010-02-03 22:47:18 +010032#include <asm/arch/at91_matrix.h>
33#include <asm/arch/at91_pio.h>
Jean-Christophe PLAGNIOL-VILLARDdc39ae92009-04-16 21:30:44 +020034#include <asm/arch/clk.h>
Stelian Pop8e429b32008-05-08 18:52:23 +020035#include <asm/arch/io.h>
Ben Warren3ae071e2008-08-12 22:11:53 -070036#include <asm/arch/hardware.h>
Stelian Pop56a24792008-05-08 14:52:31 +020037#include <lcd.h>
38#include <atmel_lcdc.h>
Stelian Pop8e429b32008-05-08 18:52:23 +020039#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
40#include <net.h>
41#endif
Ben Warren3ae071e2008-08-12 22:11:53 -070042#include <netdev.h>
Stelian Pop8e429b32008-05-08 18:52:23 +020043
44DECLARE_GLOBAL_DATA_PTR;
45
46/* ------------------------------------------------------------------------- */
47/*
48 * Miscelaneous platform dependent initialisations
49 */
50
Stelian Pop8e429b32008-05-08 18:52:23 +020051#ifdef CONFIG_CMD_NAND
52static void at91sam9263ek_nand_hw_init(void)
53{
54 unsigned long csa;
Jens Scharsig1b34f002010-02-03 22:47:18 +010055 at91_smc_t *smc = (at91_smc_t *) AT91_SMC0_BASE;
56 at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
57 at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
Stelian Pop8e429b32008-05-08 18:52:23 +020058
59 /* Enable CS3 */
Jens Scharsig1b34f002010-02-03 22:47:18 +010060 csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
61 writel(csa, &matrix->csa[0]);
62
63 /* Enable CS3 */
Stelian Pop8e429b32008-05-08 18:52:23 +020064
65 /* Configure SMC CS3 for NAND/SmartMedia */
Jens Scharsig1b34f002010-02-03 22:47:18 +010066 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
67 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
68 &smc->cs[3].setup);
Stelian Pop8e429b32008-05-08 18:52:23 +020069
Jens Scharsig1b34f002010-02-03 22:47:18 +010070 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
71 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
72 &smc->cs[3].pulse);
73
74 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
75 &smc->cs[3].cycle);
76 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
77 AT91_SMC_MODE_EXNW_DISABLE |
78#ifdef CONFIG_SYS_NAND_DBW_16
79 AT91_SMC_MODE_DBW_16 |
80#else /* CONFIG_SYS_NAND_DBW_8 */
81 AT91_SMC_MODE_DBW_8 |
82#endif
83 AT91_SMC_MODE_TDF_CYCLE(2),
84 &smc->cs[3].mode);
85
86 writel(1 << AT91SAM9263_ID_PIOA | 1 << AT91SAM9263_ID_PIOCDE,
87 &pmc->pcer);
Stelian Pop8e429b32008-05-08 18:52:23 +020088
89 /* Configure RDY/BSY */
Jens Scharsig1b34f002010-02-03 22:47:18 +010090 at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
Stelian Pop8e429b32008-05-08 18:52:23 +020091
92 /* Enable NandFlash */
Jens Scharsig1b34f002010-02-03 22:47:18 +010093 at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
Stelian Pop8e429b32008-05-08 18:52:23 +020094}
95#endif
96
Stelian Pop8e429b32008-05-08 18:52:23 +020097#ifdef CONFIG_MACB
98static void at91sam9263ek_macb_hw_init(void)
99{
Jens Scharsig1b34f002010-02-03 22:47:18 +0100100 unsigned long erstl;
101 at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
102 at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
103 at91_rstc_t *rstc = (at91_rstc_t *) AT91_RSTC_BASE;
Stelian Pop8e429b32008-05-08 18:52:23 +0200104 /* Enable clock */
Jens Scharsig1b34f002010-02-03 22:47:18 +0100105 writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer);
Stelian Pop8e429b32008-05-08 18:52:23 +0200106
107 /*
108 * Disable pull-up on:
109 * RXDV (PC25) => PHY normal mode (not Test mode)
110 * ERX0 (PE25) => PHY ADDR0
111 * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
112 *
113 * PHY has internal pull-down
114 */
Stelian Pop8e429b32008-05-08 18:52:23 +0200115
Jens Scharsig1b34f002010-02-03 22:47:18 +0100116 writel(1 << 25, &pio->pioc.pudr);
117 writel((1 << 25) | (1 <<26), &pio->pioe.pudr);
118
119 erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
Sedji Gaouaou0aafde12009-06-24 08:32:09 +0200120
Stelian Pop8e429b32008-05-08 18:52:23 +0200121 /* Need to reset PHY -> 500ms reset */
Jens Scharsig1b34f002010-02-03 22:47:18 +0100122 writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) |
123 AT91_RSTC_MR_URSTEN, &rstc->mr);
Stelian Pop8e429b32008-05-08 18:52:23 +0200124
Jens Scharsig1b34f002010-02-03 22:47:18 +0100125 writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
Stelian Pop8e429b32008-05-08 18:52:23 +0200126 /* Wait for end hardware reset */
Jens Scharsig1b34f002010-02-03 22:47:18 +0100127 while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
128 ;
Stelian Pop8e429b32008-05-08 18:52:23 +0200129
Stelian Pop19bd6882008-05-22 00:15:40 +0200130 /* Restore NRST value */
Jens Scharsig1b34f002010-02-03 22:47:18 +0100131 writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
Stelian Pop19bd6882008-05-22 00:15:40 +0200132
Stelian Pop8e429b32008-05-08 18:52:23 +0200133 /* Re-enable pull-up */
Jens Scharsig1b34f002010-02-03 22:47:18 +0100134 writel(1 << 25, &pio->pioc.puer);
135 writel((1 << 25) | (1 <<26), &pio->pioe.puer);
Stelian Pop8e429b32008-05-08 18:52:23 +0200136
Jean-Christophe PLAGNIOL-VILLARDe2c04762009-03-21 21:08:00 +0100137 at91_macb_hw_init();
Stelian Pop8e429b32008-05-08 18:52:23 +0200138}
139#endif
140
Stelian Pop56a24792008-05-08 14:52:31 +0200141#ifdef CONFIG_LCD
142vidinfo_t panel_info = {
143 vl_col: 240,
144 vl_row: 320,
145 vl_clk: 4965000,
146 vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
147 ATMEL_LCDC_INVFRAME_INVERTED,
148 vl_bpix: 3,
149 vl_tft: 1,
150 vl_hsync_len: 5,
151 vl_left_margin: 1,
152 vl_right_margin:33,
153 vl_vsync_len: 1,
154 vl_upper_margin:1,
155 vl_lower_margin:0,
156 mmio: AT91SAM9263_LCDC_BASE,
157};
158
159void lcd_enable(void)
160{
Jens Scharsig1b34f002010-02-03 22:47:18 +0100161 at91_set_pio_value(AT91_PIO_PORTA, 30, 1); /* power up */
Stelian Pop56a24792008-05-08 14:52:31 +0200162}
163
164void lcd_disable(void)
165{
Jens Scharsig1b34f002010-02-03 22:47:18 +0100166 at91_set_pio_value(AT91_PIO_PORTA, 30, 0); /* power down */
Stelian Pop56a24792008-05-08 14:52:31 +0200167}
168
169static void at91sam9263ek_lcd_hw_init(void)
170{
Jens Scharsig1b34f002010-02-03 22:47:18 +0100171 at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
Stelian Pop56a24792008-05-08 14:52:31 +0200172
Jens Scharsig1b34f002010-02-03 22:47:18 +0100173 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
174 at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
175 at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
176 at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
177 at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
178 at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
179 at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
180 at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
181 at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
182 at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
183 at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
184 at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
185 at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
186 at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
187 at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
188 at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
189 at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
190 at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
191 at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
192 at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
193 at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
194 at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
Stelian Pop56a24792008-05-08 14:52:31 +0200195
Jens Scharsig1b34f002010-02-03 22:47:18 +0100196 writel(1 << AT91SAM9263_ID_LCDC, &pmc->pcer);
Stelian Pop56a24792008-05-08 14:52:31 +0200197 gd->fb_base = AT91SAM9263_SRAM0_BASE;
198}
Haavard Skinnemoen6b59e032008-09-01 16:21:22 +0200199
200#ifdef CONFIG_LCD_INFO
201#include <nand.h>
202#include <version.h>
203
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200204#ifndef CONFIG_SYS_NO_FLASH
205extern flash_info_t flash_info[];
206#endif
207
Haavard Skinnemoen6b59e032008-09-01 16:21:22 +0200208void lcd_show_board_info(void)
209{
210 ulong dram_size, nand_size;
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200211#ifndef CONFIG_SYS_NO_FLASH
212 ulong flash_size;
213#endif
Haavard Skinnemoen6b59e032008-09-01 16:21:22 +0200214 int i;
215 char temp[32];
216
217 lcd_printf ("%s\n", U_BOOT_VERSION);
218 lcd_printf ("(C) 2008 ATMEL Corp\n");
219 lcd_printf ("at91support@atmel.com\n");
220 lcd_printf ("%s CPU at %s MHz\n",
Achim Ehrlich7c966a82010-02-24 10:29:16 +0100221 CONFIG_SYS_AT91_CPU_NAME,
Jean-Christophe PLAGNIOL-VILLARDdc39ae92009-04-16 21:30:44 +0200222 strmhz(temp, get_cpu_clk_rate()));
Haavard Skinnemoen6b59e032008-09-01 16:21:22 +0200223
224 dram_size = 0;
225 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
226 dram_size += gd->bd->bi_dram[i].size;
227 nand_size = 0;
228 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
229 nand_size += nand_info[i].size;
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200230#ifndef CONFIG_SYS_NO_FLASH
231 flash_size = 0;
232 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
233 flash_size += flash_info[i].size;
234#endif
235 lcd_printf (" %ld MB SDRAM, %ld MB NAND",
Haavard Skinnemoen6b59e032008-09-01 16:21:22 +0200236 dram_size >> 20,
237 nand_size >> 20 );
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200238#ifndef CONFIG_SYS_NO_FLASH
239 lcd_printf (",\n %ld MB NOR",
240 flash_size >> 20);
241#endif
242 lcd_puts ("\n");
Haavard Skinnemoen6b59e032008-09-01 16:21:22 +0200243}
244#endif /* CONFIG_LCD_INFO */
Stelian Pop56a24792008-05-08 14:52:31 +0200245#endif
246
Stelian Pop8e429b32008-05-08 18:52:23 +0200247int board_init(void)
248{
249 /* Enable Ctrlc */
250 console_init_f();
251
252 /* arch number of AT91SAM9263EK-Board */
253 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
254 /* adress of boot parameters */
255 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
256
Jean-Christophe PLAGNIOL-VILLARD1332a2a2009-03-21 21:07:59 +0100257 at91_serial_hw_init();
Stelian Pop8e429b32008-05-08 18:52:23 +0200258#ifdef CONFIG_CMD_NAND
259 at91sam9263ek_nand_hw_init();
260#endif
261#ifdef CONFIG_HAS_DATAFLASH
Jens Scharsig1b34f002010-02-03 22:47:18 +0100262 at91_set_pio_output(AT91_PIO_PORTE, 20, 1); /* select spi0 clock */
Jean-Christophe PLAGNIOL-VILLARD7ebafb72009-03-21 21:07:59 +0100263 at91_spi0_hw_init(1 << 0);
Stelian Pop8e429b32008-05-08 18:52:23 +0200264#endif
265#ifdef CONFIG_MACB
266 at91sam9263ek_macb_hw_init();
267#endif
268#ifdef CONFIG_USB_OHCI_NEW
Jean-Christophe PLAGNIOL-VILLARDf3f91f82009-03-21 21:08:00 +0100269 at91_uhp_hw_init();
Stelian Pop8e429b32008-05-08 18:52:23 +0200270#endif
Stelian Pop56a24792008-05-08 14:52:31 +0200271#ifdef CONFIG_LCD
272 at91sam9263ek_lcd_hw_init();
273#endif
Stelian Pop8e429b32008-05-08 18:52:23 +0200274 return 0;
275}
276
277int dram_init(void)
278{
279 gd->bd->bi_dram[0].start = PHYS_SDRAM;
280 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
281 return 0;
282}
283
284#ifdef CONFIG_RESET_PHY_R
285void reset_phy(void)
286{
Stelian Pop8e429b32008-05-08 18:52:23 +0200287}
288#endif
Ben Warren3ae071e2008-08-12 22:11:53 -0700289
290int board_eth_init(bd_t *bis)
291{
292 int rc = 0;
293#ifdef CONFIG_MACB
Jens Scharsig1b34f002010-02-03 22:47:18 +0100294 rc = macb_eth_initialize(0, (void *) AT91_EMAC_BASE, 0x00);
Ben Warren3ae071e2008-08-12 22:11:53 -0700295#endif
296 return rc;
297}