| Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2007 Freescale Semiconductor. |
| 3 | * |
| 4 | * See file CREDITS for list of people who contributed to this |
| 5 | * project. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License |
| 9 | * Version 2 as published by the Free Software Foundation. |
| 10 | */ |
| 11 | |
| Jon Loeliger | 5c74071 | 2008-01-03 10:41:04 -0600 | [diff] [blame] | 12 | #include <config.h> |
| Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 13 | #include <ppc_asm.tmpl> |
| 14 | #include <ppc_defs.h> |
| 15 | #include <asm/cache.h> |
| 16 | #include <asm/mmu.h> |
| Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 17 | #include <mpc86xx.h> |
| 18 | |
| 19 | #define LAWAR_TRGT_PCI1 0x00000000 |
| 20 | #define LAWAR_TRGT_PCIE1 0x00200000 |
| 21 | #define LAWAR_TRGT_PCIE2 0x00100000 |
| 22 | #define LAWAR_TRGT_LBC 0x00400000 |
| 23 | #define LAWAR_TRGT_DDR 0x00f00000 |
| 24 | |
| 25 | #if !defined(CONFIG_SPD_EEPROM) |
| 26 | #define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff) |
| 27 | #define LAWAR1 (LAWAR_EN | LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M)) |
| 28 | #else |
| 29 | #define LAWBAR1 0 |
| 30 | #define LAWAR1 ((LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN) |
| 31 | #endif |
| 32 | |
| 33 | #define LAWBAR2 ((CFG_PCIE1_MEM_BASE>>12) & 0xffffff) |
| 34 | #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M)) |
| 35 | |
| 36 | #define LAWBAR3 ((CFG_PCIE2_MEM_BASE>>12) & 0xffffff) |
| 37 | #define LAWAR3 (LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_256M)) |
| 38 | |
| 39 | #define LAWBAR4 ((PIXIS_BASE>>12) & 0xffffff) |
| 40 | #define LAWAR4 (LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M)) |
| 41 | |
| 42 | #define LAWBAR5 ((CFG_PCIE1_IO_PHYS>>12) & 0xffffff) |
| 43 | #define LAWAR5 (LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_1M)) |
| 44 | |
| 45 | #define LAWBAR6 ((CFG_PCIE2_IO_PHYS>>12) & 0xffffff) |
| 46 | #define LAWAR6 (LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_1M)) |
| 47 | |
| 48 | #define LAWBAR7 ((CFG_FLASH_BASE >>12) & 0xffffff) |
| 49 | #define LAWAR7 (LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) |
| 50 | |
| 51 | #define LAWBAR8 ((CFG_PCI1_MEM_PHYS>>12) & 0xffffff) |
| 52 | #define LAWAR8 (LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_256M)) |
| 53 | |
| 54 | #define LAWBAR9 ((CFG_PCI1_IO_PHYS>>12) & 0xffffff) |
| 55 | #define LAWAR9 (LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)) |
| 56 | |
| 57 | |
| 58 | .section .bootpg, "ax" |
| 59 | .globl law_entry |
| 60 | law_entry: |
| 61 | lis r7,CFG_CCSRBAR@h |
| 62 | ori r7,r7,CFG_CCSRBAR@l |
| 63 | |
| 64 | addi r4,r7,0 |
| 65 | addi r5,r7,0 |
| 66 | |
| 67 | /* Skip LAWAR0, start at LAWAR1 */ |
| 68 | lis r6,LAWBAR1@h |
| 69 | ori r6,r6,LAWBAR1@l |
| 70 | stwu r6, 0xc28(r4) |
| 71 | |
| 72 | lis r6,LAWAR1@h |
| 73 | ori r6,r6,LAWAR1@l |
| 74 | stwu r6, 0xc30(r5) |
| 75 | |
| 76 | /* LAWBAR2, LAWAR2 */ |
| 77 | lis r6,LAWBAR2@h |
| 78 | ori r6,r6,LAWBAR2@l |
| 79 | stwu r6, 0x20(r4) |
| 80 | |
| 81 | lis r6,LAWAR2@h |
| 82 | ori r6,r6,LAWAR2@l |
| 83 | stwu r6, 0x20(r5) |
| 84 | |
| 85 | /* LAWBAR3, LAWAR3 */ |
| 86 | lis r6,LAWBAR3@h |
| 87 | ori r6,r6,LAWBAR3@l |
| 88 | stwu r6, 0x20(r4) |
| 89 | |
| 90 | lis r6,LAWAR3@h |
| 91 | ori r6,r6,LAWAR3@l |
| 92 | stwu r6, 0x20(r5) |
| 93 | |
| 94 | /* LAWBAR4, LAWAR4 */ |
| 95 | lis r6,LAWBAR4@h |
| 96 | ori r6,r6,LAWBAR4@l |
| 97 | stwu r6, 0x20(r4) |
| 98 | |
| 99 | lis r6,LAWAR4@h |
| 100 | ori r6,r6,LAWAR4@l |
| 101 | stwu r6, 0x20(r5) |
| 102 | /* LAWBAR5, LAWAR5 */ |
| 103 | lis r6,LAWBAR5@h |
| 104 | ori r6,r6,LAWBAR5@l |
| 105 | stwu r6, 0x20(r4) |
| 106 | |
| 107 | lis r6,LAWAR5@h |
| 108 | ori r6,r6,LAWAR5@l |
| 109 | stwu r6, 0x20(r5) |
| 110 | |
| 111 | /* LAWBAR6, LAWAR6 */ |
| 112 | lis r6,LAWBAR6@h |
| 113 | ori r6,r6,LAWBAR6@l |
| 114 | stwu r6, 0x20(r4) |
| 115 | |
| 116 | lis r6,LAWAR6@h |
| 117 | ori r6,r6,LAWAR6@l |
| 118 | stwu r6, 0x20(r5) |
| 119 | |
| 120 | /* LAWBAR7, LAWAR7 */ |
| 121 | lis r6,LAWBAR7@h |
| 122 | ori r6,r6,LAWBAR7@l |
| 123 | stwu r6, 0x20(r4) |
| 124 | |
| 125 | lis r6,LAWAR7@h |
| 126 | ori r6,r6,LAWAR7@l |
| 127 | stwu r6, 0x20(r5) |
| 128 | |
| 129 | /* LAWBAR8, LAWAR8 */ |
| 130 | lis r6,LAWBAR8@h |
| 131 | ori r6,r6,LAWBAR8@l |
| 132 | stwu r6, 0x20(r4) |
| 133 | |
| 134 | lis r6,LAWAR8@h |
| 135 | ori r6,r6,LAWAR8@l |
| 136 | stwu r6, 0x20(r5) |
| 137 | |
| 138 | /* LAWBAR9, LAWAR9 */ |
| 139 | lis r6,LAWBAR9@h |
| 140 | ori r6,r6,LAWBAR9@l |
| 141 | stwu r6, 0x20(r4) |
| 142 | |
| 143 | lis r6,LAWAR9@h |
| 144 | ori r6,r6,LAWAR9@l |
| 145 | stwu r6, 0x20(r5) |
| 146 | |
| 147 | blr |