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Timur Tabic59e1b42010-06-14 15:28:24 -05001/*
ramneek mehresh3d7506f2012-04-18 19:39:53 +00002 * Copyright 2010-2012 Freescale Semiconductor, Inc.
Timur Tabic59e1b42010-06-14 15:28:24 -05003 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
4 * Timur Tabi <timur@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the Free
8 * Software Foundation; either version 2 of the License, or (at your option)
9 * any later version.
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15#include "../board/freescale/common/ics307_clk.h"
16
Jiang Yutang9899ac12011-01-24 18:21:15 +080017#ifdef CONFIG_36BIT
18#define CONFIG_PHYS_64BIT
19#endif
20
Matthew McClintockaf253602012-05-18 06:04:17 +000021#ifdef CONFIG_SDCARD
22#define CONFIG_RAMBOOT_SDCARD
23#define CONFIG_SYS_RAMBOOT
24#define CONFIG_SYS_EXTRA_ENV_RELOC
25#define CONFIG_SYS_TEXT_BASE 0x11000000
26#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
27#endif
28
29#ifdef CONFIG_SPIFLASH
30#define CONFIG_RAMBOOT_SPIFLASH
31#define CONFIG_SYS_RAMBOOT
32#define CONFIG_SYS_EXTRA_ENV_RELOC
33#define CONFIG_SYS_TEXT_BASE 0x11000000
34#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
35#endif
36
Matthew McClintockf45210d2013-02-18 10:02:19 +000037#define CONFIG_NAND_FSL_ELBC
38
39#ifdef CONFIG_NAND
40#define CONFIG_SPL
41#define CONFIG_SPL_INIT_MINIMAL
42#define CONFIG_SPL_SERIAL_SUPPORT
43#define CONFIG_SPL_NAND_SUPPORT
44#define CONFIG_SPL_NAND_MINIMAL
45#define CONFIG_SPL_FLUSH_IMAGE
46#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
47
48#define CONFIG_SYS_TEXT_BASE 0x00201000
49#define CONFIG_SPL_TEXT_BASE 0xfffff000
Tom Rini5ed6f442013-05-03 09:19:43 -040050#define CONFIG_SPL_MAX_SIZE 4096
Matthew McClintockf45210d2013-02-18 10:02:19 +000051#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
52#define CONFIG_SPL_RELOC_STACK 0x00100000
53#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SPL_MAX_SIZE)
54#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
55#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
56#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
57#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
58#endif
59
Timur Tabic59e1b42010-06-14 15:28:24 -050060/* High Level Configuration Options */
61#define CONFIG_BOOKE /* BOOKE */
62#define CONFIG_E500 /* BOOKE e500 family */
63#define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */
64#define CONFIG_P1022
65#define CONFIG_P1022DS
66#define CONFIG_MP /* support multiple processors */
67
Wolfgang Denk2ae18242010-10-06 09:05:45 +020068#ifndef CONFIG_SYS_TEXT_BASE
69#define CONFIG_SYS_TEXT_BASE 0xeff80000
70#endif
71
Kumar Gala7a577fd2011-01-12 02:48:53 -060072#ifndef CONFIG_RESET_VECTOR_ADDRESS
73#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
74#endif
75
Timur Tabic59e1b42010-06-14 15:28:24 -050076#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
77#define CONFIG_PCI /* Enable PCI/PCIE */
78#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
79#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
80#define CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */
81#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
82#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
83#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
84
Timur Tabic59e1b42010-06-14 15:28:24 -050085#define CONFIG_ENABLE_36BIT_PHYS
Timur Tabibabb3482011-09-06 09:36:06 -050086
87#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -050088#define CONFIG_ADDR_MAP
89#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
Jiang Yutang9899ac12011-01-24 18:21:15 +080090#endif
Timur Tabic59e1b42010-06-14 15:28:24 -050091
92#define CONFIG_FSL_LAW /* Use common FSL init code */
93
94#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
95#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
96#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
97
98/*
99 * These can be toggled for performance analysis, otherwise use default.
100 */
101#define CONFIG_L2_CACHE
102#define CONFIG_BTB
103
104#define CONFIG_SYS_MEMTEST_START 0x00000000
105#define CONFIG_SYS_MEMTEST_END 0x7fffffff
106
Timur Tabie46fedf2011-08-04 18:03:41 -0500107#define CONFIG_SYS_CCSRBAR 0xffe00000
108#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Timur Tabic59e1b42010-06-14 15:28:24 -0500109
Matthew McClintockf45210d2013-02-18 10:02:19 +0000110/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
111 SPL code*/
112#ifdef CONFIG_SPL_BUILD
113#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
114#endif
115
116
Timur Tabic59e1b42010-06-14 15:28:24 -0500117/* DDR Setup */
118#define CONFIG_DDR_SPD
119#define CONFIG_VERY_BIG_RAM
120#define CONFIG_FSL_DDR3
121
122#ifdef CONFIG_DDR_ECC
123#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
124#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
125#endif
126
127#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
128#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
129
130#define CONFIG_NUM_DDR_CONTROLLERS 1
131#define CONFIG_DIMM_SLOTS_PER_CTLR 1
132#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
133
134/* I2C addresses of SPD EEPROMs */
135#define CONFIG_SYS_SPD_BUS_NUM 1
Kumar Galac39f44d2011-01-31 22:18:47 -0600136#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
Timur Tabic59e1b42010-06-14 15:28:24 -0500137
Matthew McClintockf45210d2013-02-18 10:02:19 +0000138/* These are used when DDR doesn't use SPD. */
139#define CONFIG_SYS_SDRAM_SIZE 2048
140#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
141#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
142#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
143#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F
144#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202
145#define CONFIG_SYS_DDR_TIMING_3 0x00010000
146#define CONFIG_SYS_DDR_TIMING_0 0x40110104
147#define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746
148#define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca
149#define CONFIG_SYS_DDR_MODE_1 0x00441221
150#define CONFIG_SYS_DDR_MODE_2 0x00000000
151#define CONFIG_SYS_DDR_INTERVAL 0x0a280100
152#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
153#define CONFIG_SYS_DDR_CLK_CTRL 0x02800000
154#define CONFIG_SYS_DDR_CONTROL 0xc7000008
155#define CONFIG_SYS_DDR_CONTROL_2 0x24401041
156#define CONFIG_SYS_DDR_TIMING_4 0x00220001
157#define CONFIG_SYS_DDR_TIMING_5 0x02401400
158#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
159#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608
160
161
Timur Tabic59e1b42010-06-14 15:28:24 -0500162/*
163 * Memory map
164 *
165 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
166 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable
167 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
168 *
169 * Localbus cacheable (TBD)
170 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
171 *
172 * Localbus non-cacheable
173 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
174 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
Matthew McClintockf45210d2013-02-18 10:02:19 +0000175 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable
Timur Tabic59e1b42010-06-14 15:28:24 -0500176 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
177 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
178 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
179 */
180
181/*
182 * Local Bus Definitions
183 */
Matthew McClintockf45210d2013-02-18 10:02:19 +0000184#define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */
Jiang Yutang9899ac12011-01-24 18:21:15 +0800185#ifdef CONFIG_PHYS_64BIT
Matthew McClintockf45210d2013-02-18 10:02:19 +0000186#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800187#else
188#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
189#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500190
191#define CONFIG_FLASH_BR_PRELIM \
Matthew McClintockf45210d2013-02-18 10:02:19 +0000192 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
Timur Tabic59e1b42010-06-14 15:28:24 -0500193#define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
194
Matthew McClintockf45210d2013-02-18 10:02:19 +0000195#ifdef CONFIG_NAND
196#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
197#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
198#else
Timur Tabic59e1b42010-06-14 15:28:24 -0500199#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
200#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
Matthew McClintockf45210d2013-02-18 10:02:19 +0000201#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500202
Matthew McClintockf45210d2013-02-18 10:02:19 +0000203#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
Timur Tabic59e1b42010-06-14 15:28:24 -0500204#define CONFIG_SYS_FLASH_QUIET_TEST
205#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
206
Matthew McClintockf45210d2013-02-18 10:02:19 +0000207#define CONFIG_SYS_MAX_FLASH_BANKS 1
Timur Tabic59e1b42010-06-14 15:28:24 -0500208#define CONFIG_SYS_MAX_FLASH_SECT 1024
209
Matthew McClintockf45210d2013-02-18 10:02:19 +0000210#ifndef CONFIG_SYS_MONITOR_BASE
211#ifdef CONFIG_SPL_BUILD
212#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
213#else
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200214#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Matthew McClintockf45210d2013-02-18 10:02:19 +0000215#endif
216#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500217
218#define CONFIG_FLASH_CFI_DRIVER
219#define CONFIG_SYS_FLASH_CFI
220#define CONFIG_SYS_FLASH_EMPTY_INFO
221
Matthew McClintockf45210d2013-02-18 10:02:19 +0000222/* Nand Flash */
223#if defined(CONFIG_NAND_FSL_ELBC)
224#define CONFIG_SYS_NAND_BASE 0xff800000
225#ifdef CONFIG_PHYS_64BIT
226#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
227#else
228#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
229#endif
230
231#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
232#define CONFIG_SYS_MAX_NAND_DEVICE 1
233#define CONFIG_MTD_NAND_VERIFY_WRITE
234#define CONFIG_CMD_NAND 1
235#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
236#define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
237
238/* NAND flash config */
239#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
240 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
241 | BR_PS_8 /* Port Size = 8 bit */ \
242 | BR_MS_FCM /* MSEL = FCM */ \
243 | BR_V) /* valid */
244#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \
245 | OR_FCM_PGS /* Large Page*/ \
246 | OR_FCM_CSCT \
247 | OR_FCM_CST \
248 | OR_FCM_CHT \
249 | OR_FCM_SCY_1 \
250 | OR_FCM_TRLX \
251 | OR_FCM_EHTR)
252#ifdef CONFIG_NAND
253#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
254#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
255#else
256#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
257#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
258#endif
259
260#endif /* CONFIG_NAND_FSL_ELBC */
261
Timur Tabic59e1b42010-06-14 15:28:24 -0500262#define CONFIG_BOARD_EARLY_INIT_F
263#define CONFIG_BOARD_EARLY_INIT_R
264#define CONFIG_MISC_INIT_R
Timur Tabia2d12f82010-07-21 16:56:19 -0500265#define CONFIG_HWCONFIG
Timur Tabic59e1b42010-06-14 15:28:24 -0500266
267#define CONFIG_FSL_NGPIXIS
268#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
Jiang Yutang9899ac12011-01-24 18:21:15 +0800269#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500270#define PIXIS_BASE_PHYS 0xfffdf0000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800271#else
272#define PIXIS_BASE_PHYS PIXIS_BASE
273#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500274
275#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
276#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7)
277
278#define PIXIS_LBMAP_SWITCH 7
York Sun29068452011-01-26 10:30:00 -0800279#define PIXIS_LBMAP_MASK 0xF0
Timur Tabic59e1b42010-06-14 15:28:24 -0500280#define PIXIS_LBMAP_ALTBANK 0x20
Matthew McClintockf45210d2013-02-18 10:02:19 +0000281#define PIXIS_SPD 0x07
282#define PIXIS_SPD_SYSCLK_MASK 0x07
Jiang Yutang9b6e9d12011-02-24 16:11:56 +0800283#define PIXIS_ELBC_SPI_MASK 0xc0
284#define PIXIS_SPI 0x80
Timur Tabic59e1b42010-06-14 15:28:24 -0500285
286#define CONFIG_SYS_INIT_RAM_LOCK
287#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200288#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Timur Tabic59e1b42010-06-14 15:28:24 -0500289
Timur Tabic59e1b42010-06-14 15:28:24 -0500290#define CONFIG_SYS_GBL_DATA_OFFSET \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200291 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Timur Tabic59e1b42010-06-14 15:28:24 -0500292#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
293
294#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
Jerry Huang07b5edc2011-11-02 09:16:44 +0800295#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
Timur Tabic59e1b42010-06-14 15:28:24 -0500296
297/*
298 * Serial Port
299 */
300#define CONFIG_CONS_INDEX 1
301#define CONFIG_SYS_NS16550
302#define CONFIG_SYS_NS16550_SERIAL
303#define CONFIG_SYS_NS16550_REG_SIZE 1
304#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Matthew McClintockf45210d2013-02-18 10:02:19 +0000305#ifdef CONFIG_SPL_BUILD
306#define CONFIG_NS16550_MIN_FUNCTIONS
307#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500308
309#define CONFIG_SYS_BAUDRATE_TABLE \
310 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
311
312#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
313#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
314
315/* Use the HUSH parser */
316#define CONFIG_SYS_HUSH_PARSER
Timur Tabic59e1b42010-06-14 15:28:24 -0500317
Timur Tabic59e1b42010-06-14 15:28:24 -0500318/* Video */
Timur Tabiba8e76b2011-04-11 14:18:22 -0500319#define CONFIG_FSL_DIU_FB
320
Timur Tabid5e01e42010-09-24 01:25:53 +0200321#ifdef CONFIG_FSL_DIU_FB
322#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
323#define CONFIG_VIDEO
324#define CONFIG_CMD_BMP
Timur Tabic59e1b42010-06-14 15:28:24 -0500325#define CONFIG_CFB_CONSOLE
Timur Tabi7d3053f2011-02-15 17:09:19 -0600326#define CONFIG_VIDEO_SW_CURSOR
Timur Tabic59e1b42010-06-14 15:28:24 -0500327#define CONFIG_VGA_AS_SINGLE_DEVICE
Timur Tabid5e01e42010-09-24 01:25:53 +0200328#define CONFIG_VIDEO_LOGO
329#define CONFIG_VIDEO_BMP_LOGO
Timur Tabi55b05232010-09-16 16:35:44 -0500330#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
331/*
332 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
333 * disable empty flash sector detection, which is I/O-intensive.
334 */
335#undef CONFIG_SYS_FLASH_EMPTY_INFO
Timur Tabic59e1b42010-06-14 15:28:24 -0500336#endif
337
Timur Tabiba8e76b2011-04-11 14:18:22 -0500338#ifndef CONFIG_FSL_DIU_FB
Jiang Yutang218a7582011-01-24 18:21:19 +0800339#define CONFIG_ATI
340#endif
341
342#ifdef CONFIG_ATI
343#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
344#define CONFIG_VIDEO
345#define CONFIG_BIOSEMU
346#define CONFIG_VIDEO_SW_CURSOR
347#define CONFIG_ATI_RADEON_FB
348#define CONFIG_VIDEO_LOGO
349#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
350#define CONFIG_CFB_CONSOLE
351#define CONFIG_VGA_AS_SINGLE_DEVICE
352#endif
353
Timur Tabic59e1b42010-06-14 15:28:24 -0500354/*
355 * Pass open firmware flat tree
356 */
357#define CONFIG_OF_LIBFDT
358#define CONFIG_OF_BOARD_SETUP
359#define CONFIG_OF_STDOUT_VIA_ALIAS
360
361/* new uImage format support */
362#define CONFIG_FIT
363#define CONFIG_FIT_VERBOSE
364
365/* I2C */
366#define CONFIG_FSL_I2C
367#define CONFIG_HARD_I2C
368#define CONFIG_I2C_MULTI_BUS
369#define CONFIG_SYS_I2C_SPEED 400000
370#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
371#define CONFIG_SYS_I2C_SLAVE 0x7F
372#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
373#define CONFIG_SYS_I2C_OFFSET 0x3000
374#define CONFIG_SYS_I2C2_OFFSET 0x3100
375
376/*
377 * I2C2 EEPROM
378 */
379#define CONFIG_ID_EEPROM
380#define CONFIG_SYS_I2C_EEPROM_NXID
381#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
382#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
383#define CONFIG_SYS_EEPROM_BUS_NUM 1
384
385/*
Jiang Yutang9b6e9d12011-02-24 16:11:56 +0800386 * eSPI - Enhanced SPI
387 */
388#define CONFIG_SPI_FLASH
389#define CONFIG_SPI_FLASH_SPANSION
390
391#define CONFIG_HARD_SPI
392#define CONFIG_FSL_ESPI
393
394#define CONFIG_CMD_SF
395#define CONFIG_SF_DEFAULT_SPEED 10000000
396#define CONFIG_SF_DEFAULT_MODE 0
397
398/*
Timur Tabic59e1b42010-06-14 15:28:24 -0500399 * General PCI
400 * Memory space is mapped 1-1, but I/O space must start from 0.
401 */
402
403/* controller 1, Slot 2, tgtid 1, Base address a000 */
404#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800405#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500406#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
407#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800408#else
409#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
410#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
411#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500412#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
413#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
414#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800415#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500416#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800417#else
418#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
419#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500420#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
421
422/* controller 2, direct to uli, tgtid 2, Base address 9000 */
423#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800424#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500425#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
426#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800427#else
428#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
429#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
430#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500431#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
432#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
433#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800434#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500435#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800436#else
437#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
438#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500439#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
440
441/* controller 3, Slot 1, tgtid 3, Base address b000 */
442#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800443#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500444#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
445#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800446#else
447#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
448#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
449#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500450#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
451#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
452#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800453#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500454#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800455#else
456#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
457#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500458#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
459
460#ifdef CONFIG_PCI
Timur Tabic59e1b42010-06-14 15:28:24 -0500461#define CONFIG_PCI_PNP /* do pci plug-and-play */
462#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Kumar Gala16855ec2010-11-09 23:19:50 -0600463#define CONFIG_E1000 /* Define e1000 pci Ethernet card */
Timur Tabic59e1b42010-06-14 15:28:24 -0500464#endif
465
466/* SATA */
467#define CONFIG_LIBATA
468#define CONFIG_FSL_SATA
Zang Roy-R619119760b272012-11-26 00:05:38 +0000469#define CONFIG_FSL_SATA_V2
Timur Tabic59e1b42010-06-14 15:28:24 -0500470
471#define CONFIG_SYS_SATA_MAX_DEVICE 2
472#define CONFIG_SATA1
473#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
474#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
475#define CONFIG_SATA2
476#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
477#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
478
479#ifdef CONFIG_FSL_SATA
480#define CONFIG_LBA48
481#define CONFIG_CMD_SATA
482#define CONFIG_DOS_PARTITION
483#define CONFIG_CMD_EXT2
484#endif
485
486#define CONFIG_MMC
487#ifdef CONFIG_MMC
488#define CONFIG_CMD_MMC
489#define CONFIG_FSL_ESDHC
490#define CONFIG_GENERIC_MMC
491#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
492#endif
493
494#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
495#define CONFIG_CMD_EXT2
496#define CONFIG_CMD_FAT
497#define CONFIG_DOS_PARTITION
498#endif
499
500#define CONFIG_TSEC_ENET
501#ifdef CONFIG_TSEC_ENET
502
503#define CONFIG_TSECV2
Timur Tabic59e1b42010-06-14 15:28:24 -0500504
505#define CONFIG_MII /* MII PHY management */
506#define CONFIG_TSEC1 1
507#define CONFIG_TSEC1_NAME "eTSEC1"
508#define CONFIG_TSEC2 1
509#define CONFIG_TSEC2_NAME "eTSEC2"
510
511#define TSEC1_PHY_ADDR 1
512#define TSEC2_PHY_ADDR 2
513
514#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
515#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
516
517#define TSEC1_PHYIDX 0
518#define TSEC2_PHYIDX 0
519
520#define CONFIG_ETHPRIME "eTSEC1"
521
522#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
523#endif
524
525/*
526 * Environment
527 */
Matthew McClintockaf253602012-05-18 06:04:17 +0000528#ifdef CONFIG_RAMBOOT_SPIFLASH
529#define CONFIG_ENV_IS_IN_SPI_FLASH
530#define CONFIG_ENV_SPI_BUS 0
531#define CONFIG_ENV_SPI_CS 0
532#define CONFIG_ENV_SPI_MAX_HZ 10000000
533#define CONFIG_ENV_SPI_MODE 0
534#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
535#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
536#define CONFIG_ENV_SECT_SIZE 0x10000
537#elif defined(CONFIG_RAMBOOT_SDCARD)
538#define CONFIG_ENV_IS_IN_MMC
Timur Tabic59e1b42010-06-14 15:28:24 -0500539#define CONFIG_ENV_SIZE 0x2000
Matthew McClintockaf253602012-05-18 06:04:17 +0000540#define CONFIG_SYS_MMC_ENV_DEV 0
Matthew McClintockf45210d2013-02-18 10:02:19 +0000541#elif defined(CONFIG_NAND)
Matthew McClintockaf253602012-05-18 06:04:17 +0000542#define CONFIG_ENV_IS_IN_NAND
543#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
544#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
545#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
Matthew McClintockf45210d2013-02-18 10:02:19 +0000546#elif defined(CONFIG_SYS_RAMBOOT)
Matthew McClintockaf253602012-05-18 06:04:17 +0000547#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
548#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
549#define CONFIG_ENV_SIZE 0x2000
Matthew McClintockaf253602012-05-18 06:04:17 +0000550#else
551#define CONFIG_ENV_IS_IN_FLASH
552#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
553#define CONFIG_ENV_ADDR 0xfff80000
554#else
555#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
556#endif
557#define CONFIG_ENV_SIZE 0x2000
558#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
559#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500560
561#define CONFIG_LOADS_ECHO
562#define CONFIG_SYS_LOADS_BAUD_CHANGE
563
564/*
565 * Command line configuration.
566 */
567#include <config_cmd_default.h>
568
Kumar Gala79ee3442010-06-09 22:59:41 -0500569#define CONFIG_CMD_ELF
570#define CONFIG_CMD_ERRATA
Timur Tabic59e1b42010-06-14 15:28:24 -0500571#define CONFIG_CMD_IRQ
Timur Tabic59e1b42010-06-14 15:28:24 -0500572#define CONFIG_CMD_I2C
573#define CONFIG_CMD_MII
Kumar Gala79ee3442010-06-09 22:59:41 -0500574#define CONFIG_CMD_PING
Timur Tabic59e1b42010-06-14 15:28:24 -0500575#define CONFIG_CMD_SETEXPR
Matthew McClintockb8339e22010-12-17 17:26:41 -0600576#define CONFIG_CMD_REGINFO
Timur Tabic59e1b42010-06-14 15:28:24 -0500577
578#ifdef CONFIG_PCI
579#define CONFIG_CMD_PCI
580#define CONFIG_CMD_NET
581#endif
582
583/*
584 * USB
585 */
ramneek mehresh3d7506f2012-04-18 19:39:53 +0000586#define CONFIG_HAS_FSL_DR_USB
587#ifdef CONFIG_HAS_FSL_DR_USB
Timur Tabic59e1b42010-06-14 15:28:24 -0500588#define CONFIG_USB_EHCI
589
590#ifdef CONFIG_USB_EHCI
591#define CONFIG_CMD_USB
592#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
593#define CONFIG_USB_EHCI_FSL
594#define CONFIG_USB_STORAGE
595#define CONFIG_CMD_FAT
596#endif
ramneek mehresh3d7506f2012-04-18 19:39:53 +0000597#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500598
599/*
600 * Miscellaneous configurable options
601 */
602#define CONFIG_SYS_LONGHELP /* undef to save memory */
603#define CONFIG_CMDLINE_EDITING /* Command-line editing */
Kim Phillips5be58f52010-07-14 19:47:18 -0500604#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Timur Tabic59e1b42010-06-14 15:28:24 -0500605#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
606#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
607#ifdef CONFIG_CMD_KGDB
608#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
609#else
610#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
611#endif
612/* Print Buffer Size */
613#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
614#define CONFIG_SYS_MAXARGS 16
615#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
616#define CONFIG_SYS_HZ 1000
617
618/*
619 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500620 * have to be in the first 64 MB of memory, since this is
Timur Tabic59e1b42010-06-14 15:28:24 -0500621 * the maximum mapped by the Linux kernel during initialization.
622 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500623#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
624#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Timur Tabic59e1b42010-06-14 15:28:24 -0500625
Timur Tabic59e1b42010-06-14 15:28:24 -0500626#ifdef CONFIG_CMD_KGDB
627#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
628#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
629#endif
630
631/*
632 * Environment Configuration
633 */
634
635#define CONFIG_HOSTNAME p1022ds
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000636#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000637#define CONFIG_BOOTFILE "uImage"
Timur Tabic59e1b42010-06-14 15:28:24 -0500638#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
639
640#define CONFIG_LOADADDR 1000000
641
642#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
Timur Tabic59e1b42010-06-14 15:28:24 -0500643
644#define CONFIG_BAUDRATE 115200
645
Timur Tabi84e34b62012-05-04 12:21:29 +0000646#define CONFIG_EXTRA_ENV_SETTINGS \
647 "netdev=eth0\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200648 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
649 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
Timur Tabi84e34b62012-05-04 12:21:29 +0000650 "tftpflash=tftpboot $loadaddr $uboot && " \
651 "protect off $ubootaddr +$filesize && " \
652 "erase $ubootaddr +$filesize && " \
653 "cp.b $loadaddr $ubootaddr $filesize && " \
654 "protect on $ubootaddr +$filesize && " \
655 "cmp.b $loadaddr $ubootaddr $filesize\0" \
656 "consoledev=ttyS0\0" \
657 "ramdiskaddr=2000000\0" \
658 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
659 "fdtaddr=c00000\0" \
660 "fdtfile=p1022ds.dtb\0" \
661 "bdev=sda3\0" \
Timur Tabiba8e76b2011-04-11 14:18:22 -0500662 "hwconfig=esdhc;audclk:12\0"
Timur Tabic59e1b42010-06-14 15:28:24 -0500663
664#define CONFIG_HDBOOT \
665 "setenv bootargs root=/dev/$bdev rw " \
Timur Tabi84e34b62012-05-04 12:21:29 +0000666 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
Timur Tabic59e1b42010-06-14 15:28:24 -0500667 "tftp $loadaddr $bootfile;" \
668 "tftp $fdtaddr $fdtfile;" \
669 "bootm $loadaddr - $fdtaddr"
670
671#define CONFIG_NFSBOOTCOMMAND \
672 "setenv bootargs root=/dev/nfs rw " \
673 "nfsroot=$serverip:$rootpath " \
674 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
Timur Tabi84e34b62012-05-04 12:21:29 +0000675 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
Timur Tabic59e1b42010-06-14 15:28:24 -0500676 "tftp $loadaddr $bootfile;" \
677 "tftp $fdtaddr $fdtfile;" \
678 "bootm $loadaddr - $fdtaddr"
679
680#define CONFIG_RAMBOOTCOMMAND \
681 "setenv bootargs root=/dev/ram rw " \
Timur Tabi84e34b62012-05-04 12:21:29 +0000682 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
Timur Tabic59e1b42010-06-14 15:28:24 -0500683 "tftp $ramdiskaddr $ramdiskfile;" \
684 "tftp $loadaddr $bootfile;" \
685 "tftp $fdtaddr $fdtfile;" \
686 "bootm $loadaddr $ramdiskaddr $fdtaddr"
687
688#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
689
690#endif