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Mark Jackson13b50fe2008-07-30 13:07:27 +01001/*
2 * Copyright (C) 2006 Atmel Corporation
3 *
4 * Configuration settings for the AVR32 Network Gateway
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
Andreas Bießmann5d73bc72010-11-04 23:15:30 +000027#include <asm/arch/hardware.h>
Mark Jackson13b50fe2008-07-30 13:07:27 +010028
Andreas Bießmann2607ecf2011-04-18 04:12:42 +000029#define CONFIG_AVR32
30#define CONFIG_AT32AP
31#define CONFIG_AT32AP7000
32#define CONFIG_MIMC200
Mark Jackson13b50fe2008-07-30 13:07:27 +010033
Andreas Bießmann2607ecf2011-04-18 04:12:42 +000034#define CONFIG_MIMC200_EXT_FLASH
Mark Jackson13b50fe2008-07-30 13:07:27 +010035
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020036#define CONFIG_SYS_HZ 1000
Mark Jackson13b50fe2008-07-30 13:07:27 +010037
38/*
39 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
40 * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
41 * and the PBA bus to run at 1/4 the PLL frequency.
42 */
Andreas Bießmann2607ecf2011-04-18 04:12:42 +000043#define CONFIG_PLL
44#define CONFIG_SYS_POWER_MANAGER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020045#define CONFIG_SYS_OSC0_HZ 10000000
46#define CONFIG_SYS_PLL0_DIV 1
47#define CONFIG_SYS_PLL0_MUL 15
48#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
49#define CONFIG_SYS_CLKDIV_CPU 0
50#define CONFIG_SYS_CLKDIV_HSB 1
51#define CONFIG_SYS_CLKDIV_PBA 2
52#define CONFIG_SYS_CLKDIV_PBB 1
Mark Jackson13b50fe2008-07-30 13:07:27 +010053
Haavard Skinnemoen1f36f732010-08-12 13:52:54 +070054/* Reserve VM regions for SDRAM, NOR flash and FRAM */
55#define CONFIG_SYS_NR_VM_REGIONS 3
56
Mark Jackson13b50fe2008-07-30 13:07:27 +010057/*
58 * The PLLOPT register controls the PLL like this:
59 * icp = PLLOPT<2>
60 * ivco = PLLOPT<1:0>
61 *
62 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
63 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064#define CONFIG_SYS_PLL0_OPT 0x04
Mark Jackson13b50fe2008-07-30 13:07:27 +010065
Andreas Bießmannf4278b72010-11-04 23:15:31 +000066#define CONFIG_USART_BASE ATMEL_BASE_USART1
67#define CONFIG_USART_ID 1
68
Mark Jackson13b50fe2008-07-30 13:07:27 +010069#define CONFIG_MIMC200_DBGLINK 1
70
71/* User serviceable stuff */
Andreas Bießmann2607ecf2011-04-18 04:12:42 +000072#define CONFIG_DOS_PARTITION
Mark Jackson13b50fe2008-07-30 13:07:27 +010073
Andreas Bießmann2607ecf2011-04-18 04:12:42 +000074#define CONFIG_CMDLINE_TAG
75#define CONFIG_SETUP_MEMORY_TAGS
76#define CONFIG_INITRD_TAG
Mark Jackson13b50fe2008-07-30 13:07:27 +010077
78#define CONFIG_STACKSIZE (2048)
79
80#define CONFIG_BAUDRATE 115200
81#define CONFIG_BOOTARGS \
Mark Jacksonc0356a82009-08-17 16:42:52 +010082 "root=/dev/mtdblock1 rootfstype=jffs2 fbmem=512k console=ttyS1"
Mark Jackson13b50fe2008-07-30 13:07:27 +010083#define CONFIG_BOOTCOMMAND \
Mark Jacksona69a4232008-10-03 11:48:57 +010084 "fsload boot/uImage; bootm"
Mark Jackson13b50fe2008-07-30 13:07:27 +010085
Andreas Bießmann2607ecf2011-04-18 04:12:42 +000086#define CONFIG_SILENT_CONSOLE /* enable silent startup */
87#define CONFIG_DISABLE_CONSOLE /* disable console */
88#define CONFIG_SYS_DEVICE_NULLDEV /* include nulldev device */
Mark Jackson13b50fe2008-07-30 13:07:27 +010089
Mark Jacksonf68378d2009-07-21 11:35:22 +010090#define CONFIG_LCD 1
91
Mark Jackson13b50fe2008-07-30 13:07:27 +010092/*
93 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
94 * data on the serial line may interrupt the boot sequence.
95 */
96#define CONFIG_BOOTDELAY 0
Andreas Bießmann2607ecf2011-04-18 04:12:42 +000097#define CONFIG_ZERO_BOOTDELAY_CHECK
98#define CONFIG_AUTOBOOT
Mark Jackson13b50fe2008-07-30 13:07:27 +010099
100/*
101 * After booting the board for the first time, new ethernet addresses
102 * should be generated and assigned to the environment variables
103 * "ethaddr" and "eth1addr". This is normally done during production.
104 */
Andreas Bießmann2607ecf2011-04-18 04:12:42 +0000105#define CONFIG_OVERWRITE_ETHADDR_ONCE
Mark Jackson13b50fe2008-07-30 13:07:27 +0100106
107/*
108 * BOOTP/DHCP options
109 */
110#define CONFIG_BOOTP_SUBNETMASK
111#define CONFIG_BOOTP_GATEWAY
112
Mark Jackson13b50fe2008-07-30 13:07:27 +0100113/*
114 * Command line configuration.
115 */
116#include <config_cmd_default.h>
117
118#define CONFIG_CMD_ASKENV
119#define CONFIG_CMD_DHCP
120#define CONFIG_CMD_EXT2
121#define CONFIG_CMD_FAT
122#define CONFIG_CMD_JFFS2
123#define CONFIG_CMD_MMC
124#define CONFIG_CMD_NET
125
Andreas Bießmann2607ecf2011-04-18 04:12:42 +0000126#define CONFIG_ATMEL_USART
127#define CONFIG_MACB
128#define CONFIG_PORTMUX_PIO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_NR_PIOS 5
Andreas Bießmann2607ecf2011-04-18 04:12:42 +0000130#define CONFIG_SYS_HSDRAMC
131#define CONFIG_MMC
Sven Schnelle72fa4672011-10-21 14:49:25 +0200132#define CONFIG_GENERIC_ATMEL_MCI
133#define CONFIG_GENERIC_MMC
Mark Jackson13b50fe2008-07-30 13:07:27 +0100134
Mark Jacksonf68378d2009-07-21 11:35:22 +0100135#if defined(CONFIG_LCD)
136#define CONFIG_CMD_BMP
137#define CONFIG_ATMEL_LCD 1
138#define LCD_BPP LCD_COLOR16
139#define CONFIG_BMP_16BPP 1
140#define CONFIG_FB_ADDR 0x10600000
141#define CONFIG_WHITE_ON_BLACK 1
142#define CONFIG_VIDEO_BMP_GZIP 1
143#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE 262144
144#define CONFIG_ATMEL_LCD_BGR555 1
145#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
146#define CONFIG_SPLASH_SCREEN 1
147#endif
148
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_DCACHE_LINESZ 32
150#define CONFIG_SYS_ICACHE_LINESZ 32
Mark Jackson13b50fe2008-07-30 13:07:27 +0100151
152#define CONFIG_NR_DRAM_BANKS 1
153
Andreas Bießmann2607ecf2011-04-18 04:12:42 +0000154#define CONFIG_SYS_FLASH_CFI
155#define CONFIG_FLASH_CFI_DRIVER
Mark Jackson13b50fe2008-07-30 13:07:27 +0100156
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_FLASH_BASE 0x00000000
158#define CONFIG_SYS_FLASH_SIZE 0x800000
159#define CONFIG_SYS_MAX_FLASH_BANKS 1
160#define CONFIG_SYS_MAX_FLASH_SECT 135
Mark Jackson13b50fe2008-07-30 13:07:27 +0100161
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
Andreas Bießmannd85edc72011-04-18 04:12:46 +0000163#define CONFIG_SYS_TEXT_BASE 0x00000000
Mark Jackson13b50fe2008-07-30 13:07:27 +0100164
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
166#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
167#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
Mark Jackson13b50fe2008-07-30 13:07:27 +0100168
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_FRAM_BASE 0x08000000
170#define CONFIG_SYS_FRAM_SIZE 0x20000
Mark Jackson13b50fe2008-07-30 13:07:27 +0100171
Andreas Bießmann2607ecf2011-04-18 04:12:42 +0000172#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200173#define CONFIG_ENV_SIZE 65536
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
Mark Jackson13b50fe2008-07-30 13:07:27 +0100175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
Mark Jackson13b50fe2008-07-30 13:07:27 +0100177
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_MALLOC_LEN (1024*1024)
179#define CONFIG_SYS_DMA_ALLOC_LEN (16384)
Mark Jackson13b50fe2008-07-30 13:07:27 +0100180
181/* Allow 4MB for the kernel run-time image */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
183#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
Mark Jackson13b50fe2008-07-30 13:07:27 +0100184
185/* Other configuration settings that shouldn't have to change all that often */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_PROMPT "U-Boot> "
187#define CONFIG_SYS_CBSIZE 256
188#define CONFIG_SYS_MAXARGS 16
189#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
Andreas Bießmann2607ecf2011-04-18 04:12:42 +0000190#define CONFIG_SYS_LONGHELP
Mark Jackson13b50fe2008-07-30 13:07:27 +0100191
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
193#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000)
Mark Jackson13b50fe2008-07-30 13:07:27 +0100194
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
Mark Jackson13b50fe2008-07-30 13:07:27 +0100196
197#endif /* __CONFIG_H */