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Alex Dubova14a9442011-01-23 21:59:10 -08001/*
2 * Copyright 2011 Alex Dubov <oakad@yahoo.com>
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * Merury Computers MPQ101 board configuration file
25 *
26 */
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30#ifdef CONFIG_36BIT
31# define CONFIG_PHYS_64BIT
32#endif
33
34/* High Level Configuration Options */
35#define CONFIG_BOOKE /* BOOKE */
36#define CONFIG_E500 /* BOOKE e500 family */
37#define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */
38#define CONFIG_MPC8548 /* MPC8548 specific */
39#define CONFIG_MPQ101 /* MPQ101 board specific */
40
41#define CONFIG_SYS_SRIO /* enable serial RapidIO */
42#define CONFIG_TSEC_ENET /* tsec ethernet support */
43#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
44#define CONFIG_FSL_LAW /* Use common FSL init code */
45
46/*
47 * These can be toggled for performance analysis, otherwise use default.
48 */
49#define CONFIG_L2_CACHE /* toggle L2 cache */
50#define CONFIG_BTB /* toggle branch predition */
51
52#define CONFIG_PANIC_HANG
53
54/*
55 * Only possible on E500 Version 2 or newer cores.
56 */
57#define CONFIG_ENABLE_36BIT_PHYS
58
59#ifdef CONFIG_PHYS_64BIT
60# define CONFIG_ADDR_MAP
61# define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
62#endif
63
64
65#define CONFIG_SYS_CLK_FREQ 33000000 /* sysclk for MPC85xx */
66
Timur Tabie46fedf2011-08-04 18:03:41 -050067#define CONFIG_SYS_CCSRBAR 0xe0000000
68#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Alex Dubova14a9442011-01-23 21:59:10 -080069
70/* DDR Setup */
71#define CONFIG_FSL_DDR2
72
73#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
74
75#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
76#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
77#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
78
79#define CONFIG_NUM_DDR_CONTROLLERS 1
80#define CONFIG_DIMM_SLOTS_PER_CTLR 1
81#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
82
83/* Fixed 512MB DDR2 parameters */
84#define CONFIG_SYS_SDRAM_SIZE_LOG 29 /* DDR is 512MB */
85#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
86#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014102
87#define CONFIG_SYS_DDR_TIMING_3 0x00010000
88#define CONFIG_SYS_DDR_TIMING_0 0x00260802
89#define CONFIG_SYS_DDR_TIMING_1 0x5c47a432
90#define CONFIG_SYS_DDR_TIMING_1_PERF 0x49352322
91#define CONFIG_SYS_DDR_TIMING_2 0x03984cce
92#define CONFIG_SYS_DDR_TIMING_2_PERF 0x14904cca
93#define CONFIG_SYS_DDR_MODE_1 0x00400442
94#define CONFIG_SYS_DDR_MODE_1_PERF 0x00480432
95#define CONFIG_SYS_DDR_MODE_2 0x00000000
96#define CONFIG_SYS_DDR_MODE_2_PERF 0x00000000
97#define CONFIG_SYS_DDR_INTERVAL 0x08200100
98#define CONFIG_SYS_DDR_INTERVAL_PERF 0x06180100
99#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
100#define CONFIG_SYS_DDR_CONTROL 0xc3008000 /* Type = DDR2 */
101#define CONFIG_SYS_DDR_CONTROL2 0x04400000
102
103#define CONFIG_SYS_ALT_MEMTEST
104#define CONFIG_SYS_MEMTEST_START 0x0ff00000 /* memtest works on */
105#define CONFIG_SYS_MEMTEST_END 0x0ffffffc
106
107/*
108 * RAM definitions
109 */
110#define CONFIG_SYS_INIT_RAM_LOCK
111#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
112#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
113
114#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
115 - GENERATED_GBL_DATA_SIZE)
116#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
117
118#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
119#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
120
121/*
122 * Local Bus Definitions
123 */
124#define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */
125#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
126
127
128/*
129 * FLASH on the Local Bus
130 * One bank, 128M, using the CFI driver.
131 */
132#define CONFIG_SYS_BOOT_BLOCK 0xf8000000 /* boot TLB block */
133#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 128M */
134
135#ifdef CONFIG_PHYS_64BIT
136# define CONFIG_SYS_FLASH_BASE_PHYS 0xff8000000ull
137#else
138# define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
139#endif
140
141/* 0xf8001801 */
142#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
143 | BR_PS_32 | BR_V)
144
145/* 0xf8006ff7 */
146#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(128) | OR_GPCM_XAM | OR_GPCM_CSNT \
147 | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \
148 | OR_GPCM_SCY_15 | OR_GPCM_TRLX \
149 | OR_GPCM_EHTR | OR_GPCM_EAD)
150
151#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
152#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
153
154#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
155#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
156
157#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
158#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
159
160#define CONFIG_FLASH_CFI_DRIVER
161#define CONFIG_SYS_FLASH_CFI
162#define CONFIG_SYS_FLASH_EMPTY_INFO
163#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
164/*
165 * When initializing flash, if we cannot find the manufacturer ID,
166 * assume this is the AMD flash.
167 */
168#define CONFIG_ASSUME_AMD_FLASH
169
170/*
171 * Environment parameters
172 */
173#define CONFIG_ENV_IS_IN_FLASH
174#define CONFIG_ENV_OVERWRITE
175#define CONFIG_SYS_USE_PPCENV
176#define ENV_IS_EMBEDDED
177#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K */
178#define CONFIG_ENV_SIZE 0x800
179
180/* Environment at the start of flash sector, before text. */
181#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SIZE)
182#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
183#define CONFIG_SYS_TEXT_BASE 0xfffc0800
184#define CONFIG_SYS_LDSCRIPT "board/mercury/mpq101/u-boot.lds"
185
186/*
187 * Cypress CY7C67200 USB controller on the Local Bus.
188 * Not supported by u-boot at present.
189 */
190#define CONFIG_SYS_LBC_OPTION_BASE 0xf0000000
191
192#ifdef CONFIG_PHYS_64BIT
193# define CONFIG_SYS_LBC_OPTION_BASE_PHYS 0xff0000000ull
194#else
195# define CONFIG_SYS_LBC_OPTION_BASE_PHYS CONFIG_SYS_LBC_OPTION_BASE
196#endif
197
198/* 0xf0001001 */
199#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBC_OPTION_BASE_PHYS) \
200 | BR_PS_16 | BR_V)
201
202/* fffff002 */
203#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(0x8000) | OR_GPCM_XAM \
204 | OR_GPCM_BCTLD | OR_GPCM_EHTR)
205
206/*
207 * Serial Ports
208 */
209#define CONFIG_CONS_INDEX 2
210#define CONFIG_SYS_NS16550
211#define CONFIG_SYS_NS16550_SERIAL
212#define CONFIG_SYS_NS16550_REG_SIZE 1
213#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
214
215#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, 9600, \
216 19200, 38400, 115200}
217
218#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
219#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
220
221/*
222 * I2C buses and peripherals
223 */
224#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
225#define CONFIG_HARD_I2C /* I2C with hardware support*/
226#define CONFIG_I2C_MULTI_BUS
227#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
228#define CONFIG_SYS_I2C_SLAVE 0x7f
229#define CONFIG_SYS_I2C_OFFSET 0x3000
230#define CONFIG_SYS_I2C2_OFFSET 0x3100
231
232/* I2C RTC - M41T81 */
233#define CONFIG_RTC_M41T62
234#define CONFIG_SYS_I2C_RTC_ADDR 0x68
235#define CONFIG_SYS_M41T11_BASE_YEAR 2000
236
237/* I2C EEPROM - 24C256 */
238#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
239#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
240#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12
241#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
242#define CONFIG_SYS_EEPROM_BUS_NUM 1
243
244/*
245 * RapidIO MMU
246 */
247#ifdef CONFIG_SYS_SRIO
248# define CONFIG_SRIO1
249# define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000
250# define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
251
252# ifdef CONFIG_PHYS_64BIT
253# define CONFIG_SYS_SRIO1_MEM_PHYS 0xfc0000000ull
254# else
255# define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_VIRT
256# endif
257#endif
258
259/*
260 * Ethernet
261 */
262#ifdef CONFIG_TSEC_ENET
263
Alex Dubova14a9442011-01-23 21:59:10 -0800264# define CONFIG_MII /* MII PHY management */
265# define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
266
267# define CONFIG_TSEC1
268# define CONFIG_TSEC1_NAME "eTSEC0"
269# define TSEC1_PHY_ADDR 0x10
270# define TSEC1_PHYIDX 0
271# define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
272
273# define CONFIG_TSEC2
274# define CONFIG_TSEC2_NAME "eTSEC1"
275# define TSEC2_PHY_ADDR 0x11
276# define TSEC2_PHYIDX 0
277# define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
278
279# define CONFIG_TSEC3
280# define CONFIG_TSEC3_NAME "eTSEC2"
281# define TSEC3_PHY_ADDR 0x12
282# define TSEC3_PHYIDX 0
283# define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
284
285# define CONFIG_TSEC4
286# define CONFIG_TSEC4_NAME "eTSEC3"
287# define TSEC4_PHY_ADDR 0x13
288# define TSEC4_PHYIDX 0
289# define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
290
291/* Options are: eTSEC[0-3] */
292# define CONFIG_ETHPRIME "eTSEC0"
293# define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
294#endif
295
296/*
297 * Command line configuration.
298 */
299#include <config_cmd_default.h>
300
301#define CONFIG_CMD_DATE
302#define CONFIG_CMD_DHCP
303#define CONFIG_CMD_PING
304#define CONFIG_CMD_SNTP
305#define CONFIG_CMD_I2C
306#define CONFIG_CMD_EEPROM
307#define CONFIG_CMD_MII
308#define CONFIG_CMD_ELF
309#define CONFIG_CMD_IRQ
310#define CONFIG_CMD_SETEXPR
311#define CONFIG_CMD_JFFS2
312
313/*
314 * Miscellaneous configurable options
315 */
316
317/* pass open firmware flat tree */
318#define CONFIG_OF_LIBFDT
319#define CONFIG_OF_BOARD_SETUP
320#define CONFIG_OF_STDOUT_VIA_ALIAS
321
322#define CONFIG_FIT /* new uImage format support */
323#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
324
325/* Use the HUSH parser */
326#define CONFIG_SYS_HUSH_PARSER
327
Alex Dubova14a9442011-01-23 21:59:10 -0800328
329#define CONFIG_LOADS_ECHO /* echo on for serial download */
330#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
331
332#define CONFIG_SYS_LONGHELP /* undef to save memory */
333#define CONFIG_CMDLINE_EDITING /* Command-line editing */
334#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
335
336#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
337#define CONFIG_SYS_PROMPT "MPQ-101=> " /* Monitor Command Prompt */
338
339/* Console I/O Buffer Size */
340#ifdef CONFIG_CMD_KGDB
341# define CONFIG_SYS_CBSIZE 1024
342#else
343# define CONFIG_SYS_CBSIZE 256
344#endif
345
346/* Print Buffer Size */
347#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
348
349#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
350#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
351#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
352
353/*
354 * For booting Linux, the board info and command line data
355 * have to be in the first 16 MB of memory, since this is
356 * the maximum mapped by the Linux kernel during initialization.
357 */
358#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
359#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
360
361#ifdef CONFIG_CMD_KGDB
362# define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
363# define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
364#endif
365
366/*
367 * Basic Environment Configuration
368 */
369#define CONFIG_BAUDRATE 115200
370#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
371
372/*default location for tftp and bootm*/
373#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
374
375#endif /* __CONFIG_H */