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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Wolfgang Denkff7fefe2006-03-13 12:37:35 +01002/*
3 * (C) Copyright 2003
4 * Texas Instruments <www.ti.com>
5 *
6 * (C) Copyright 2002
7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 * Marius Groeger <mgroeger@sysgo.de>
9 *
10 * (C) Copyright 2002
11 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
12 * Alex Zuepke <azu@sysgo.de>
13 *
14 * (C) Copyright 2002-2004
Detlev Zundel792a09e2009-05-13 10:54:10 +020015 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
Wolfgang Denkff7fefe2006-03-13 12:37:35 +010016 *
17 * (C) Copyright 2004
18 * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
Wolfgang Denkff7fefe2006-03-13 12:37:35 +010019 */
20
21#include <common.h>
Wolfgang Denkff7fefe2006-03-13 12:37:35 +010022
Gururaja Hebbar K Re8f12072008-08-25 11:11:34 +020023#define TIMER_ENABLE (1 << 7)
24#define TIMER_MODE_MSK (1 << 6)
25#define TIMER_MODE_FR (0 << 6)
26#define TIMER_MODE_PD (1 << 6)
27
28#define TIMER_INT_EN (1 << 5)
29#define TIMER_PRS_MSK (3 << 2)
30#define TIMER_PRS_8S (1 << 3)
31#define TIMER_SIZE_MSK (1 << 2)
32#define TIMER_ONE_SHT (1 << 0)
33
Wolfgang Denkff7fefe2006-03-13 12:37:35 +010034int timer_init (void)
35{
Gururaja Hebbar K Re8f12072008-08-25 11:11:34 +020036 ulong tmr_ctrl_val;
37
38 /* 1st disable the Timer */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020039 tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8);
Gururaja Hebbar K Re8f12072008-08-25 11:11:34 +020040 tmr_ctrl_val &= ~TIMER_ENABLE;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041 *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
Gururaja Hebbar K Re8f12072008-08-25 11:11:34 +020042
43 /*
44 * The Timer Control Register has one Undefined/Shouldn't Use Bit
45 * So we should do read/modify/write Operation
46 */
47
48 /*
49 * Timer Mode : Free Running
50 * Interrupt : Disabled
51 * Prescale : 8 Stage, Clk/256
52 * Tmr Siz : 16 Bit Counter
53 * Tmr in Wrapping Mode
54 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055 tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8);
Gururaja Hebbar K Re8f12072008-08-25 11:11:34 +020056 tmr_ctrl_val &= ~(TIMER_MODE_MSK | TIMER_INT_EN | TIMER_PRS_MSK | TIMER_SIZE_MSK | TIMER_ONE_SHT );
57 tmr_ctrl_val |= (TIMER_ENABLE | TIMER_PRS_8S);
58
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059 *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
Wolfgang Denkff7fefe2006-03-13 12:37:35 +010060
Wolfgang Denkff7fefe2006-03-13 12:37:35 +010061 return 0;
62}