| Christophe Leroy | 4d0c8db | 2023-04-04 13:09:36 +0200 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * CMPC885 Device Tree Source |
| 4 | * |
| 5 | * Copyright 2020 CS GROUP France |
| 6 | * |
| 7 | */ |
| 8 | |
| 9 | /dts-v1/; |
| 10 | |
| 11 | #include <dt-bindings/clk/mpc83xx-clk.h> |
| 12 | |
| 13 | / { |
| 14 | model = "CMPCPRO"; |
| 15 | compatible = "fsl, cmpc85xx", "fsl,mod85xx", "CMPCPRO", "MPC8321E", "fsl,cmpcpro"; |
| 16 | #address-cells = <1>; |
| 17 | #size-cells = <1>; |
| 18 | |
| 19 | chosen { |
| 20 | stdout-path = &serial0; |
| 21 | }; |
| 22 | WDT: watchdog@0 { |
| 23 | device_type = "watchdog"; |
| 24 | compatible = "fsl,pq1-wdt"; |
| 25 | }; |
| 26 | |
| 27 | aliases { |
| 28 | ethernet0 = ð0; |
| 29 | etehrnet1 = ð1; |
| 30 | serial0 = &serial0; |
| 31 | }; |
| 32 | |
| 33 | cpus { |
| 34 | #address-cells = <1>; |
| 35 | #size-cells = <0>; |
| 36 | PowerPC,8321@0 { |
| 37 | device_type = "cpu"; |
| 38 | reg = <0x0>; |
| 39 | d-cache-line-size = <0x20>; // 32 bytes |
| 40 | i-cache-line-size = <0x20>; // 32 bytes |
| 41 | d-cache-size = <16384>; // L1, 16K |
| 42 | i-cache-size = <16384>; // L1, 16K |
| 43 | timebase-frequency = <0>; |
| 44 | bus-frequency = <0>; |
| 45 | clock-frequency = <0>; |
| 46 | }; |
| 47 | }; |
| 48 | |
| 49 | memory { |
| 50 | device_type = "memory"; |
| 51 | reg = <0x00000000 0x20000000>; |
| 52 | }; |
| 53 | |
| 54 | soc8321@b0000000 { |
| 55 | #address-cells = <1>; |
| 56 | #size-cells = <1>; |
| 57 | device_type = "soc"; |
| 58 | compatible = "simple-bus"; |
| 59 | ranges = <0x0 0xb0000000 0x00100000>; |
| 60 | reg = <0xb0000000 0x00000200>; |
| 61 | bus-frequency = <0>; |
| 62 | pmc: power@b00 { |
| 63 | compatible = "fsl,mpc8323-pmc", "fsl,mpc8349-pmc"; |
| 64 | reg = <0xb00 0x100 0xa00 0x100>; |
| 65 | interrupts = <80 0x8>; |
| 66 | interrupt-parent = <&ipic>; |
| 67 | }; |
| 68 | serial0: serial@4500 { |
| 69 | clocks = <&socclocks MPC83XX_CLK_CSB>; |
| 70 | cell-index = <0>; |
| 71 | device_type = "serial"; |
| 72 | compatible = "fsl,ns16550", "ns16550"; |
| 73 | reg = <0x4500 0x100>; |
| 74 | clock-frequency = <0>; |
| 75 | interrupts = <9 0x8>; |
| 76 | interrupt-parent = <&ipic>; |
| 77 | }; |
| 78 | ipic:pic@700 { |
| 79 | interrupt-controller; |
| 80 | #address-cells = <0>; |
| 81 | #interrupt-cells = <2>; |
| 82 | reg = <0x700 0x100>; |
| 83 | device_type = "ipic"; |
| 84 | }; |
| 85 | par_io@1400 { |
| 86 | #address-cells = <1>; |
| 87 | #size-cells = <1>; |
| 88 | reg = <0x1400 0x100>; |
| 89 | ranges; |
| 90 | compatible = "fsl,mpc8323-qe-pario","simple-bus"; |
| 91 | device_type = "par_io"; |
| 92 | num-ports = <7>; |
| 93 | qe_pio_a: gpio-controller@1400 { |
| 94 | #gpio-cells = <2>; |
| 95 | compatible = "fsl,mpc8323-qe-pario-bank","fsl,mpc8308-gpio"; |
| 96 | reg = <0x1400 0x18>; |
| 97 | gpio-controller; |
| 98 | }; |
| 99 | qe_pio_b: gpio-controller@1418 { |
| 100 | #gpio-cells = <2>; |
| 101 | compatible = "fsl,mpc8323-qe-pario-bank","fsl,mpc8308-gpio"; |
| 102 | reg = <0x1418 0x18>; |
| 103 | gpio-controller; |
| 104 | }; |
| 105 | qe_pio_c: gpio-controller@1430 { |
| 106 | #gpio-cells = <2>; |
| 107 | compatible = "fsl,mpc8323-qe-pario-bank","fsl,mpc8308-gpio"; |
| 108 | reg = <0x1430 0x18>; |
| 109 | gpio-controller; |
| 110 | }; |
| 111 | qe_pio_d: gpio-controller@1448 { |
| 112 | #gpio-cells = <2>; |
| 113 | compatible = "fsl,mpc8323-qe-pario-bank","fsl,mpc8308-gpio"; |
| 114 | reg = <0x1448 0x18>; |
| 115 | gpio-controller; |
| 116 | }; |
| 117 | }; |
| 118 | }; |
| 119 | socclocks: clocks { |
| 120 | bootph-all; |
| 121 | compatible = "fsl,mpc832x-clk"; |
| 122 | #clock-cells = <1>; |
| 123 | }; |
| 124 | qe@b0100000 { |
| 125 | #address-cells = <1>; |
| 126 | #size-cells = <1>; |
| 127 | device_type = "qe"; |
| 128 | compatible = "fsl,qe","simple-bus"; |
| 129 | ranges = <0x0 0xb0100000 0x00100000>; |
| 130 | reg = <0xb0100000 0x480>; |
| 131 | brg-frequency = <0>; |
| 132 | bus-frequency = <198000000>; |
| 133 | fsl,qe-num-riscs = <1>; |
| 134 | fsl,qe-num-snums = <28>; |
| 135 | spi@4c0 { |
| 136 | clocks = <&socclocks MPC83XX_CLK_CSB>; |
| 137 | #address-cells = <1>; |
| 138 | #size-cells = <0>; |
| 139 | cell-index = <0>; |
| 140 | compatible = "fsl,mpc832x-spi"; |
| 141 | reg = <0x4c0 0x40>; |
| 142 | mode = "cpu"; |
| 143 | gpios = <&qe_pio_d 3 1>; |
| 144 | clock-frequency = <0>; |
| 145 | eeprom@3 { |
| 146 | compatible = "atmel,at25", "cs,eeprom"; |
| 147 | cell-index = <1>; |
| 148 | }; |
| 149 | }; |
| 150 | eth0: ucc@3000 { |
| 151 | device_type = "network"; |
| 152 | compatible = "ucc_geth"; |
| 153 | cell-index = <2>; |
| 154 | reg = <0x3000 0x200>; |
| 155 | rx-clock-name = "clk17"; |
| 156 | tx-clock-name = "clk17"; |
| 157 | phy-handle = <&phy1>; |
| 158 | phy-connection-type = "rmii"; |
| 159 | }; |
| 160 | eth1: ucc@2200 { |
| 161 | device_type = "network"; |
| 162 | compatible = "ucc_geth"; |
| 163 | cell-index = <3>; |
| 164 | reg = <0x2200 0x200>; |
| 165 | rx-clock-name = "clk12"; |
| 166 | tx-clock-name = "clk12"; |
| 167 | phy-handle = <&phy2>; |
| 168 | phy-connection-type = "rmii"; |
| 169 | }; |
| 170 | mdio@3120 { |
| 171 | #address-cells = <1>; |
| 172 | #size-cells = <0>; |
| 173 | reg = <0x3120 0x18>; |
| 174 | compatible = "fsl,ucc-mdio"; |
| 175 | phy1:ethernet-phy@1 { |
| 176 | interrupt-parent = <&ipic>; |
| 177 | reg = <0x1>; |
| 178 | interrupts = <17 8>; |
| 179 | device_type = "ethernet-phy"; |
| 180 | }; |
| 181 | phy2:ethernet-phy@2 { |
| 182 | interrupt-parent = <&ipic>; |
| 183 | reg = <0x2>; |
| 184 | interrupts = <17 8>; |
| 185 | device_type = "ethernet-phy"; |
| 186 | }; |
| 187 | }; |
| 188 | }; |
| 189 | }; |