blob: 7a7575b26861d91d4e35381ef080a7238aee06b6 [file] [log] [blame]
wdenk5653fc32004-02-08 22:55:38 +00001/*
wdenkbf9e3b32004-02-12 00:47:09 +00002 * (C) Copyright 2002-2004
wdenk5653fc32004-02-08 22:55:38 +00003 * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
4 *
5 * Copyright (C) 2003 Arabella Software Ltd.
6 * Yuli Barcohen <yuli@arabellasw.com>
7 * Modified to work with AMD flashes
8 *
wdenkbf9e3b32004-02-12 00:47:09 +00009 * Copyright (C) 2004
10 * Ed Okerson
11 * Modified to work with little-endian systems.
12 *
wdenk5653fc32004-02-08 22:55:38 +000013 * See file CREDITS for list of people who contributed to this
14 * project.
15 *
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * MA 02111-1307 USA
30 *
31 * History
32 * 01/20/2004 - combined variants of original driver.
wdenkbf9e3b32004-02-12 00:47:09 +000033 * 01/22/2004 - Write performance enhancements for parallel chips (Tolunay)
34 * 01/23/2004 - Support for x8/x16 chips (Rune Raknerud)
35 * 01/27/2004 - Little endian support Ed Okerson
wdenk5653fc32004-02-08 22:55:38 +000036 *
37 * Tested Architectures
wdenkbf9e3b32004-02-12 00:47:09 +000038 * Port Width Chip Width # of banks Flash Chip Board
wdenk2d1a5372004-02-23 19:30:57 +000039 * 32 16 1 28F128J3 seranoa/eagle
40 * 64 16 1 28F128J3 seranoa/falcon
wdenkcd37d9e2004-02-10 00:03:41 +000041 *
wdenk5653fc32004-02-08 22:55:38 +000042 */
43
44/* The DEBUG define must be before common to enable debugging */
wdenk2d1a5372004-02-23 19:30:57 +000045/* #define DEBUG */
46
wdenk5653fc32004-02-08 22:55:38 +000047#include <common.h>
48#include <asm/processor.h>
wdenk028ab6b2004-02-23 23:54:43 +000049#include <linux/byteorder/swab.h>
wdenkbf9e3b32004-02-12 00:47:09 +000050#ifdef CFG_FLASH_CFI_DRIVER
wdenk028ab6b2004-02-23 23:54:43 +000051
wdenk5653fc32004-02-08 22:55:38 +000052/*
53 * This file implements a Common Flash Interface (CFI) driver for U-Boot.
54 * The width of the port and the width of the chips are determined at initialization.
55 * These widths are used to calculate the address for access CFI data structures.
56 * It has been tested on an Intel Strataflash implementation and AMD 29F016D.
57 *
58 * References
59 * JEDEC Standard JESD68 - Common Flash Interface (CFI)
60 * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
61 * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
62 * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
63 *
64 * TODO
65 *
66 * Use Primary Extended Query table (PRI) and Alternate Algorithm Query
67 * Table (ALT) to determine if protection is available
68 *
69 * Add support for other command sets Use the PRI and ALT to determine command set
70 * Verify erase and program timeouts.
71 */
72
wdenkbf9e3b32004-02-12 00:47:09 +000073#ifndef CFG_FLASH_BANKS_LIST
74#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
75#endif
76
wdenk5653fc32004-02-08 22:55:38 +000077#define FLASH_CMD_CFI 0x98
78#define FLASH_CMD_READ_ID 0x90
79#define FLASH_CMD_RESET 0xff
80#define FLASH_CMD_BLOCK_ERASE 0x20
81#define FLASH_CMD_ERASE_CONFIRM 0xD0
82#define FLASH_CMD_WRITE 0x40
83#define FLASH_CMD_PROTECT 0x60
84#define FLASH_CMD_PROTECT_SET 0x01
85#define FLASH_CMD_PROTECT_CLEAR 0xD0
86#define FLASH_CMD_CLEAR_STATUS 0x50
wdenkbf9e3b32004-02-12 00:47:09 +000087#define FLASH_CMD_WRITE_TO_BUFFER 0xE8
88#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
wdenk5653fc32004-02-08 22:55:38 +000089
90#define FLASH_STATUS_DONE 0x80
91#define FLASH_STATUS_ESS 0x40
92#define FLASH_STATUS_ECLBS 0x20
93#define FLASH_STATUS_PSLBS 0x10
94#define FLASH_STATUS_VPENS 0x08
95#define FLASH_STATUS_PSS 0x04
96#define FLASH_STATUS_DPS 0x02
97#define FLASH_STATUS_R 0x01
98#define FLASH_STATUS_PROTECT 0x01
99
100#define AMD_CMD_RESET 0xF0
101#define AMD_CMD_WRITE 0xA0
102#define AMD_CMD_ERASE_START 0x80
103#define AMD_CMD_ERASE_SECTOR 0x30
104
105#define AMD_STATUS_TOGGLE 0x40
106#define AMD_STATUS_ERROR 0x20
107
108#define FLASH_OFFSET_CFI 0x55
109#define FLASH_OFFSET_CFI_RESP 0x10
wdenkbf9e3b32004-02-12 00:47:09 +0000110#define FLASH_OFFSET_PRIMARY_VENDOR 0x13
wdenk5653fc32004-02-08 22:55:38 +0000111#define FLASH_OFFSET_WTOUT 0x1F
wdenkbf9e3b32004-02-12 00:47:09 +0000112#define FLASH_OFFSET_WBTOUT 0x20
wdenk5653fc32004-02-08 22:55:38 +0000113#define FLASH_OFFSET_ETOUT 0x21
wdenkbf9e3b32004-02-12 00:47:09 +0000114#define FLASH_OFFSET_CETOUT 0x22
wdenk5653fc32004-02-08 22:55:38 +0000115#define FLASH_OFFSET_WMAX_TOUT 0x23
wdenkbf9e3b32004-02-12 00:47:09 +0000116#define FLASH_OFFSET_WBMAX_TOUT 0x24
wdenk5653fc32004-02-08 22:55:38 +0000117#define FLASH_OFFSET_EMAX_TOUT 0x25
wdenkbf9e3b32004-02-12 00:47:09 +0000118#define FLASH_OFFSET_CEMAX_TOUT 0x26
wdenk5653fc32004-02-08 22:55:38 +0000119#define FLASH_OFFSET_SIZE 0x27
wdenkbf9e3b32004-02-12 00:47:09 +0000120#define FLASH_OFFSET_INTERFACE 0x28
121#define FLASH_OFFSET_BUFFER_SIZE 0x2A
wdenk5653fc32004-02-08 22:55:38 +0000122#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
123#define FLASH_OFFSET_ERASE_REGIONS 0x2D
124#define FLASH_OFFSET_PROTECT 0x02
wdenkbf9e3b32004-02-12 00:47:09 +0000125#define FLASH_OFFSET_USER_PROTECTION 0x85
126#define FLASH_OFFSET_INTEL_PROTECTION 0x81
wdenk5653fc32004-02-08 22:55:38 +0000127
128
129#define FLASH_MAN_CFI 0x01000000
130
wdenkbf9e3b32004-02-12 00:47:09 +0000131#define CFI_CMDSET_NONE 0
wdenk5653fc32004-02-08 22:55:38 +0000132#define CFI_CMDSET_INTEL_EXTENDED 1
wdenkbf9e3b32004-02-12 00:47:09 +0000133#define CFI_CMDSET_AMD_STANDARD 2
wdenk5653fc32004-02-08 22:55:38 +0000134#define CFI_CMDSET_INTEL_STANDARD 3
wdenkbf9e3b32004-02-12 00:47:09 +0000135#define CFI_CMDSET_AMD_EXTENDED 4
wdenk5653fc32004-02-08 22:55:38 +0000136#define CFI_CMDSET_MITSU_STANDARD 256
137#define CFI_CMDSET_MITSU_EXTENDED 257
wdenkbf9e3b32004-02-12 00:47:09 +0000138#define CFI_CMDSET_SST 258
wdenk5653fc32004-02-08 22:55:38 +0000139
140
141typedef union {
142 unsigned char c;
143 unsigned short w;
144 unsigned long l;
145 unsigned long long ll;
146} cfiword_t;
147
148typedef union {
wdenkbf9e3b32004-02-12 00:47:09 +0000149 volatile unsigned char *cp;
wdenk5653fc32004-02-08 22:55:38 +0000150 volatile unsigned short *wp;
wdenkbf9e3b32004-02-12 00:47:09 +0000151 volatile unsigned long *lp;
wdenk5653fc32004-02-08 22:55:38 +0000152 volatile unsigned long long *llp;
153} cfiptr_t;
154
155#define NUM_ERASE_REGIONS 4
156
157static ulong bank_base[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST;
158
wdenkbf9e3b32004-02-12 00:47:09 +0000159flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
wdenk5653fc32004-02-08 22:55:38 +0000160
161/*-----------------------------------------------------------------------
162 * Functions
163 */
164
165typedef unsigned long flash_sect_t;
166
wdenkbf9e3b32004-02-12 00:47:09 +0000167static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c);
168static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf);
wdenk028ab6b2004-02-23 23:54:43 +0000169static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
wdenkbf9e3b32004-02-12 00:47:09 +0000170static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect);
wdenk028ab6b2004-02-23 23:54:43 +0000171static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
172static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
173static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
wdenkbf9e3b32004-02-12 00:47:09 +0000174static int flash_detect_cfi (flash_info_t * info);
wdenk5653fc32004-02-08 22:55:38 +0000175static ulong flash_get_size (ulong base, int banknum);
wdenk028ab6b2004-02-23 23:54:43 +0000176static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword);
wdenkbf9e3b32004-02-12 00:47:09 +0000177static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
178 ulong tout, char *prompt);
wdenk5653fc32004-02-08 22:55:38 +0000179#ifdef CFG_FLASH_USE_BUFFER_WRITE
wdenk028ab6b2004-02-23 23:54:43 +0000180static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, int len);
wdenk5653fc32004-02-08 22:55:38 +0000181#endif
182
wdenk5653fc32004-02-08 22:55:38 +0000183/*-----------------------------------------------------------------------
184 * create an address based on the offset and the port width
185 */
wdenk028ab6b2004-02-23 23:54:43 +0000186inline uchar *flash_make_addr (flash_info_t * info, flash_sect_t sect, uint offset)
wdenk5653fc32004-02-08 22:55:38 +0000187{
wdenkbf9e3b32004-02-12 00:47:09 +0000188 return ((uchar *) (info->start[sect] + (offset * info->portwidth)));
wdenk5653fc32004-02-08 22:55:38 +0000189}
wdenkbf9e3b32004-02-12 00:47:09 +0000190
191#ifdef DEBUG
192/*-----------------------------------------------------------------------
193 * Debug support
194 */
195void print_longlong (char *str, unsigned long long data)
196{
197 int i;
198 char *cp;
199
200 cp = (unsigned char *) &data;
201 for (i = 0; i < 8; i++)
202 sprintf (&str[i * 2], "%2.2x", *cp++);
203}
204static void flash_printqry (flash_info_t * info, flash_sect_t sect)
205{
206 cfiptr_t cptr;
207 int x, y;
208
209 for (x = 0; x < 0x40; x += 16 / info->portwidth) {
210 cptr.cp =
211 flash_make_addr (info, sect,
212 x + FLASH_OFFSET_CFI_RESP);
213 debug ("%p : ", cptr.cp);
214 for (y = 0; y < 16; y++) {
215 debug ("%2.2x ", cptr.cp[y]);
216 }
217 debug (" ");
218 for (y = 0; y < 16; y++) {
219 if (cptr.cp[y] >= 0x20 && cptr.cp[y] <= 0x7e) {
220 debug ("%c", cptr.cp[y]);
221 } else {
222 debug (".");
223 }
224 }
225 debug ("\n");
226 }
227}
wdenkbf9e3b32004-02-12 00:47:09 +0000228#endif
229
230
wdenk5653fc32004-02-08 22:55:38 +0000231/*-----------------------------------------------------------------------
232 * read a character at a port width address
233 */
wdenkbf9e3b32004-02-12 00:47:09 +0000234inline uchar flash_read_uchar (flash_info_t * info, uint offset)
wdenk5653fc32004-02-08 22:55:38 +0000235{
236 uchar *cp;
wdenkbf9e3b32004-02-12 00:47:09 +0000237
238 cp = flash_make_addr (info, 0, offset);
239#if defined(__LITTLE_ENDIAN)
240 return (cp[0]);
241#else
wdenk5653fc32004-02-08 22:55:38 +0000242 return (cp[info->portwidth - 1]);
wdenkbf9e3b32004-02-12 00:47:09 +0000243#endif
wdenk5653fc32004-02-08 22:55:38 +0000244}
245
246/*-----------------------------------------------------------------------
247 * read a short word by swapping for ppc format.
248 */
wdenkbf9e3b32004-02-12 00:47:09 +0000249ushort flash_read_ushort (flash_info_t * info, flash_sect_t sect, uint offset)
wdenk5653fc32004-02-08 22:55:38 +0000250{
wdenkbf9e3b32004-02-12 00:47:09 +0000251 uchar *addr;
252 ushort retval;
wdenk5653fc32004-02-08 22:55:38 +0000253
wdenkbf9e3b32004-02-12 00:47:09 +0000254#ifdef DEBUG
255 int x;
256#endif
257 addr = flash_make_addr (info, sect, offset);
wdenk5653fc32004-02-08 22:55:38 +0000258
wdenkbf9e3b32004-02-12 00:47:09 +0000259#ifdef DEBUG
260 debug ("ushort addr is at %p info->portwidth = %d\n", addr,
261 info->portwidth);
262 for (x = 0; x < 2 * info->portwidth; x++) {
263 debug ("addr[%x] = 0x%x\n", x, addr[x]);
264 }
265#endif
266#if defined(__LITTLE_ENDIAN)
267 retval = ((addr[(info->portwidth)] << 8) | addr[0]);
268#else
269 retval = ((addr[(2 * info->portwidth) - 1] << 8) |
270 addr[info->portwidth - 1]);
271#endif
272
273 debug ("retval = 0x%x\n", retval);
274 return retval;
wdenk5653fc32004-02-08 22:55:38 +0000275}
276
277/*-----------------------------------------------------------------------
278 * read a long word by picking the least significant byte of each maiximum
279 * port size word. Swap for ppc format.
280 */
wdenkbf9e3b32004-02-12 00:47:09 +0000281ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset)
wdenk5653fc32004-02-08 22:55:38 +0000282{
wdenkbf9e3b32004-02-12 00:47:09 +0000283 uchar *addr;
284 ulong retval;
wdenk5653fc32004-02-08 22:55:38 +0000285
wdenkbf9e3b32004-02-12 00:47:09 +0000286#ifdef DEBUG
287 int x;
288#endif
289 addr = flash_make_addr (info, sect, offset);
290
291#ifdef DEBUG
292 debug ("long addr is at %p info->portwidth = %d\n", addr,
293 info->portwidth);
294 for (x = 0; x < 4 * info->portwidth; x++) {
295 debug ("addr[%x] = 0x%x\n", x, addr[x]);
296 }
297#endif
298#if defined(__LITTLE_ENDIAN)
299 retval = (addr[0] << 16) | (addr[(info->portwidth)] << 24) |
wdenk028ab6b2004-02-23 23:54:43 +0000300 (addr[(2 * info->portwidth)]) | (addr[(3 * info->portwidth)] << 8);
wdenkbf9e3b32004-02-12 00:47:09 +0000301#else
302 retval = (addr[(2 * info->portwidth) - 1] << 24) |
303 (addr[(info->portwidth) - 1] << 16) |
304 (addr[(4 * info->portwidth) - 1] << 8) |
305 addr[(3 * info->portwidth) - 1];
306#endif
307 return retval;
wdenk5653fc32004-02-08 22:55:38 +0000308}
309
310/*-----------------------------------------------------------------------
311 */
312unsigned long flash_init (void)
313{
314 unsigned long size = 0;
315 int i;
316
317 /* Init: no FLASHes known */
wdenkbf9e3b32004-02-12 00:47:09 +0000318 for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
wdenk5653fc32004-02-08 22:55:38 +0000319 flash_info[i].flash_id = FLASH_UNKNOWN;
wdenkbf9e3b32004-02-12 00:47:09 +0000320 size += flash_info[i].size = flash_get_size (bank_base[i], i);
wdenk5653fc32004-02-08 22:55:38 +0000321 if (flash_info[i].flash_id == FLASH_UNKNOWN) {
wdenk028ab6b2004-02-23 23:54:43 +0000322 printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
323 i, flash_info[i].size, flash_info[i].size << 20);
wdenk5653fc32004-02-08 22:55:38 +0000324 }
325 }
326
327 /* Monitor protection ON by default */
328#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
wdenkbf9e3b32004-02-12 00:47:09 +0000329 flash_protect (FLAG_PROTECT_SET,
330 CFG_MONITOR_BASE,
331 CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
332 &flash_info[0]);
wdenk5653fc32004-02-08 22:55:38 +0000333#endif
334
335 return (size);
336}
337
338/*-----------------------------------------------------------------------
339 */
wdenkbf9e3b32004-02-12 00:47:09 +0000340int flash_erase (flash_info_t * info, int s_first, int s_last)
wdenk5653fc32004-02-08 22:55:38 +0000341{
342 int rcode = 0;
343 int prot;
344 flash_sect_t sect;
345
wdenkbf9e3b32004-02-12 00:47:09 +0000346 if (info->flash_id != FLASH_MAN_CFI) {
wdenk5653fc32004-02-08 22:55:38 +0000347 printf ("Can't erase unknown flash type - aborted\n");
348 return 1;
349 }
350 if ((s_first < 0) || (s_first > s_last)) {
351 printf ("- no sectors to erase\n");
352 return 1;
353 }
354
355 prot = 0;
wdenkbf9e3b32004-02-12 00:47:09 +0000356 for (sect = s_first; sect <= s_last; ++sect) {
wdenk5653fc32004-02-08 22:55:38 +0000357 if (info->protect[sect]) {
358 prot++;
359 }
360 }
361 if (prot) {
wdenkbf9e3b32004-02-12 00:47:09 +0000362 printf ("- Warning: %d protected sectors will not be erased!\n", prot);
wdenk5653fc32004-02-08 22:55:38 +0000363 } else {
364 printf ("\n");
365 }
366
367
wdenkbf9e3b32004-02-12 00:47:09 +0000368 for (sect = s_first; sect <= s_last; sect++) {
wdenk5653fc32004-02-08 22:55:38 +0000369 if (info->protect[sect] == 0) { /* not protected */
wdenkbf9e3b32004-02-12 00:47:09 +0000370 switch (info->vendor) {
wdenk5653fc32004-02-08 22:55:38 +0000371 case CFI_CMDSET_INTEL_STANDARD:
372 case CFI_CMDSET_INTEL_EXTENDED:
wdenk028ab6b2004-02-23 23:54:43 +0000373 flash_write_cmd (info, sect, 0, FLASH_CMD_CLEAR_STATUS);
374 flash_write_cmd (info, sect, 0, FLASH_CMD_BLOCK_ERASE);
375 flash_write_cmd (info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
wdenk5653fc32004-02-08 22:55:38 +0000376 break;
377 case CFI_CMDSET_AMD_STANDARD:
378 case CFI_CMDSET_AMD_EXTENDED:
wdenkbf9e3b32004-02-12 00:47:09 +0000379 flash_unlock_seq (info, sect);
wdenk028ab6b2004-02-23 23:54:43 +0000380 flash_write_cmd (info, sect, 0x555, AMD_CMD_ERASE_START);
wdenkbf9e3b32004-02-12 00:47:09 +0000381 flash_unlock_seq (info, sect);
wdenk028ab6b2004-02-23 23:54:43 +0000382 flash_write_cmd (info, sect, 0, AMD_CMD_ERASE_SECTOR);
wdenk5653fc32004-02-08 22:55:38 +0000383 break;
384 default:
wdenkbf9e3b32004-02-12 00:47:09 +0000385 debug ("Unkown flash vendor %d\n",
386 info->vendor);
wdenk5653fc32004-02-08 22:55:38 +0000387 break;
388 }
389
wdenkbf9e3b32004-02-12 00:47:09 +0000390 if (flash_full_status_check
391 (info, sect, info->erase_blk_tout, "erase")) {
wdenk5653fc32004-02-08 22:55:38 +0000392 rcode = 1;
393 } else
wdenkbf9e3b32004-02-12 00:47:09 +0000394 printf (".");
wdenk5653fc32004-02-08 22:55:38 +0000395 }
396 }
397 printf (" done\n");
398 return rcode;
399}
400
401/*-----------------------------------------------------------------------
402 */
wdenkbf9e3b32004-02-12 00:47:09 +0000403void flash_print_info (flash_info_t * info)
wdenk5653fc32004-02-08 22:55:38 +0000404{
405 int i;
406
407 if (info->flash_id != FLASH_MAN_CFI) {
408 printf ("missing or unknown FLASH type\n");
409 return;
410 }
411
wdenkbf9e3b32004-02-12 00:47:09 +0000412 printf ("CFI conformant FLASH (%d x %d)",
413 (info->portwidth << 3), (info->chipwidth << 3));
wdenk5653fc32004-02-08 22:55:38 +0000414 printf (" Size: %ld MB in %d Sectors\n",
415 info->size >> 20, info->sector_count);
wdenk028ab6b2004-02-23 23:54:43 +0000416 printf (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
417 info->erase_blk_tout,
418 info->write_tout,
419 info->buffer_write_tout,
420 info->buffer_size);
wdenk5653fc32004-02-08 22:55:38 +0000421
422 printf (" Sector Start Addresses:");
wdenkbf9e3b32004-02-12 00:47:09 +0000423 for (i = 0; i < info->sector_count; ++i) {
wdenk5653fc32004-02-08 22:55:38 +0000424#ifdef CFG_FLASH_EMPTY_INFO
425 int k;
426 int size;
427 int erased;
428 volatile unsigned long *flash;
429
430 /*
431 * Check if whole sector is erased
432 */
wdenkbf9e3b32004-02-12 00:47:09 +0000433 if (i != (info->sector_count - 1))
434 size = info->start[i + 1] - info->start[i];
wdenk5653fc32004-02-08 22:55:38 +0000435 else
wdenkbf9e3b32004-02-12 00:47:09 +0000436 size = info->start[0] + info->size - info->start[i];
wdenk5653fc32004-02-08 22:55:38 +0000437 erased = 1;
wdenkbf9e3b32004-02-12 00:47:09 +0000438 flash = (volatile unsigned long *) info->start[i];
439 size = size >> 2; /* divide by 4 for longword access */
440 for (k = 0; k < size; k++) {
441 if (*flash++ != 0xffffffff) {
442 erased = 0;
443 break;
444 }
445 }
wdenk5653fc32004-02-08 22:55:38 +0000446
447 if ((i % 5) == 0)
448 printf ("\n");
449 /* print empty and read-only info */
450 printf (" %08lX%s%s",
451 info->start[i],
452 erased ? " E" : " ",
453 info->protect[i] ? "RO " : " ");
454#else
455 if ((i % 5) == 0)
456 printf ("\n ");
457 printf (" %08lX%s",
wdenkbf9e3b32004-02-12 00:47:09 +0000458 info->start[i], info->protect[i] ? " (RO)" : " ");
wdenk5653fc32004-02-08 22:55:38 +0000459#endif
460 }
461 printf ("\n");
462 return;
463}
464
465/*-----------------------------------------------------------------------
466 * Copy memory to flash, returns:
467 * 0 - OK
468 * 1 - write timeout
469 * 2 - Flash not erased
470 */
wdenkbf9e3b32004-02-12 00:47:09 +0000471int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
wdenk5653fc32004-02-08 22:55:38 +0000472{
473 ulong wp;
474 ulong cp;
475 int aln;
476 cfiword_t cword;
477 int i, rc;
478
wdenkbf9e3b32004-02-12 00:47:09 +0000479#ifdef CFG_FLASH_USE_BUFFER_WRITE
480 int buffered_size;
481#endif
482 int x8mode = 0;
483
484 /* special handling of 16 bit devices in 8 bit mode */
485 if ((info->interface == FLASH_CFI_X8X16)
486 && (info->chipwidth == FLASH_CFI_BY8)) {
487 switch (info->vendor) {
488 case CFI_CMDSET_INTEL_STANDARD:
489 case CFI_CMDSET_INTEL_EXTENDED:
490 x8mode = info->portwidth;
491 info->portwidth >>= 1; /* XXX - Need to test on x9/x16 in parallel. */
492 /*info->portwidth = FLASH_CFI_8BIT; */ /* XXX - Need to test on x9/x16 in parallel. */
493 break;
494 case CFI_CMDSET_AMD_STANDARD:
495 case CFI_CMDSET_AMD_EXTENDED:
496 default:
497 break;
498 }
499 }
500 /* get lower aligned address */
wdenk5653fc32004-02-08 22:55:38 +0000501 /* get lower aligned address */
502 wp = (addr & ~(info->portwidth - 1));
503
504 /* handle unaligned start */
wdenkbf9e3b32004-02-12 00:47:09 +0000505 if ((aln = addr - wp) != 0) {
wdenk5653fc32004-02-08 22:55:38 +0000506 cword.l = 0;
507 cp = wp;
wdenkbf9e3b32004-02-12 00:47:09 +0000508 for (i = 0; i < aln; ++i, ++cp)
509 flash_add_byte (info, &cword, (*(uchar *) cp));
wdenk5653fc32004-02-08 22:55:38 +0000510
wdenkbf9e3b32004-02-12 00:47:09 +0000511 for (; (i < info->portwidth) && (cnt > 0); i++) {
512 flash_add_byte (info, &cword, *src++);
wdenk5653fc32004-02-08 22:55:38 +0000513 cnt--;
514 cp++;
515 }
wdenkbf9e3b32004-02-12 00:47:09 +0000516 for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
517 flash_add_byte (info, &cword, (*(uchar *) cp));
518 if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
wdenk5653fc32004-02-08 22:55:38 +0000519 return rc;
520 wp = cp;
521 }
522
wdenkbf9e3b32004-02-12 00:47:09 +0000523 /* handle the aligned part */
wdenk5653fc32004-02-08 22:55:38 +0000524#ifdef CFG_FLASH_USE_BUFFER_WRITE
wdenkbf9e3b32004-02-12 00:47:09 +0000525 buffered_size = (info->portwidth / info->chipwidth);
526 buffered_size *= info->buffer_size;
527 while (cnt >= info->portwidth) {
528 i = buffered_size > cnt ? cnt : buffered_size;
529 if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK)
wdenk5653fc32004-02-08 22:55:38 +0000530 return rc;
531 wp += i;
532 src += i;
wdenkbf9e3b32004-02-12 00:47:09 +0000533 cnt -= i;
wdenk5653fc32004-02-08 22:55:38 +0000534 }
535#else
wdenkbf9e3b32004-02-12 00:47:09 +0000536 while (cnt >= info->portwidth) {
wdenk5653fc32004-02-08 22:55:38 +0000537 cword.l = 0;
wdenkbf9e3b32004-02-12 00:47:09 +0000538 for (i = 0; i < info->portwidth; i++) {
539 flash_add_byte (info, &cword, *src++);
wdenk5653fc32004-02-08 22:55:38 +0000540 }
wdenkbf9e3b32004-02-12 00:47:09 +0000541 if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
wdenk5653fc32004-02-08 22:55:38 +0000542 return rc;
543 wp += info->portwidth;
544 cnt -= info->portwidth;
545 }
546#endif /* CFG_FLASH_USE_BUFFER_WRITE */
547 if (cnt == 0) {
548 return (0);
549 }
550
551 /*
552 * handle unaligned tail bytes
553 */
554 cword.l = 0;
wdenkbf9e3b32004-02-12 00:47:09 +0000555 for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) {
556 flash_add_byte (info, &cword, *src++);
wdenk5653fc32004-02-08 22:55:38 +0000557 --cnt;
558 }
wdenkbf9e3b32004-02-12 00:47:09 +0000559 for (; i < info->portwidth; ++i, ++cp) {
560 flash_add_byte (info, &cword, (*(uchar *) cp));
wdenk5653fc32004-02-08 22:55:38 +0000561 }
562
wdenkbf9e3b32004-02-12 00:47:09 +0000563 /* special handling of 16 bit devices in 8 bit mode */
564 if (x8mode) {
565 info->portwidth = x8mode;;
566 }
567 return flash_write_cfiword (info, wp, cword);
wdenk5653fc32004-02-08 22:55:38 +0000568}
569
570/*-----------------------------------------------------------------------
571 */
572#ifdef CFG_FLASH_PROTECTION
573
wdenkbf9e3b32004-02-12 00:47:09 +0000574int flash_real_protect (flash_info_t * info, long sector, int prot)
wdenk5653fc32004-02-08 22:55:38 +0000575{
576 int retcode = 0;
577
wdenkbf9e3b32004-02-12 00:47:09 +0000578 flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
579 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT);
580 if (prot)
581 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET);
wdenk5653fc32004-02-08 22:55:38 +0000582 else
wdenkbf9e3b32004-02-12 00:47:09 +0000583 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
wdenk5653fc32004-02-08 22:55:38 +0000584
wdenkbf9e3b32004-02-12 00:47:09 +0000585 if ((retcode =
586 flash_full_status_check (info, sector, info->erase_blk_tout,
587 prot ? "protect" : "unprotect")) == 0) {
wdenk5653fc32004-02-08 22:55:38 +0000588
589 info->protect[sector] = prot;
590 /* Intel's unprotect unprotects all locking */
wdenkbf9e3b32004-02-12 00:47:09 +0000591 if (prot == 0) {
wdenk5653fc32004-02-08 22:55:38 +0000592 flash_sect_t i;
wdenkbf9e3b32004-02-12 00:47:09 +0000593
594 for (i = 0; i < info->sector_count; i++) {
595 if (info->protect[i])
596 flash_real_protect (info, i, 1);
wdenk5653fc32004-02-08 22:55:38 +0000597 }
598 }
599 }
wdenk5653fc32004-02-08 22:55:38 +0000600 return retcode;
wdenkbf9e3b32004-02-12 00:47:09 +0000601}
602
wdenk5653fc32004-02-08 22:55:38 +0000603/*-----------------------------------------------------------------------
604 * flash_read_user_serial - read the OneTimeProgramming cells
605 */
wdenkbf9e3b32004-02-12 00:47:09 +0000606void flash_read_user_serial (flash_info_t * info, void *buffer, int offset,
607 int len)
wdenk5653fc32004-02-08 22:55:38 +0000608{
wdenkbf9e3b32004-02-12 00:47:09 +0000609 uchar *src;
610 uchar *dst;
wdenk5653fc32004-02-08 22:55:38 +0000611
612 dst = buffer;
wdenkbf9e3b32004-02-12 00:47:09 +0000613 src = flash_make_addr (info, 0, FLASH_OFFSET_USER_PROTECTION);
614 flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
615 memcpy (dst, src + offset, len);
616 flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
wdenk5653fc32004-02-08 22:55:38 +0000617}
wdenkbf9e3b32004-02-12 00:47:09 +0000618
wdenk5653fc32004-02-08 22:55:38 +0000619/*
620 * flash_read_factory_serial - read the device Id from the protection area
621 */
wdenkbf9e3b32004-02-12 00:47:09 +0000622void flash_read_factory_serial (flash_info_t * info, void *buffer, int offset,
623 int len)
wdenk5653fc32004-02-08 22:55:38 +0000624{
wdenkbf9e3b32004-02-12 00:47:09 +0000625 uchar *src;
wdenkcd37d9e2004-02-10 00:03:41 +0000626
wdenkbf9e3b32004-02-12 00:47:09 +0000627 src = flash_make_addr (info, 0, FLASH_OFFSET_INTEL_PROTECTION);
628 flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
629 memcpy (buffer, src + offset, len);
630 flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
wdenk5653fc32004-02-08 22:55:38 +0000631}
632
633#endif /* CFG_FLASH_PROTECTION */
634
wdenkbf9e3b32004-02-12 00:47:09 +0000635/*
636 * flash_is_busy - check to see if the flash is busy
637 * This routine checks the status of the chip and returns true if the chip is busy
638 */
639static int flash_is_busy (flash_info_t * info, flash_sect_t sect)
wdenk5653fc32004-02-08 22:55:38 +0000640{
641 int retval;
wdenkbf9e3b32004-02-12 00:47:09 +0000642
643 switch (info->vendor) {
wdenk5653fc32004-02-08 22:55:38 +0000644 case CFI_CMDSET_INTEL_STANDARD:
645 case CFI_CMDSET_INTEL_EXTENDED:
wdenkbf9e3b32004-02-12 00:47:09 +0000646 retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE);
wdenk5653fc32004-02-08 22:55:38 +0000647 break;
648 case CFI_CMDSET_AMD_STANDARD:
649 case CFI_CMDSET_AMD_EXTENDED:
wdenkbf9e3b32004-02-12 00:47:09 +0000650 retval = flash_toggle (info, sect, 0, AMD_STATUS_TOGGLE);
wdenk5653fc32004-02-08 22:55:38 +0000651 break;
652 default:
653 retval = 0;
654 }
wdenkbf9e3b32004-02-12 00:47:09 +0000655 debug ("flash_is_busy: %d\n", retval);
wdenk5653fc32004-02-08 22:55:38 +0000656 return retval;
657}
wdenkbf9e3b32004-02-12 00:47:09 +0000658
wdenk5653fc32004-02-08 22:55:38 +0000659/*-----------------------------------------------------------------------
660 * wait for XSR.7 to be set. Time out with an error if it does not.
661 * This routine does not set the flash to read-array mode.
662 */
wdenkbf9e3b32004-02-12 00:47:09 +0000663static int flash_status_check (flash_info_t * info, flash_sect_t sector,
664 ulong tout, char *prompt)
wdenk5653fc32004-02-08 22:55:38 +0000665{
666 ulong start;
667
668 /* Wait for command completion */
669 start = get_timer (0);
wdenkbf9e3b32004-02-12 00:47:09 +0000670 while (flash_is_busy (info, sector)) {
671 if (get_timer (start) > info->erase_blk_tout * CFG_HZ) {
672 printf ("Flash %s timeout at address %lx data %lx\n",
673 prompt, info->start[sector],
674 flash_read_long (info, sector, 0));
675 flash_write_cmd (info, sector, 0, info->cmd_reset);
wdenk5653fc32004-02-08 22:55:38 +0000676 return ERR_TIMOUT;
677 }
678 }
679 return ERR_OK;
680}
wdenkbf9e3b32004-02-12 00:47:09 +0000681
wdenk5653fc32004-02-08 22:55:38 +0000682/*-----------------------------------------------------------------------
683 * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
684 * This routine sets the flash to read-array mode.
685 */
wdenkbf9e3b32004-02-12 00:47:09 +0000686static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
687 ulong tout, char *prompt)
wdenk5653fc32004-02-08 22:55:38 +0000688{
689 int retcode;
wdenkbf9e3b32004-02-12 00:47:09 +0000690
691 retcode = flash_status_check (info, sector, tout, prompt);
692 switch (info->vendor) {
wdenk5653fc32004-02-08 22:55:38 +0000693 case CFI_CMDSET_INTEL_EXTENDED:
694 case CFI_CMDSET_INTEL_STANDARD:
wdenkbf9e3b32004-02-12 00:47:09 +0000695 if ((retcode != ERR_OK)
696 && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) {
wdenk5653fc32004-02-08 22:55:38 +0000697 retcode = ERR_INVAL;
wdenkbf9e3b32004-02-12 00:47:09 +0000698 printf ("Flash %s error at address %lx\n", prompt,
699 info->start[sector]);
wdenk028ab6b2004-02-23 23:54:43 +0000700 if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) {
wdenkbf9e3b32004-02-12 00:47:09 +0000701 printf ("Command Sequence Error.\n");
wdenk028ab6b2004-02-23 23:54:43 +0000702 } else if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS)) {
wdenkbf9e3b32004-02-12 00:47:09 +0000703 printf ("Block Erase Error.\n");
wdenk5653fc32004-02-08 22:55:38 +0000704 retcode = ERR_NOT_ERASED;
wdenk028ab6b2004-02-23 23:54:43 +0000705 } else if (flash_isset (info, sector, 0, FLASH_STATUS_PSLBS)) {
wdenkbf9e3b32004-02-12 00:47:09 +0000706 printf ("Locking Error\n");
wdenk5653fc32004-02-08 22:55:38 +0000707 }
wdenkbf9e3b32004-02-12 00:47:09 +0000708 if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) {
709 printf ("Block locked.\n");
710 retcode = ERR_PROTECTED;
711 }
712 if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS))
713 printf ("Vpp Low Error.\n");
wdenk5653fc32004-02-08 22:55:38 +0000714 }
wdenkbf9e3b32004-02-12 00:47:09 +0000715 flash_write_cmd (info, sector, 0, FLASH_CMD_RESET);
wdenk5653fc32004-02-08 22:55:38 +0000716 break;
717 default:
718 break;
719 }
720 return retcode;
721}
wdenkbf9e3b32004-02-12 00:47:09 +0000722
wdenk5653fc32004-02-08 22:55:38 +0000723/*-----------------------------------------------------------------------
724 */
wdenkbf9e3b32004-02-12 00:47:09 +0000725static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
wdenk5653fc32004-02-08 22:55:38 +0000726{
wdenk4d13cba2004-03-14 14:09:05 +0000727#if defined(__LITTLE_ENDIAN)
728 unsigned short w;
729 unsigned int l;
730 unsigned long long ll;
731#endif
732
wdenkbf9e3b32004-02-12 00:47:09 +0000733 switch (info->portwidth) {
wdenk5653fc32004-02-08 22:55:38 +0000734 case FLASH_CFI_8BIT:
735 cword->c = c;
736 break;
737 case FLASH_CFI_16BIT:
wdenk4d13cba2004-03-14 14:09:05 +0000738#if defined(__LITTLE_ENDIAN)
739 w = c;
740 w <<= 8;
741 cword->w = (cword->w >> 8) | w;
742#else
wdenk5653fc32004-02-08 22:55:38 +0000743 cword->w = (cword->w << 8) | c;
wdenk4d13cba2004-03-14 14:09:05 +0000744#endif
wdenk5653fc32004-02-08 22:55:38 +0000745 break;
746 case FLASH_CFI_32BIT:
wdenk4d13cba2004-03-14 14:09:05 +0000747#if defined(__LITTLE_ENDIAN)
748 l = c;
749 l <<= 24;
750 cword->l = (cword->l >> 8) | l;
751#else
wdenk5653fc32004-02-08 22:55:38 +0000752 cword->l = (cword->l << 8) | c;
wdenk4d13cba2004-03-14 14:09:05 +0000753#endif
wdenk5653fc32004-02-08 22:55:38 +0000754 break;
755 case FLASH_CFI_64BIT:
wdenk4d13cba2004-03-14 14:09:05 +0000756#if defined(__LITTLE_ENDIAN)
757 ll = c;
758 ll <<= 56;
759 cword->ll = (cword->ll >> 8) | ll;
760#else
wdenk5653fc32004-02-08 22:55:38 +0000761 cword->ll = (cword->ll << 8) | c;
wdenk4d13cba2004-03-14 14:09:05 +0000762#endif
wdenk5653fc32004-02-08 22:55:38 +0000763 break;
764 }
765}
766
767
768/*-----------------------------------------------------------------------
769 * make a proper sized command based on the port and chip widths
770 */
wdenkbf9e3b32004-02-12 00:47:09 +0000771static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf)
wdenk5653fc32004-02-08 22:55:38 +0000772{
773 int i;
wdenkbf9e3b32004-02-12 00:47:09 +0000774
775#if defined(__LITTLE_ENDIAN)
wdenk028ab6b2004-02-23 23:54:43 +0000776 ushort stmpw;
777 uint stmpi;
wdenkbf9e3b32004-02-12 00:47:09 +0000778#endif
779 uchar *cp = (uchar *) cmdbuf;
780
781 for (i = 0; i < info->portwidth; i++)
782 *cp++ = ((i + 1) % info->chipwidth) ? '\0' : cmd;
783#if defined(__LITTLE_ENDIAN)
wdenk028ab6b2004-02-23 23:54:43 +0000784 switch (info->portwidth) {
785 case FLASH_CFI_8BIT:
786 break;
787 case FLASH_CFI_16BIT:
788 stmpw = *(ushort *) cmdbuf;
789 *(ushort *) cmdbuf = __swab16 (stmpw);
790 break;
791 case FLASH_CFI_32BIT:
792 stmpi = *(uint *) cmdbuf;
793 *(uint *) cmdbuf = __swab32 (stmpi);
794 break;
795 default:
796 printf("WARNING: flash_make_cmd: unsuppported LittleEndian mode\n");
797 break;
wdenkbf9e3b32004-02-12 00:47:09 +0000798 }
799#endif
wdenk5653fc32004-02-08 22:55:38 +0000800}
801
802/*
803 * Write a proper sized command to the correct address
804 */
wdenk028ab6b2004-02-23 23:54:43 +0000805static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
wdenk5653fc32004-02-08 22:55:38 +0000806{
807
808 volatile cfiptr_t addr;
809 cfiword_t cword;
wdenkbf9e3b32004-02-12 00:47:09 +0000810
811 addr.cp = flash_make_addr (info, sect, offset);
812 flash_make_cmd (info, cmd, &cword);
813 switch (info->portwidth) {
wdenk5653fc32004-02-08 22:55:38 +0000814 case FLASH_CFI_8BIT:
wdenkbf9e3b32004-02-12 00:47:09 +0000815 debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr.cp, cmd,
816 cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
wdenk5653fc32004-02-08 22:55:38 +0000817 *addr.cp = cword.c;
818 break;
819 case FLASH_CFI_16BIT:
wdenkbf9e3b32004-02-12 00:47:09 +0000820 debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr.wp,
821 cmd, cword.w,
wdenk5653fc32004-02-08 22:55:38 +0000822 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
823 *addr.wp = cword.w;
824 break;
825 case FLASH_CFI_32BIT:
wdenkbf9e3b32004-02-12 00:47:09 +0000826 debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr.lp,
827 cmd, cword.l,
wdenk5653fc32004-02-08 22:55:38 +0000828 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
829 *addr.lp = cword.l;
830 break;
831 case FLASH_CFI_64BIT:
832#ifdef DEBUG
wdenkbf9e3b32004-02-12 00:47:09 +0000833 {
wdenk5653fc32004-02-08 22:55:38 +0000834 char str[20];
wdenkcd37d9e2004-02-10 00:03:41 +0000835
wdenkbf9e3b32004-02-12 00:47:09 +0000836 print_longlong (str, cword.ll);
837
838 debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n",
839 addr.llp, cmd, str,
wdenk5653fc32004-02-08 22:55:38 +0000840 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
841 }
842#endif
843 *addr.llp = cword.ll;
844 break;
845 }
846}
847
wdenkbf9e3b32004-02-12 00:47:09 +0000848static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect)
wdenk5653fc32004-02-08 22:55:38 +0000849{
wdenkbf9e3b32004-02-12 00:47:09 +0000850 flash_write_cmd (info, sect, 0x555, 0xAA);
851 flash_write_cmd (info, sect, 0x2AA, 0x55);
wdenk5653fc32004-02-08 22:55:38 +0000852}
wdenkbf9e3b32004-02-12 00:47:09 +0000853
wdenk5653fc32004-02-08 22:55:38 +0000854/*-----------------------------------------------------------------------
855 */
wdenk028ab6b2004-02-23 23:54:43 +0000856static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
wdenk5653fc32004-02-08 22:55:38 +0000857{
858 cfiptr_t cptr;
859 cfiword_t cword;
860 int retval;
wdenk5653fc32004-02-08 22:55:38 +0000861
wdenkbf9e3b32004-02-12 00:47:09 +0000862 cptr.cp = flash_make_addr (info, sect, offset);
863 flash_make_cmd (info, cmd, &cword);
864
865 debug ("is= cmd %x(%c) addr %p ", cmd, cmd, cptr.cp);
866 switch (info->portwidth) {
wdenk5653fc32004-02-08 22:55:38 +0000867 case FLASH_CFI_8BIT:
wdenkbf9e3b32004-02-12 00:47:09 +0000868 debug ("is= %x %x\n", cptr.cp[0], cword.c);
wdenk5653fc32004-02-08 22:55:38 +0000869 retval = (cptr.cp[0] == cword.c);
870 break;
871 case FLASH_CFI_16BIT:
wdenkbf9e3b32004-02-12 00:47:09 +0000872 debug ("is= %4.4x %4.4x\n", cptr.wp[0], cword.w);
wdenk5653fc32004-02-08 22:55:38 +0000873 retval = (cptr.wp[0] == cword.w);
874 break;
875 case FLASH_CFI_32BIT:
wdenkbf9e3b32004-02-12 00:47:09 +0000876 debug ("is= %8.8lx %8.8lx\n", cptr.lp[0], cword.l);
wdenk5653fc32004-02-08 22:55:38 +0000877 retval = (cptr.lp[0] == cword.l);
878 break;
879 case FLASH_CFI_64BIT:
wdenkcd37d9e2004-02-10 00:03:41 +0000880#ifdef DEBUG
wdenkbf9e3b32004-02-12 00:47:09 +0000881 {
wdenk5653fc32004-02-08 22:55:38 +0000882 char str1[20];
883 char str2[20];
wdenkbf9e3b32004-02-12 00:47:09 +0000884
885 print_longlong (str1, cptr.llp[0]);
886 print_longlong (str2, cword.ll);
887 debug ("is= %s %s\n", str1, str2);
wdenk5653fc32004-02-08 22:55:38 +0000888 }
889#endif
890 retval = (cptr.llp[0] == cword.ll);
891 break;
892 default:
893 retval = 0;
894 break;
895 }
896 return retval;
897}
wdenkbf9e3b32004-02-12 00:47:09 +0000898
wdenk5653fc32004-02-08 22:55:38 +0000899/*-----------------------------------------------------------------------
900 */
wdenk028ab6b2004-02-23 23:54:43 +0000901static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
wdenk5653fc32004-02-08 22:55:38 +0000902{
903 cfiptr_t cptr;
904 cfiword_t cword;
905 int retval;
wdenkbf9e3b32004-02-12 00:47:09 +0000906
907 cptr.cp = flash_make_addr (info, sect, offset);
908 flash_make_cmd (info, cmd, &cword);
909 switch (info->portwidth) {
wdenk5653fc32004-02-08 22:55:38 +0000910 case FLASH_CFI_8BIT:
911 retval = ((cptr.cp[0] & cword.c) == cword.c);
912 break;
913 case FLASH_CFI_16BIT:
914 retval = ((cptr.wp[0] & cword.w) == cword.w);
915 break;
916 case FLASH_CFI_32BIT:
917 retval = ((cptr.lp[0] & cword.l) == cword.l);
918 break;
919 case FLASH_CFI_64BIT:
920 retval = ((cptr.llp[0] & cword.ll) == cword.ll);
wdenkbf9e3b32004-02-12 00:47:09 +0000921 break;
wdenk5653fc32004-02-08 22:55:38 +0000922 default:
923 retval = 0;
924 break;
925 }
926 return retval;
927}
928
929/*-----------------------------------------------------------------------
930 */
wdenk028ab6b2004-02-23 23:54:43 +0000931static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
wdenk5653fc32004-02-08 22:55:38 +0000932{
933 cfiptr_t cptr;
934 cfiword_t cword;
935 int retval;
wdenkbf9e3b32004-02-12 00:47:09 +0000936
937 cptr.cp = flash_make_addr (info, sect, offset);
938 flash_make_cmd (info, cmd, &cword);
939 switch (info->portwidth) {
wdenk5653fc32004-02-08 22:55:38 +0000940 case FLASH_CFI_8BIT:
941 retval = ((cptr.cp[0] & cword.c) != (cptr.cp[0] & cword.c));
942 break;
943 case FLASH_CFI_16BIT:
944 retval = ((cptr.wp[0] & cword.w) != (cptr.wp[0] & cword.w));
945 break;
946 case FLASH_CFI_32BIT:
947 retval = ((cptr.lp[0] & cword.l) != (cptr.lp[0] & cword.l));
948 break;
949 case FLASH_CFI_64BIT:
wdenkbf9e3b32004-02-12 00:47:09 +0000950 retval = ((cptr.llp[0] & cword.ll) !=
951 (cptr.llp[0] & cword.ll));
wdenk5653fc32004-02-08 22:55:38 +0000952 break;
953 default:
954 retval = 0;
955 break;
956 }
957 return retval;
958}
959
960/*-----------------------------------------------------------------------
961 * detect if flash is compatible with the Common Flash Interface (CFI)
962 * http://www.jedec.org/download/search/jesd68.pdf
963 *
964*/
wdenkbf9e3b32004-02-12 00:47:09 +0000965static int flash_detect_cfi (flash_info_t * info)
wdenk5653fc32004-02-08 22:55:38 +0000966{
wdenkbf9e3b32004-02-12 00:47:09 +0000967 debug ("flash detect cfi\n");
wdenk5653fc32004-02-08 22:55:38 +0000968
wdenkbf9e3b32004-02-12 00:47:09 +0000969 for (info->portwidth = FLASH_CFI_8BIT;
970 info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) {
971 for (info->chipwidth = FLASH_CFI_BY8;
972 info->chipwidth <= info->portwidth;
973 info->chipwidth <<= 1) {
974 flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
wdenk028ab6b2004-02-23 23:54:43 +0000975 flash_write_cmd (info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
976 if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
977 && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R')
978 && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) {
979 info->interface = flash_read_ushort (info, 0, FLASH_OFFSET_INTERFACE);
wdenkbf9e3b32004-02-12 00:47:09 +0000980 debug ("device interface is %d\n",
981 info->interface);
982 debug ("found port %d chip %d ",
983 info->portwidth, info->chipwidth);
984 debug ("port %d bits chip %d bits\n",
wdenk028ab6b2004-02-23 23:54:43 +0000985 info->portwidth << CFI_FLASH_SHIFT_WIDTH,
986 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
wdenk5653fc32004-02-08 22:55:38 +0000987 return 1;
988 }
989 }
990 }
wdenkbf9e3b32004-02-12 00:47:09 +0000991 debug ("not found\n");
wdenk5653fc32004-02-08 22:55:38 +0000992 return 0;
993}
wdenkbf9e3b32004-02-12 00:47:09 +0000994
wdenk5653fc32004-02-08 22:55:38 +0000995/*
996 * The following code cannot be run from FLASH!
997 *
998 */
999static ulong flash_get_size (ulong base, int banknum)
1000{
wdenkbf9e3b32004-02-12 00:47:09 +00001001 flash_info_t *info = &flash_info[banknum];
wdenk5653fc32004-02-08 22:55:38 +00001002 int i, j;
1003 flash_sect_t sect_cnt;
1004 unsigned long sector;
1005 unsigned long tmp;
1006 int size_ratio;
1007 uchar num_erase_regions;
wdenkbf9e3b32004-02-12 00:47:09 +00001008 int erase_region_size;
1009 int erase_region_count;
wdenk5653fc32004-02-08 22:55:38 +00001010
1011 info->start[0] = base;
1012
wdenkbf9e3b32004-02-12 00:47:09 +00001013 if (flash_detect_cfi (info)) {
wdenk028ab6b2004-02-23 23:54:43 +00001014 info->vendor = flash_read_ushort (info, 0, FLASH_OFFSET_PRIMARY_VENDOR);
wdenkbf9e3b32004-02-12 00:47:09 +00001015#ifdef DEBUG
1016 flash_printqry (info, 0);
1017#endif
1018 switch (info->vendor) {
wdenk5653fc32004-02-08 22:55:38 +00001019 case CFI_CMDSET_INTEL_STANDARD:
1020 case CFI_CMDSET_INTEL_EXTENDED:
1021 default:
1022 info->cmd_reset = FLASH_CMD_RESET;
1023 break;
1024 case CFI_CMDSET_AMD_STANDARD:
1025 case CFI_CMDSET_AMD_EXTENDED:
1026 info->cmd_reset = AMD_CMD_RESET;
1027 break;
1028 }
wdenkcd37d9e2004-02-10 00:03:41 +00001029
wdenkbf9e3b32004-02-12 00:47:09 +00001030 debug ("manufacturer is %d\n", info->vendor);
wdenk5653fc32004-02-08 22:55:38 +00001031 size_ratio = info->portwidth / info->chipwidth;
wdenkbf9e3b32004-02-12 00:47:09 +00001032 /* if the chip is x8/x16 reduce the ratio by half */
1033 if ((info->interface == FLASH_CFI_X8X16)
1034 && (info->chipwidth == FLASH_CFI_BY8)) {
1035 size_ratio >>= 1;
1036 }
wdenk028ab6b2004-02-23 23:54:43 +00001037 num_erase_regions = flash_read_uchar (info, FLASH_OFFSET_NUM_ERASE_REGIONS);
wdenkbf9e3b32004-02-12 00:47:09 +00001038 debug ("size_ratio %d port %d bits chip %d bits\n",
1039 size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH,
1040 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
1041 debug ("found %d erase regions\n", num_erase_regions);
wdenk5653fc32004-02-08 22:55:38 +00001042 sect_cnt = 0;
1043 sector = base;
wdenkbf9e3b32004-02-12 00:47:09 +00001044 for (i = 0; i < num_erase_regions; i++) {
1045 if (i > NUM_ERASE_REGIONS) {
wdenk028ab6b2004-02-23 23:54:43 +00001046 printf ("%d erase regions found, only %d used\n",
1047 num_erase_regions, NUM_ERASE_REGIONS);
wdenk5653fc32004-02-08 22:55:38 +00001048 break;
1049 }
wdenkbf9e3b32004-02-12 00:47:09 +00001050 tmp = flash_read_long (info, 0,
1051 FLASH_OFFSET_ERASE_REGIONS +
1052 i * 4);
1053 erase_region_size =
1054 (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;
wdenk5653fc32004-02-08 22:55:38 +00001055 tmp >>= 16;
wdenkbf9e3b32004-02-12 00:47:09 +00001056 erase_region_count = (tmp & 0xffff) + 1;
wdenk028ab6b2004-02-23 23:54:43 +00001057 printf ("erase_region_count = %d erase_region_size = %d\n",
1058 erase_region_count, erase_region_size);
wdenkbf9e3b32004-02-12 00:47:09 +00001059 for (j = 0; j < erase_region_count; j++) {
wdenk5653fc32004-02-08 22:55:38 +00001060 info->start[sect_cnt] = sector;
1061 sector += (erase_region_size * size_ratio);
wdenkbf9e3b32004-02-12 00:47:09 +00001062 info->protect[sect_cnt] =
1063 flash_isset (info, sect_cnt,
1064 FLASH_OFFSET_PROTECT,
1065 FLASH_STATUS_PROTECT);
wdenk5653fc32004-02-08 22:55:38 +00001066 sect_cnt++;
1067 }
1068 }
1069
1070 info->sector_count = sect_cnt;
1071 /* multiply the size by the number of chips */
wdenk028ab6b2004-02-23 23:54:43 +00001072 info->size = (1 << flash_read_uchar (info, FLASH_OFFSET_SIZE)) * size_ratio;
1073 info->buffer_size = (1 << flash_read_ushort (info, 0, FLASH_OFFSET_BUFFER_SIZE));
wdenkbf9e3b32004-02-12 00:47:09 +00001074 tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_ETOUT);
wdenk028ab6b2004-02-23 23:54:43 +00001075 info->erase_blk_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_EMAX_TOUT)));
wdenkbf9e3b32004-02-12 00:47:09 +00001076 tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT);
wdenk028ab6b2004-02-23 23:54:43 +00001077 info->buffer_write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT)));
wdenkbf9e3b32004-02-12 00:47:09 +00001078 tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT);
wdenk028ab6b2004-02-23 23:54:43 +00001079 info->write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WMAX_TOUT))) / 1000;
wdenk5653fc32004-02-08 22:55:38 +00001080 info->flash_id = FLASH_MAN_CFI;
1081 }
1082
wdenkbf9e3b32004-02-12 00:47:09 +00001083 flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
1084 return (info->size);
wdenk5653fc32004-02-08 22:55:38 +00001085}
1086
1087
1088/*-----------------------------------------------------------------------
1089 */
wdenkbf9e3b32004-02-12 00:47:09 +00001090static int flash_write_cfiword (flash_info_t * info, ulong dest,
1091 cfiword_t cword)
wdenk5653fc32004-02-08 22:55:38 +00001092{
1093
1094 cfiptr_t ctladdr;
1095 cfiptr_t cptr;
1096 int flag;
1097
wdenkbf9e3b32004-02-12 00:47:09 +00001098 ctladdr.cp = flash_make_addr (info, 0, 0);
1099 cptr.cp = (uchar *) dest;
wdenk5653fc32004-02-08 22:55:38 +00001100
1101
1102 /* Check if Flash is (sufficiently) erased */
wdenkbf9e3b32004-02-12 00:47:09 +00001103 switch (info->portwidth) {
wdenk5653fc32004-02-08 22:55:38 +00001104 case FLASH_CFI_8BIT:
1105 flag = ((cptr.cp[0] & cword.c) == cword.c);
1106 break;
1107 case FLASH_CFI_16BIT:
1108 flag = ((cptr.wp[0] & cword.w) == cword.w);
1109 break;
1110 case FLASH_CFI_32BIT:
wdenkbf9e3b32004-02-12 00:47:09 +00001111 flag = ((cptr.lp[0] & cword.l) == cword.l);
wdenk5653fc32004-02-08 22:55:38 +00001112 break;
1113 case FLASH_CFI_64BIT:
1114 flag = ((cptr.lp[0] & cword.ll) == cword.ll);
1115 break;
1116 default:
1117 return 2;
1118 }
wdenkbf9e3b32004-02-12 00:47:09 +00001119 if (!flag)
wdenk5653fc32004-02-08 22:55:38 +00001120 return 2;
1121
1122 /* Disable interrupts which might cause a timeout here */
wdenkbf9e3b32004-02-12 00:47:09 +00001123 flag = disable_interrupts ();
wdenk5653fc32004-02-08 22:55:38 +00001124
wdenkbf9e3b32004-02-12 00:47:09 +00001125 switch (info->vendor) {
wdenk5653fc32004-02-08 22:55:38 +00001126 case CFI_CMDSET_INTEL_EXTENDED:
1127 case CFI_CMDSET_INTEL_STANDARD:
wdenkbf9e3b32004-02-12 00:47:09 +00001128 flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS);
1129 flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE);
wdenk5653fc32004-02-08 22:55:38 +00001130 break;
1131 case CFI_CMDSET_AMD_EXTENDED:
1132 case CFI_CMDSET_AMD_STANDARD:
wdenkbf9e3b32004-02-12 00:47:09 +00001133 flash_unlock_seq (info, 0);
1134 flash_write_cmd (info, 0, 0x555, AMD_CMD_WRITE);
wdenk5653fc32004-02-08 22:55:38 +00001135 break;
1136 }
1137
wdenkbf9e3b32004-02-12 00:47:09 +00001138 switch (info->portwidth) {
wdenk5653fc32004-02-08 22:55:38 +00001139 case FLASH_CFI_8BIT:
1140 cptr.cp[0] = cword.c;
1141 break;
1142 case FLASH_CFI_16BIT:
1143 cptr.wp[0] = cword.w;
1144 break;
1145 case FLASH_CFI_32BIT:
1146 cptr.lp[0] = cword.l;
1147 break;
1148 case FLASH_CFI_64BIT:
1149 cptr.llp[0] = cword.ll;
1150 break;
1151 }
1152
1153 /* re-enable interrupts if necessary */
wdenkbf9e3b32004-02-12 00:47:09 +00001154 if (flag)
1155 enable_interrupts ();
wdenk5653fc32004-02-08 22:55:38 +00001156
wdenkbf9e3b32004-02-12 00:47:09 +00001157 return flash_full_status_check (info, 0, info->write_tout, "write");
wdenk5653fc32004-02-08 22:55:38 +00001158}
1159
1160#ifdef CFG_FLASH_USE_BUFFER_WRITE
1161
1162/* loop through the sectors from the highest address
1163 * when the passed address is greater or equal to the sector address
1164 * we have a match
1165 */
wdenkbf9e3b32004-02-12 00:47:09 +00001166static flash_sect_t find_sector (flash_info_t * info, ulong addr)
wdenk5653fc32004-02-08 22:55:38 +00001167{
1168 flash_sect_t sector;
wdenkbf9e3b32004-02-12 00:47:09 +00001169
1170 for (sector = info->sector_count - 1; sector >= 0; sector--) {
1171 if (addr >= info->start[sector])
wdenk5653fc32004-02-08 22:55:38 +00001172 break;
1173 }
1174 return sector;
1175}
1176
wdenkbf9e3b32004-02-12 00:47:09 +00001177static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
1178 int len)
wdenk5653fc32004-02-08 22:55:38 +00001179{
1180 flash_sect_t sector;
1181 int cnt;
1182 int retcode;
1183 volatile cfiptr_t src;
1184 volatile cfiptr_t dst;
1185
1186 src.cp = cp;
wdenkbf9e3b32004-02-12 00:47:09 +00001187 dst.cp = (uchar *) dest;
1188 sector = find_sector (info, dest);
1189 flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
1190 flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
1191 if ((retcode =
1192 flash_status_check (info, sector, info->buffer_write_tout,
1193 "write to buffer")) == ERR_OK) {
1194 /* reduce the number of loops by the width of the port */
1195 switch (info->portwidth) {
wdenk5653fc32004-02-08 22:55:38 +00001196 case FLASH_CFI_8BIT:
1197 cnt = len;
1198 break;
1199 case FLASH_CFI_16BIT:
1200 cnt = len >> 1;
1201 break;
1202 case FLASH_CFI_32BIT:
1203 cnt = len >> 2;
1204 break;
1205 case FLASH_CFI_64BIT:
1206 cnt = len >> 3;
1207 break;
1208 default:
1209 return ERR_INVAL;
1210 break;
1211 }
wdenkbf9e3b32004-02-12 00:47:09 +00001212 flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
1213 while (cnt-- > 0) {
1214 switch (info->portwidth) {
wdenk5653fc32004-02-08 22:55:38 +00001215 case FLASH_CFI_8BIT:
1216 *dst.cp++ = *src.cp++;
1217 break;
1218 case FLASH_CFI_16BIT:
1219 *dst.wp++ = *src.wp++;
1220 break;
1221 case FLASH_CFI_32BIT:
1222 *dst.lp++ = *src.lp++;
1223 break;
1224 case FLASH_CFI_64BIT:
1225 *dst.llp++ = *src.llp++;
1226 break;
1227 default:
1228 return ERR_INVAL;
1229 break;
1230 }
1231 }
wdenkbf9e3b32004-02-12 00:47:09 +00001232 flash_write_cmd (info, sector, 0,
1233 FLASH_CMD_WRITE_BUFFER_CONFIRM);
1234 retcode =
1235 flash_full_status_check (info, sector,
1236 info->buffer_write_tout,
1237 "buffer write");
wdenk5653fc32004-02-08 22:55:38 +00001238 }
wdenkbf9e3b32004-02-12 00:47:09 +00001239 flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
wdenk5653fc32004-02-08 22:55:38 +00001240 return retcode;
1241}
1242#endif /* CFG_USE_FLASH_BUFFER_WRITE */
1243#endif /* CFG_FLASH_CFI */