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wdenk56f94be2002-11-05 16:35:14 +00001/*
2 * (C) Copyright 2000, 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/*
26 * board/config.h - configuration options, board specific
27 * Derived from ../tqm8xx/tqm8xx.c
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37
38#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
39#define CONFIG_KUP4K 1 /* ...on a KUP4K module */
40
41#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
42#undef CONFIG_8xx_CONS_SMC2
43#undef CONFIG_8xx_CONS_NONE
wdenk2a3cb022002-11-05 21:01:48 +000044#define CONFIG_BAUDRATE 9600 /* console baudrate */
wdenk56f94be2002-11-05 16:35:14 +000045#if 0
46#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
47#else
wdenka6c7ad22002-12-03 21:28:10 +000048#define CONFIG_BOOTDELAY 5 /* autoboot after 1 second */
wdenk56f94be2002-11-05 16:35:14 +000049#endif
50
51#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
52
53#define CONFIG_BOARD_TYPES 1 /* support board types */
54
55#if 0
56#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
57#endif
58
59#undef CONFIG_BOOTARGS
60
61#define CONFIG_NFSBOOTCOMMAND \
62 "dhcp ;"\
63 "setenv bootargs root=/dev/nfs ro nfsroot=$(nfsip):$(rootpath) "\
64 "ip=$(ipaddr):$(nfsip):$(gatewayip):"\
65 "$(netmask):heydeck.eva:eth0:off; "\
66 "bootm 100000"
67
68#define CONFIG_RAMBOOTCOMMAND \
69 "diskboot 100000 0:1; "\
70 "setenv bootargs root=/dev/hda2 panic=1 "\
71 "ip=192.168.0.71:192.168.0.100:192.168.0.2:255.255.255.0; "\
72 "bootm"
73
74#define CONFIG_BOOTCOMMAND \
75 "run ramboot "\
76 "run nfsboot"
77
78#define CONFIG_MISC_INIT_R 1
79
80#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
81#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
82
83#undef CONFIG_WATCHDOG /* watchdog disabled */
84
85#define CONFIG_STATUS_LED 1 /* Status LED enabled */
86
87#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
88
89#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
90
91#define CONFIG_MAC_PARTITION
92#define CONFIG_DOS_PARTITION
93
94#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
95
96#define CONFIG_ETHADDR 00:0B:64:00:00:00 /* our OUI from IEEE */
97#define CONFIG_KUP4K_LOGO 0x40040000 /* Address of logo bitmap */
98
99/* Define to allow the user to overwrite serial and ethaddr */
100#define CONFIG_ENV_OVERWRITE
101
102#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
103 CFG_CMD_DHCP | \
104 CFG_CMD_IDE | \
105 CFG_CMD_DATE )
106
107/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
108#include <cmd_confdefs.h>
109
110/*
111 * Miscellaneous configurable options
112 */
113#define CFG_LONGHELP /* undef to save memory */
114#define CFG_PROMPT "=> " /* Monitor Command Prompt */
115#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
116#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
117#else
118#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
119#endif
120#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
121#define CFG_MAXARGS 16 /* max number of command args */
122#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
123
124#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
125#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
126
127#define CFG_LOAD_ADDR 0x100000 /* default load address */
128
129#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
130
131#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
132
133/*
134 * Low Level Configuration Settings
135 * (address mappings, register initial values, etc.)
136 * You should know what you are doing if you make changes here.
137 */
138/*-----------------------------------------------------------------------
139 * Internal Memory Mapped Register
140 */
141#define CFG_IMMR 0xFFF00000
142
143/*-----------------------------------------------------------------------
144 * Definitions for initial stack pointer and data area (in DPRAM)
145 */
146#define CFG_INIT_RAM_ADDR CFG_IMMR
147#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
148#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
149#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
150#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
151
152/*-----------------------------------------------------------------------
153 * Start addresses for the final memory configuration
154 * (Set up by the startup code)
155 * Please note that CFG_SDRAM_BASE _must_ start at 0
156 */
157#define CFG_SDRAM_BASE 0x00000000
158#define CFG_FLASH_BASE 0x40000000
159#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
160#define CFG_MONITOR_BASE CFG_FLASH_BASE
161#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
162
163/*
164 * For booting Linux, the board info and command line data
165 * have to be in the first 8 MB of memory, since this is
166 * the maximum mapped by the Linux kernel during initialization.
167 */
168#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
169
170/*-----------------------------------------------------------------------
171 * FLASH organization
172 */
173#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
174#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
175
176#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
177#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
178
179#define CFG_ENV_IS_IN_FLASH 1
180#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
181#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
182#define CFG_ENV_SECT_SIZE 0x8000
183
184/* Address and size of Redundant Environment Sector */
185#if 0
186#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
187#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
188#endif
189/*-----------------------------------------------------------------------
190 * Hardware Information Block
191 */
192#if 0
193#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
194#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
195#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
196#endif
197/*-----------------------------------------------------------------------
198 * Cache Configuration
199 */
200#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
201#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
202#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
203#endif
204
205/*-----------------------------------------------------------------------
206 * SYPCR - System Protection Control 11-9
207 * SYPCR can only be written once after reset!
208 *-----------------------------------------------------------------------
209 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
210 */
211#if defined(CONFIG_WATCHDOG)
212#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
213 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
214#else
215#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
216#endif
217
218/*-----------------------------------------------------------------------
219 * SIUMCR - SIU Module Configuration 11-6
220 *-----------------------------------------------------------------------
221 * PCMCIA config., multi-function pin tri-state
222 */
223#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00)
224
225/*-----------------------------------------------------------------------
226 * TBSCR - Time Base Status and Control 11-26
227 *-----------------------------------------------------------------------
228 * Clear Reference Interrupt Status, Timebase freezing enabled
229 */
230#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
231
232/*-----------------------------------------------------------------------
233 * RTCSC - Real-Time Clock Status and Control Register 11-27
234 *-----------------------------------------------------------------------
235 */
236#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
237
238/*-----------------------------------------------------------------------
239 * PISCR - Periodic Interrupt Status and Control 11-31
240 *-----------------------------------------------------------------------
241 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
242 */
243#define CFG_PISCR (PISCR_PS | PISCR_PITF)
244
245/*-----------------------------------------------------------------------
246 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
247 *-----------------------------------------------------------------------
248 * Reset PLL lock status sticky bit, timer expired status bit and timer
249 * interrupt status bit
250 *
251 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
252 */
253#define CFG_PLPRCR ( (3-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
254
255/*-----------------------------------------------------------------------
256 * SCCR - System Clock and reset Control Register 15-27
257 *-----------------------------------------------------------------------
258 * Set clock output, timebase and RTC source and divider,
259 * power management and some other internal clocks
260 */
261#define SCCR_MASK SCCR_EBDF00
262#define CFG_SCCR ( SCCR_TBS | SCCR_EBDF00 | \
263 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
264 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
265 SCCR_DFALCD00)
266
267/*-----------------------------------------------------------------------
268 * PCMCIA stuff
269 *-----------------------------------------------------------------------
270 *
271 */
272
wdenkea909b72002-11-21 23:11:29 +0000273/* KUP4K use both slots, SLOT_A as "primary". */
274#define CONFIG_PCMCIA_SLOT_A 1
wdenk56f94be2002-11-05 16:35:14 +0000275
276#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
277#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
278#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
279#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
280#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
281#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
282#define CFG_PCMCIA_IO_ADDR (0xEC000000)
283#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
284
wdenkea909b72002-11-21 23:11:29 +0000285#define PCMCIA_SOCKETS_NO 2
286#define PCMCIA_MEM_WIN_NO 8
wdenk56f94be2002-11-05 16:35:14 +0000287/*-----------------------------------------------------------------------
288 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
289 *-----------------------------------------------------------------------
290 */
291
292#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
293
294#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
wdenk1f53a412002-12-04 23:39:58 +0000295#define CONFIG_IDE_LED 1 /* LED for ide supported */
wdenk56f94be2002-11-05 16:35:14 +0000296#undef CONFIG_IDE_RESET /* reset for ide not supported */
297
wdenkea909b72002-11-21 23:11:29 +0000298#define CFG_IDE_MAXBUS 2
299#define CFG_IDE_MAXDEVICE 4
wdenk56f94be2002-11-05 16:35:14 +0000300
301#define CFG_ATA_IDE0_OFFSET 0x0000
302
wdenkea909b72002-11-21 23:11:29 +0000303#define CFG_ATA_IDE1_OFFSET (4 * CFG_PCMCIA_MEM_SIZE)
304
wdenk56f94be2002-11-05 16:35:14 +0000305#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
306
307/* Offset for data I/O */
308#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
309
310/* Offset for normal register accesses */
311#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
312
313/* Offset for alternate registers */
314#define CFG_ATA_ALT_OFFSET 0x0100
315
316
317/*-----------------------------------------------------------------------
318 *
319 *-----------------------------------------------------------------------
320 *
321 */
322/*#define CFG_DER 0x2002000F*/
323#define CFG_DER 0
324
325/*
326 * Init Memory Controller:
327 *
328 * BR0/1 and OR0/1 (FLASH)
329 */
330#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
331
332/* used to re-map FLASH both when starting from SRAM or FLASH:
333 * restrict access enough to keep SRAM working (if any)
334 * but not too much to meddle with FLASH accesses
335 */
336#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
337#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
338
339/*
340 * FLASH timing:
341 */
342#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
343 OR_SCY_2_CLK | OR_EHTR | OR_BI)
344
345#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
346#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
347#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
348
349
350/*
351 * BR2/3 and OR2/3 (SDRAM)
352 *
353 */
354#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
355#define SDRAM_BASE2_PRELIM 0x20000000 /* SDRAM bank #1 */
356#define SDRAM_BASE3_PRELIM 0x30000000 /* SDRAM bank #2 */
357#define SDRAM_MAX_SIZE 0x04000000 /* max 648 MB per bank */
358
359/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
360#define CFG_OR_TIMING_SDRAM 0x00000A00
361
362#if 0
363#define CFG_OR1_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
364#define CFG_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
365
366#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
367#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
368
369#define CFG_OR3_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
370#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
371#endif
372
373
374/*
375 * Memory Periodic Timer Prescaler
376 *
377 * The Divider for PTA (refresh timer) configuration is based on an
378 * example SDRAM configuration (64 MBit, one bank). The adjustment to
379 * the number of chip selects (NCS) and the actually needed refresh
380 * rate is done by setting MPTPR.
381 *
382 * PTA is calculated from
383 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
384 *
385 * gclk CPU clock (not bus clock!)
386 * Trefresh Refresh cycle * 4 (four word bursts used)
387 *
388 * 4096 Rows from SDRAM example configuration
389 * 1000 factor s -> ms
390 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
391 * 4 Number of refresh cycles per period
392 * 64 Refresh cycle in ms per number of rows
393 * --------------------------------------------
394 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
395 *
396 * 50 MHz => 50.000.000 / Divider = 98
397 * 66 Mhz => 66.000.000 / Divider = 129
398 * 80 Mhz => 80.000.000 / Divider = 156
399 */
400#if defined(CONFIG_80MHz)
401#define CFG_MAMR_PTA 156
402#elif defined(CONFIG_66MHz)
403#define CFG_MAMR_PTA 129
404#else /* 50 MHz */
405#define CFG_MAMR_PTA 98
406#endif /*CONFIG_??MHz */
407
408/*
409 * For 16 MBit, refresh rates could be 31.3 us
410 * (= 64 ms / 2K = 125 / quad bursts).
411 * For a simpler initialization, 15.6 us is used instead.
412 *
413 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
414 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
415 */
416#define CFG_MPTPR 0x400
417
418/*
419 * MAMR settings for SDRAM
420 */
421#define CFG_MAMR 0x80802114
422
423/*
424 * Internal Definitions
425 *
426 * Boot Flags
427 */
428#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
429#define BOOTFLAG_WARM 0x02 /* Software reboot */
430
431
wdenka6c7ad22002-12-03 21:28:10 +0000432#if NOT_USED_FOR_NOW
wdenk56f94be2002-11-05 16:35:14 +0000433#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
434#if 0
435#define CONFIG_AUTOBOOT_PROMPT "Boote in %d Sekunden - stop mit \"2\"\n"
436#endif
437#define CONFIG_AUTOBOOT_STOP_STR "2" /* easy to stop for now */
wdenka6c7ad22002-12-03 21:28:10 +0000438#endif /* NOT_USED_FOR_NOW */
wdenk56f94be2002-11-05 16:35:14 +0000439
440#endif /* __CONFIG_H */