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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/* ------------------------------------------------------------------------- */
25
26/*
27 * board/config.h - configuration options, board specific
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37
38#define CONFIG_MPC824X 1
39#define CONFIG_MPC8240 1
40#define CONFIG_SANDPOINT 1
41
42#if 0
43#define USE_DINK32 1
44#else
45#undef USE_DINK32
46#endif
47
48#define CONFIG_CONS_INDEX 1
49#define CONFIG_BAUDRATE 115200
50#define CONFIG_DRAM_SPEED 100 /* MHz */
51
52#define CONFIG_COMMANDS ( (CONFIG_CMD_DFL & ~CFG_CMD_AUTOSCRIPT) | \
53 CFG_CMD_ELF | \
54 CFG_CMD_I2C | \
55 CFG_CMD_SDRAM | \
56 CFG_CMD_EEPROM | \
57 CFG_CMD_PCI )
58
59/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
60#include <cmd_confdefs.h>
61
62
63/*
64 * Miscellaneous configurable options
65 */
66#define CFG_LONGHELP 1 /* undef to save memory */
67#define CFG_PROMPT "=> " /* Monitor Command Prompt */
68#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
69#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
70#define CFG_MAXARGS 16 /* max number of command args */
71#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
72#define CFG_LOAD_ADDR 0x00100000 /* default load address */
73#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
74
75/*-----------------------------------------------------------------------
76 * PCI stuff
77 *-----------------------------------------------------------------------
78 */
79#define CONFIG_PCI /* include pci support */
80#undef CONFIG_PCI_PNP
81
82#define CONFIG_NET_MULTI /* Multi ethernet cards support */
83
84#define CONFIG_EEPRO100
85
86#define PCI_ENET0_IOADDR 0x80000000
87#define PCI_ENET0_MEMADDR 0x80000000
88#define PCI_ENET1_IOADDR 0x81000000
89#define PCI_ENET1_MEMADDR 0x81000000
90
91
92/*-----------------------------------------------------------------------
93 * Start addresses for the final memory configuration
94 * (Set up by the startup code)
95 * Please note that CFG_SDRAM_BASE _must_ start at 0
96 */
97#define CFG_SDRAM_BASE 0x00000000
98#define CFG_MAX_RAM_SIZE 0x10000000
99
100#define CFG_RESET_ADDRESS 0xFFF00100
101
102#if defined (USE_DINK32)
103#define CFG_MONITOR_LEN 0x00030000
104#define CFG_MONITOR_BASE 0x00090000
105#define CFG_RAMBOOT 1
106#define CFG_INIT_RAM_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
107#define CFG_INIT_RAM_END 0x10000
108#define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
109#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
110#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
111#else
112#undef CFG_RAMBOOT
113#define CFG_MONITOR_LEN 0x00030000
114#define CFG_MONITOR_BASE TEXT_BASE
115
116/*#define CFG_GBL_DATA_SIZE 256*/
117#define CFG_GBL_DATA_SIZE 128
118
119#define CFG_INIT_RAM_ADDR 0x40000000
120#define CFG_INIT_RAM_END 0x1000
121#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
122
123#endif
124
125#define CFG_FLASH_BASE 0xFFF00000
126#if 0
127#define CFG_FLASH_SIZE (512 * 1024) /* sandpoint has tiny eeprom */
128#else
129#define CFG_FLASH_SIZE (1024 * 1024) /* Unity has onboard 1MByte flash */
130#endif
131#define CFG_ENV_IS_IN_FLASH 1
132#define CFG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */
133#define CFG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
134
135#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
136
137#define CFG_MEMTEST_START 0x00000000 /* memtest works on */
138#define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
139
140#define CFG_EUMB_ADDR 0xFC000000
141
142#define CFG_ISA_MEM 0xFD000000
143#define CFG_ISA_IO 0xFE000000
144
145#define CFG_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */
146#define CFG_FLASH_RANGE_SIZE 0x01000000
147#define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */
148#define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */
149
150/*
151 * select i2c support configuration
152 *
153 * Supported configurations are {none, software, hardware} drivers.
154 * If the software driver is chosen, there are some additional
155 * configuration items that the driver uses to drive the port pins.
156 */
157#define CONFIG_HARD_I2C 1 /* To enable I2C support */
158#undef CONFIG_SOFT_I2C /* I2C bit-banged */
159#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
160#define CFG_I2C_SLAVE 0x7F
161
162#ifdef CONFIG_SOFT_I2C
163#error "Soft I2C is not configured properly. Please review!"
164#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
165#define I2C_ACTIVE (iop->pdir |= 0x00010000)
166#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
167#define I2C_READ ((iop->pdat & 0x00010000) != 0)
168#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
169 else iop->pdat &= ~0x00010000
170#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
171 else iop->pdat &= ~0x00020000
172#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
173#endif /* CONFIG_SOFT_I2C */
174
175
176#define CFG_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
177#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
178#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* write page size */
179#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
180
181
182#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
183#define CFG_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
184
185/*-----------------------------------------------------------------------
186 * Definitions for initial stack pointer and data area (in DPRAM)
187 */
188
189
190#define CFG_WINBOND_83C553 1 /*has a winbond bridge */
191#define CFG_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */
192#define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */
193#define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */
194
195#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */
196#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
197
198/*
199 * NS87308 Configuration
200 */
201#define CFG_NS87308 /* Nat Semi super-io controller on ISA bus */
202
203#define CFG_NS87308_BADDR_10 1
204
205#define CFG_NS87308_DEVS ( CFG_NS87308_UART1 | \
206 CFG_NS87308_UART2 | \
207 CFG_NS87308_POWRMAN | \
208 CFG_NS87308_RTC_APC )
209
210#undef CFG_NS87308_PS2MOD
211
212#define CFG_NS87308_CS0_BASE 0x0076
213#define CFG_NS87308_CS0_CONF 0x30
214#define CFG_NS87308_CS1_BASE 0x0075
215#define CFG_NS87308_CS1_CONF 0x30
216#define CFG_NS87308_CS2_BASE 0x0074
217#define CFG_NS87308_CS2_CONF 0x30
218
219/*
220 * NS16550 Configuration
221 */
222#define CFG_NS16550
223#define CFG_NS16550_SERIAL
224
225#define CFG_NS16550_REG_SIZE 1
226
227#define CFG_NS16550_CLK 1843200
228
229#define CFG_NS16550_COM1 (CFG_ISA_IO + CFG_NS87308_UART1_BASE)
230#define CFG_NS16550_COM2 (CFG_ISA_IO + CFG_NS87308_UART2_BASE)
231
232/*
233 * Low Level Configuration Settings
234 * (address mappings, register initial values, etc.)
235 * You should know what you are doing if you make changes here.
236 */
237
238#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
239#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2
240
241#define CFG_ROMNAL 7 /*rom/flash next access time */
242#define CFG_ROMFAL 11 /*rom/flash access time */
243
244#define CFG_REFINT 430 /* no of clock cycles between CBR refresh cycles */
245
246/* the following are for SDRAM only*/
247#define CFG_BSTOPRE 121 /* Burst To Precharge, sets open page interval */
248#define CFG_REFREC 8 /* Refresh to activate interval */
249#define CFG_RDLAT 4 /* data latency from read command */
250#define CFG_PRETOACT 3 /* Precharge to activate interval */
251#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
252#define CFG_ACTORW 3 /* Activate to R/W */
253#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
254#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
255#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */
256
257#define CFG_REGISTERD_TYPE_BUFFER 1
258
259/* memory bank settings*/
260/*
261 * only bits 20-29 are actually used from these vales to set the
262 * start/end address the upper two bits will be 0, and the lower 20
263 * bits will be set to 0x00000 for a start address, or 0xfffff for an
264 * end address
265 */
266#define CFG_BANK0_START 0x00000000
267#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
268#define CFG_BANK0_ENABLE 1
269#define CFG_BANK1_START 0x3ff00000
270#define CFG_BANK1_END 0x3fffffff
271#define CFG_BANK1_ENABLE 0
272#define CFG_BANK2_START 0x3ff00000
273#define CFG_BANK2_END 0x3fffffff
274#define CFG_BANK2_ENABLE 0
275#define CFG_BANK3_START 0x3ff00000
276#define CFG_BANK3_END 0x3fffffff
277#define CFG_BANK3_ENABLE 0
278#define CFG_BANK4_START 0x00000000
279#define CFG_BANK4_END 0x00000000
280#define CFG_BANK4_ENABLE 0
281#define CFG_BANK5_START 0x00000000
282#define CFG_BANK5_END 0x00000000
283#define CFG_BANK5_ENABLE 0
284#define CFG_BANK6_START 0x00000000
285#define CFG_BANK6_END 0x00000000
286#define CFG_BANK6_ENABLE 0
287#define CFG_BANK7_START 0x00000000
288#define CFG_BANK7_END 0x00000000
289#define CFG_BANK7_ENABLE 0
290/*
291 * Memory bank enable bitmask, specifying which of the banks defined above
292 are actually present. MSB is for bank #7, LSB is for bank #0.
293 */
294#define CFG_BANK_ENABLE 0x01
295
296#define CFG_ODCR 0xff /* configures line driver impedances, */
297 /* see 8240 book for bit definitions */
298#define CFG_PGMAX 0x32 /* how long the 8240 retains the */
299 /* currently accessed page in memory */
300 /* see 8240 book for details */
301
302/* SDRAM 0 - 256MB */
303#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
304#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
305
306/* stack in DCACHE @ 1GB (no backing mem) */
307#if defined(USE_DINK32)
308#define CFG_IBAT1L (0x40000000 | BATL_PP_00 )
309#define CFG_IBAT1U (0x40000000 | BATU_BL_128K )
310#else
311#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
312#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
313#endif
314
315/* PCI memory */
316#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
317#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
318
319/* Flash, config addrs, etc */
320#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
321#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
322
323#define CFG_DBAT0L CFG_IBAT0L
324#define CFG_DBAT0U CFG_IBAT0U
325#define CFG_DBAT1L CFG_IBAT1L
326#define CFG_DBAT1U CFG_IBAT1U
327#define CFG_DBAT2L CFG_IBAT2L
328#define CFG_DBAT2U CFG_IBAT2U
329#define CFG_DBAT3L CFG_IBAT3L
330#define CFG_DBAT3U CFG_IBAT3U
331
332/*
333 * For booting Linux, the board info and command line data
334 * have to be in the first 8 MB of memory, since this is
335 * the maximum mapped by the Linux kernel during initialization.
336 */
337#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
338/*-----------------------------------------------------------------------
339 * FLASH organization
340 */
341#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
342#define CFG_MAX_FLASH_SECT 20 /* max number of sectors on one chip */
343
344#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
345#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
346
347/*-----------------------------------------------------------------------
348 * Cache Configuration
349 */
350#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */
351#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
352# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
353#endif
354
355
356/*
357 * Internal Definitions
358 *
359 * Boot Flags
360 */
361#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
362#define BOOTFLAG_WARM 0x02 /* Software reboot */
363
364
365/* values according to the manual */
366
367#define CONFIG_DRAM_50MHZ 1
368#define CONFIG_SDRAM_50MHZ
369
370#undef NR_8259_INTS
371#define NR_8259_INTS 1
372
373
374#define CONFIG_DISK_SPINUP_TIME 1000000
375
376
377#endif /* __CONFIG_H */