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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 4d75a504d00e65253229e1d1b798a7c37041f078 / . / include / configs / cradle.h
blob: 5a215e495f0113a7954de469c0e9e1cb0d8af1d9 [file] [log] [blame]
wdenkd9fd6ff2002-10-11 08:43:32 +0000[diff] [blame]1/*
2 * (C) Copyright 2002
3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4 *
5 * (C) Copyright 2002
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * If we are developing, we might want to start armboot from ram
33 * so we MUST NOT initialize critical regs like mem-timing ...
34 */
35#define CONFIG_INIT_CRITICAL /* undef for developing */
36
37/*
38 * High Level Configuration Options
39 * (easy to change)
40 */
41#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
42#define CONFIG_HHP_CRADLE 1 /* on an Cradle Board */
43
44#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
45
46/*
47 * Size of malloc() pool
48 */
wdenk699b13a2002-11-03 18:03:52 +0000[diff] [blame]49#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
wdenkd9fd6ff2002-10-11 08:43:32 +0000[diff] [blame]50
51/*
52 * Hardware drivers
53 */
54#define CONFIG_DRIVER_SMC91111
55#define CONFIG_SMC91111_BASE 0x10000300
56#define CONFIG_SMC91111_EXT_PHY
57#define CONFIG_SMC_USE_32_BIT
58
59/*
60 * select serial console configuration
61 */
62#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */
63
64/* allow to overwrite serial and ethaddr */
65#define CONFIG_ENV_OVERWRITE
66
67#define CONFIG_BAUDRATE 115200
68
69#define CONFIG_COMMANDS (CONFIG_CMD_DFL)
70
71/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
72#include <cmd_confdefs.h>
73
74#define CONFIG_BOOTDELAY 3
75#define CONFIG_BOOTARGS "root=/dev/mtdblock2 console=ttyS0,115200"
76#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
77#define CONFIG_NETMASK 255.255.0.0
78#define CONFIG_IPADDR 192.168.0.21
79#define CONFIG_SERVERIP 192.168.0.250
80#define CONFIG_BOOTCOMMAND "bootm 40000"
81#define CONFIG_CMDLINE_TAG
82
83/*
84 * Miscellaneous configurable options
85 */
86#define CFG_LONGHELP /* undef to save memory */
87#define CFG_PROMPT "=> " /* Monitor Command Prompt */
88#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
89#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
90#define CFG_MAXARGS 16 /* max number of command args */
91#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
92
93#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
94#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
95
96#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
97
98#define CFG_LOAD_ADDR 0xa2000000 /* default load address */
99
100#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
101#define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
102
103 /* valid baudrates */
104#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
105
106/*
107 * Stack sizes
108 *
109 * The stack sizes are set up in start.S using the settings below
110 */
111#define CONFIG_STACKSIZE (128*1024) /* regular stack */
112#ifdef CONFIG_USE_IRQ
113#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
114#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
115#endif
116
117/*
118 * Physical Memory Map
119 */
120#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
121#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
122#define PHYS_SDRAM_1_SIZE 0x01000000 /* 64 MB */
123#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
124#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
125#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
126#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
127#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
128#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
129
130#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
131#define PHYS_FLASH_2 0x04000000 /* Flash Bank #1 */
132#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
133
134#define CFG_DRAM_BASE 0xa0000000
135#define CFG_DRAM_SIZE 0x04000000
136
137#define CFG_FLASH_BASE PHYS_FLASH_1
138
139/*
140 * FLASH and environment organization
141 */
142#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
143#define CFG_MAX_FLASH_SECT 32 /* max number of sectors on one chip */
144
145/* timeout values are in ticks */
146#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
147#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
148
149#define CFG_ENV_IS_IN_FLASH 1
150#define CFG_ENV_ADDR 0x00020000 /* absolute address for now */
151#define CFG_ENV_SIZE 0x20000 /* 8K ouch, this may later be */
152
153/******************************************************************************
154 *
155 * CPU specific defines
156 *
157 ******************************************************************************/
158
159/*
160 * GPIO settings
161 *
162 * GPIO pin assignments
163 * GPIO Name Dir Out AF
164 * 0 NC
165 * 1 NC
166 * 2 SIRQ1 I
167 * 3 SIRQ2 I
168 * 4 SIRQ3 I
169 * 5 DMAACK1 O 0
170 * 6 DMAACK2 O 0
171 * 7 DMAACK3 O 0
172 * 8 TC1 O 0
173 * 9 TC2 O 0
174 * 10 TC3 O 0
175 * 11 nDMAEN O 1
176 * 12 AENCTRL O 0
177 * 13 PLDTC O 0
178 * 14 ETHIRQ I
179 * 15 NC
180 * 16 NC
181 * 17 NC
182 * 18 RDY I
183 * 19 DMASIO I
184 * 20 ETHIRQ NC
185 * 21 NC
186 * 22 PGMEN O 1 FIXME for debug only enable flash
187 * 23 NC
188 * 24 NC
189 * 25 NC
190 * 26 NC
191 * 27 NC
192 * 28 NC
193 * 29 NC
194 * 30 NC
195 * 31 NC
196 * 32 NC
197 * 33 NC
198 * 34 FFRXD I 01
199 * 35 FFCTS I 01
200 * 36 FFDCD I 01
201 * 37 FFDSR I 01
202 * 38 FFRI I 01
203 * 39 FFTXD O 1 10
204 * 40 FFDTR O 0 10
205 * 41 FFRTS O 0 10
206 * 42 RS232FOFF O 0 00
207 * 43 NC
208 * 44 NC
209 * 45 IRSL0 O 0
210 * 46 IRRX0 I 01
211 * 47 IRTX0 O 0 10
212 * 48 NC
213 * 49 nIOWE O 0
214 * 50 NC
215 * 51 NC
216 * 52 NC
217 * 53 NC
218 * 54 NC
219 * 55 NC
220 * 56 NC
221 * 57 NC
222 * 58 DKDIRQ I
223 * 59 NC
224 * 60 NC
225 * 61 NC
226 * 62 NC
227 * 63 NC
228 * 64 COMLED O 0
229 * 65 COMLED O 0
230 * 66 COMLED O 0
231 * 67 COMLED O 0
232 * 68 COMLED O 0
233 * 69 COMLED O 0
234 * 70 COMLED O 0
235 * 71 COMLED O 0
236 * 72 NC
237 * 73 NC
238 * 74 NC
239 * 75 NC
240 * 76 NC
241 * 77 NC
242 * 78 CSIO O 1
243 * 79 NC
244 * 80 CSETH O 1
245 *
246 * NOTE: All NC's are defined to be outputs
247 *
248 */
249/* Pin direction control */
250/* NOTE GPIO 0, 61, 62 are set for inputs due to CPLD SPAREs */
251#define CFG_GPDR0_VAL 0xfff3bf02
252#define CFG_GPDR1_VAL 0xfbffbf83
253#define CFG_GPDR2_VAL 0x0001ffff
254/* Set and Clear registers */
255#define CFG_GPSR0_VAL 0x00400800
256#define CFG_GPSR1_VAL 0x00000480
257#define CFG_GPSR2_VAL 0x00014000
258#define CFG_GPCR0_VAL 0x00000000
259#define CFG_GPCR1_VAL 0x00000000
260#define CFG_GPCR2_VAL 0x00000000
261/* Edge detect registers (these are set by the kernel) */
262#define CFG_GRER0_VAL 0x00000000
263#define CFG_GRER1_VAL 0x00000000
264#define CFG_GRER2_VAL 0x00000000
265#define CFG_GFER0_VAL 0x00000000
266#define CFG_GFER1_VAL 0x00000000
267#define CFG_GFER2_VAL 0x00000000
268/* Alternate function registers */
269#define CFG_GAFR0_L_VAL 0x00000000
270#define CFG_GAFR0_U_VAL 0x00000010
271#define CFG_GAFR1_L_VAL 0x900a9550
272#define CFG_GAFR1_U_VAL 0x00000008
273#define CFG_GAFR2_L_VAL 0x20000000
274#define CFG_GAFR2_U_VAL 0x00000002
275
276/*
277 * Clocks, power control and interrupts
278 */
279#define CFG_PSSR_VAL 0x00000020
280#define CFG_CCCR_VAL 0x00000141 /* 100 MHz memory, 200 MHz CPU */
281#define CFG_CKEN_VAL 0x00000060 /* FFUART and STUART enabled */
282#define CFG_ICMR_VAL 0x00000000 /* No interrupts enabled */
283
284/* FIXME
285 *
286 * RTC settings
287 * Watchdog
288 *
289 */
290
291/*
292 * Memory settings
293 *
294 * FIXME Can ethernet be burst read and/or write?? This is set for lubbock
295 * Verify timings on all
296 */
297#define CFG_MSC0_VAL 0x000023FA /* flash bank (cs0) */
298/*#define CFG_MSC1_VAL 0x00003549 / * SuperIO bank (cs2) */
299#define CFG_MSC1_VAL 0x0000354c /* SuperIO bank (cs2) */
300#define CFG_MSC2_VAL 0x00001224 /* Ethernet bank (cs4) */
301#ifdef REDBOOT_WAY
302#define CFG_MDCNFG_VAL 0x00001aa1 /* FIXME can DTC be 01? */
303#define CFG_MDMRS_VAL 0x00000000
304#define CFG_MDREFR_VAL 0x00018018
305#else
306#define CFG_MDCNFG_VAL 0x00001aa1 /* FIXME can DTC be 01? */
307#define CFG_MDMRS_VAL 0x00000000
308#define CFG_MDREFR_VAL 0x00403018 /* Initial setting, individual bits set in memsetup.S */
309#endif
310
311/*
312 * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
313 */
314#define CFG_MECR_VAL 0x00000000
315#define CFG_MCMEM0_VAL 0x00010504
316#define CFG_MCMEM1_VAL 0x00010504
317#define CFG_MCATT0_VAL 0x00010504
318#define CFG_MCATT1_VAL 0x00010504
319#define CFG_MCIO0_VAL 0x00004715
320#define CFG_MCIO1_VAL 0x00004715
321
322/* Board specific defines */
323
324/* LED defines */
325#define YELLOW 0x03
326#define RED 0x02
327#define GREEN 0x01
328#define OFF 0x00
329#define LED_IRDA0 0
330#define LED_IRDA1 2
331#define LED_IRDA2 4
332#define LED_IRDA3 6
333#define CRADLE_LED_SET_REG GPSR2
334#define CRADLE_LED_CLR_REG GPCR2
335
336/* SuperIO defines */
337#define CRADLE_SIO_INDEX 0x2e
338#define CRADLE_SIO_DATA 0x2f
339
340/* IO defines */
341#define CRADLE_CPLD_PHYS 0x08000000
342#define CRADLE_SIO1_PHYS 0x08100000
343#define CRADLE_SIO2_PHYS 0x08200000
344#define CRADLE_SIO3_PHYS 0x08300000
345#define CRADLE_ETH_PHYS 0x10000000
346
347#ifndef __ASSEMBLY__
348
349/* global prototypes */
350void led_code(int code, int color);
351
352#endif
353
354#endif /* __CONFIG_H */