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Mario Sixaed7d0e2019-01-21 09:18:23 +01001/*
2 * Internal Definitions
3 */
Simon Glass1af3c7f2020-05-10 11:40:09 -06004#include <linux/stringify.h>
Mario Sixaed7d0e2019-01-21 09:18:23 +01005#define BOOTFLASH_START 0xF0000000
6
Mario Sixaed7d0e2019-01-21 09:18:23 +01007/*
8 * DDR Setup
9 */
10#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
11#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
12
13#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
14 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
15
16#define CFG_83XX_DDR_USES_CS0
17
18/*
19 * Manually set up DDR parameters
20 */
21#define CONFIG_DDR_II
22#define CONFIG_SYS_DDR_SIZE 2048 /* MB */
23
24/*
25 * The reserved memory
26 */
27#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
28#define CONFIG_SYS_FLASH_BASE 0xF0000000
29
30#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
31#define CONFIG_SYS_RAMBOOT
32#endif
33
34/* Reserve 768 kB for Mon */
35#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
36
37/*
38 * Initial RAM Base Address Setup
39 */
40#define CONFIG_SYS_INIT_RAM_LOCK
41#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
42#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
43#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
44 GENERATED_GBL_DATA_SIZE)
45/*
46 * Init Local Bus Memory Controller:
47 *
48 * Bank Bus Machine PortSz Size Device
49 * ---- --- ------- ------ ----- ------
50 * 0 Local GPCM 16 bit 256MB FLASH
51 * 1 Local GPCM 8 bit 128MB GPIO/PIGGY
52 *
53 */
54
55/*
56 * FLASH on the Local Bus
57 */
58#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
59
60#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
61#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
62#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
63
64/*
65 * Serial Port
66 */
67#define CONFIG_SYS_NS16550_SERIAL
68#define CONFIG_SYS_NS16550_REG_SIZE 1
69#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
70
71#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
72#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
73
74/* I2C */
75#define CONFIG_SYS_I2C
76#define CONFIG_SYS_NUM_I2C_BUSES 4
77#define CONFIG_SYS_I2C_MAX_HOPS 1
78#define CONFIG_SYS_I2C_FSL
79#define CONFIG_SYS_FSL_I2C_SPEED 200000
80#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
81#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
82#define CONFIG_SYS_I2C_OFFSET 0x3000
83#define CONFIG_SYS_FSL_I2C2_SPEED 200000
84#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
85#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
86#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
87 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
88 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
89 {1, {I2C_NULL_HOP} } }
90
Mario Sixaed7d0e2019-01-21 09:18:23 +010091#if defined(CONFIG_CMD_NAND)
92#define CONFIG_NAND_KMETER1
93#define CONFIG_SYS_MAX_NAND_DEVICE 1
94#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE
95#endif
96
97/*
98 * For booting Linux, the board info and command line data
99 * have to be in the first 8 MB of memory, since this is
100 * the maximum mapped by the Linux kernel during initialization.
101 */
102#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
103
104/*
105 * Environment
106 */
107
108#ifndef CONFIG_SYS_RAMBOOT
Mario Sixaed7d0e2019-01-21 09:18:23 +0100109/* Address and size of Redundant Environment Sector */
Mario Sixaed7d0e2019-01-21 09:18:23 +0100110#endif /* CFG_SYS_RAMBOOT */
111
112/*
113 * Environment Configuration
114 */
Mario Sixaed7d0e2019-01-21 09:18:23 +0100115#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
116#define CONFIG_KM_DEF_ENV "km-common=empty\0"
117#endif
118
119#ifndef CONFIG_KM_DEF_ARCH
120#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
121#endif
122
123#define CONFIG_EXTRA_ENV_SETTINGS \
124 CONFIG_KM_DEF_ENV \
125 CONFIG_KM_DEF_ARCH \
126 "newenv=" \
127 "prot off " __stringify(CONFIG_ENV_ADDR) " +0x40000 && " \
128 "era " __stringify(CONFIG_ENV_ADDR) " +0x40000\0" \
129 "unlock=yes\0" \
130 ""
131
132#if defined(CONFIG_UEC_ETH)
133#define CONFIG_HAS_ETH0
134#endif
135
136/*
137 * QE UEC ethernet configuration
138 */
139#define CONFIG_UEC_ETH
140#define CONFIG_ETHPRIME "UEC0"