blob: d022faaa91a48aec7341af9b7f00389a1ad8d8ba [file] [log] [blame]
Marek Vasut4d573d52022-05-21 16:56:26 +02001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2022 Marek Vasut <marex@denx.de>
4 */
5
6#ifndef __IMX8MP_DHCOM_PDK2_H
7#define __IMX8MP_DHCOM_PDK2_H
8
9#include <linux/sizes.h>
10#include <linux/stringify.h>
11#include <asm/arch/imx-regs.h>
12
Marek Vasut4d573d52022-05-21 16:56:26 +020013/* Link Definitions */
Tom Rini65cc0e22022-11-16 13:10:41 -050014#define CFG_SYS_INIT_RAM_ADDR 0x40000000
15#define CFG_SYS_INIT_RAM_SIZE 0x200000
Marek Vasut4d573d52022-05-21 16:56:26 +020016
Tom Riniaa6e94d2022-11-16 13:10:37 -050017#define CFG_SYS_SDRAM_BASE 0x40000000
Marek Vasut4d573d52022-05-21 16:56:26 +020018#define PHYS_SDRAM 0x40000000
19#define PHYS_SDRAM_SIZE 0x20000000 /* Minimum 512 MiB DDR */
20
Tom Rini4db38662022-12-04 10:04:55 -050021#define CFG_MXC_UART_BASE UART1_BASE_ADDR
Marek Vasut4d573d52022-05-21 16:56:26 +020022
Marek Vasut4d573d52022-05-21 16:56:26 +020023/* PHY needs a longer autonegotiation timeout after reset */
24#define PHY_ANEG_TIMEOUT 20000
25#define FEC_QUIRK_ENET_MAC
26
27/* USDHC */
Tom Rini6cc04542022-10-28 20:27:13 -040028#define CFG_SYS_FSL_USDHC_NUM 2
29#define CFG_SYS_FSL_ESDHC_ADDR 0
Marek Vasut4d573d52022-05-21 16:56:26 +020030
Tom Rini0613c362022-12-04 10:03:50 -050031#define CFG_EXTRA_ENV_SETTINGS \
Marek Vasut4d573d52022-05-21 16:56:26 +020032 "altbootcmd=run bootcmd ; reset\0" \
33 "bootlimit=3\0" \
34 "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
35 "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
36 "ramdisk_addr_r=0x58000000\0" \
37 "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
38 /* Give slow devices beyond USB HUB chance to come up. */ \
39 "usb_pgood_delay=2000\0" \
40 "dfu_alt_info=" \
41 /* RAM block at DRAM offset 256..768 MiB */ \
42 "ram ram0=ram ram 0x50000000 0x20000000&" \
43 /* 16 MiB SPI NOR */ \
44 "mtd nor0=sf raw 0x0 0x1000000\0" \
45 "dh_update_env=" \
46 "setenv dh_update_env true ; saveenv ; saveenv\0" \
47 "dh_update_sf_gen_fcfb=" \
48 "setexpr sfaddr ${loadaddr} - 0x1000 ; " \
49 "base ${sfaddr} ; " \
50 "mw 0 0 0x400 ; " \
51 "mw 0x400 0x42464346 ; " \
52 "mw 0x404 0x56010000 ; " \
53 "mw 0x40c 00030300 ; " \
54 "mw 0x444 0x00020101 ; " \
55 "mw 0x450 0x10000000 ; " \
56 "mw 0x480 0x0818040b ; " \
57 "mw 0x484 0x24043008 ; " \
58 "mw 0x5c0 0x100 ; " \
59 "mw 0x5c4 0x10000 ; " \
60 "base 0\0" \
61 "dh_update_sf_write_data=" \
62 "setexpr sfaddr ${loadaddr} - 0x1000 ; " \
63 "setexpr filesize ${filesize} + 0x1000 ; " \
64 "sf probe && sf update ${sfaddr} 0 ${filesize}\0" \
65 "dh_update_sd_to_sf=" \
66 "load mmc 0:1 ${loadaddr} boot/flash.bin && " \
67 "run dh_update_sf_gen_fcfb dh_update_sf_write_data\0" \
68 "dh_update_emmc_to_sf=" \
69 "load mmc 1:1 ${loadaddr} boot/flash.bin && " \
70 "run dh_update_sf_gen_fcfb dh_update_sf_write_data\0" \
71 BOOTENV
72
73#define BOOT_TARGET_DEVICES(func) \
74 func(MMC, mmc, 0) \
75 func(MMC, mmc, 1) \
76 func(USB, usb, 0) \
77 func(DHCP, dhcp, na)
78
79#include <config_distro_bootcmd.h>
80
81#endif