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Thomas Chouf6569882010-04-15 22:32:38 +08001/*
2 * Opencore 10/100 ethernet mac driver
3 *
4 * Copyright (C) 2007-2008 Avionic Design Development GmbH
5 * Copyright (C) 2008-2009 Avionic Design GmbH
6 * Thierry Reding <thierry.reding@avionic-design.de>
7 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <common.h>
15#include <command.h>
16#include <malloc.h>
17#include <net.h>
18#include <miiphy.h>
19#include <asm/io.h>
20#include <asm/cache.h>
21
22/* register offsets */
23#define MODER 0x00
24#define INT_SOURCE 0x04
25#define INT_MASK 0x08
26#define IPGT 0x0c
27#define IPGR1 0x10
28#define IPGR2 0x14
29#define PACKETLEN 0x18
30#define COLLCONF 0x1c
31#define TX_BD_NUM 0x20
32#define CTRLMODER 0x24
33#define MIIMODER 0x28
34#define MIICOMMAND 0x2c
35#define MIIADDRESS 0x30
36#define MIITX_DATA 0x34
37#define MIIRX_DATA 0x38
38#define MIISTATUS 0x3c
39#define MAC_ADDR0 0x40
40#define MAC_ADDR1 0x44
41#define ETH_HASH0 0x48
42#define ETH_HASH1 0x4c
43#define ETH_TXCTRL 0x50
44
45/* mode register */
46#define MODER_RXEN (1 << 0) /* receive enable */
47#define MODER_TXEN (1 << 1) /* transmit enable */
48#define MODER_NOPRE (1 << 2) /* no preamble */
49#define MODER_BRO (1 << 3) /* broadcast address */
50#define MODER_IAM (1 << 4) /* individual address mode */
51#define MODER_PRO (1 << 5) /* promiscuous mode */
52#define MODER_IFG (1 << 6) /* interframe gap for incoming frames */
53#define MODER_LOOP (1 << 7) /* loopback */
54#define MODER_NBO (1 << 8) /* no back-off */
55#define MODER_EDE (1 << 9) /* excess defer enable */
56#define MODER_FULLD (1 << 10) /* full duplex */
57#define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */
58#define MODER_DCRC (1 << 12) /* delayed CRC enable */
59#define MODER_CRC (1 << 13) /* CRC enable */
60#define MODER_HUGE (1 << 14) /* huge packets enable */
61#define MODER_PAD (1 << 15) /* padding enabled */
62#define MODER_RSM (1 << 16) /* receive small packets */
63
64/* interrupt source and mask registers */
65#define INT_MASK_TXF (1 << 0) /* transmit frame */
66#define INT_MASK_TXE (1 << 1) /* transmit error */
67#define INT_MASK_RXF (1 << 2) /* receive frame */
68#define INT_MASK_RXE (1 << 3) /* receive error */
69#define INT_MASK_BUSY (1 << 4)
70#define INT_MASK_TXC (1 << 5) /* transmit control frame */
71#define INT_MASK_RXC (1 << 6) /* receive control frame */
72
73#define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE)
74#define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE)
75
76#define INT_MASK_ALL ( \
77 INT_MASK_TXF | INT_MASK_TXE | \
78 INT_MASK_RXF | INT_MASK_RXE | \
79 INT_MASK_TXC | INT_MASK_RXC | \
80 INT_MASK_BUSY \
81 )
82
83/* packet length register */
84#define PACKETLEN_MIN(min) (((min) & 0xffff) << 16)
85#define PACKETLEN_MAX(max) (((max) & 0xffff) << 0)
86#define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \
87 PACKETLEN_MAX(max))
88
89/* transmit buffer number register */
90#define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80)
91
92/* control module mode register */
93#define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */
94#define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */
95#define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */
96
97/* MII mode register */
98#define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */
99#define MIIMODER_NOPRE (1 << 8) /* no preamble */
100
101/* MII command register */
102#define MIICOMMAND_SCAN (1 << 0) /* scan status */
103#define MIICOMMAND_READ (1 << 1) /* read status */
104#define MIICOMMAND_WRITE (1 << 2) /* write control data */
105
106/* MII address register */
107#define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0)
108#define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8)
109#define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \
110 MIIADDRESS_RGAD(reg))
111
112/* MII transmit data register */
113#define MIITX_DATA_VAL(x) ((x) & 0xffff)
114
115/* MII receive data register */
116#define MIIRX_DATA_VAL(x) ((x) & 0xffff)
117
118/* MII status register */
119#define MIISTATUS_LINKFAIL (1 << 0)
120#define MIISTATUS_BUSY (1 << 1)
121#define MIISTATUS_INVALID (1 << 2)
122
123/* TX buffer descriptor */
124#define TX_BD_CS (1 << 0) /* carrier sense lost */
125#define TX_BD_DF (1 << 1) /* defer indication */
126#define TX_BD_LC (1 << 2) /* late collision */
127#define TX_BD_RL (1 << 3) /* retransmission limit */
128#define TX_BD_RETRY_MASK (0x00f0)
129#define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4)
130#define TX_BD_UR (1 << 8) /* transmitter underrun */
131#define TX_BD_CRC (1 << 11) /* TX CRC enable */
132#define TX_BD_PAD (1 << 12) /* pad enable */
133#define TX_BD_WRAP (1 << 13)
134#define TX_BD_IRQ (1 << 14) /* interrupt request enable */
135#define TX_BD_READY (1 << 15) /* TX buffer ready */
136#define TX_BD_LEN(x) (((x) & 0xffff) << 16)
137#define TX_BD_LEN_MASK (0xffff << 16)
138
139#define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \
140 TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR)
141
142/* RX buffer descriptor */
143#define RX_BD_LC (1 << 0) /* late collision */
144#define RX_BD_CRC (1 << 1) /* RX CRC error */
145#define RX_BD_SF (1 << 2) /* short frame */
146#define RX_BD_TL (1 << 3) /* too long */
147#define RX_BD_DN (1 << 4) /* dribble nibble */
148#define RX_BD_IS (1 << 5) /* invalid symbol */
149#define RX_BD_OR (1 << 6) /* receiver overrun */
150#define RX_BD_MISS (1 << 7)
151#define RX_BD_CF (1 << 8) /* control frame */
152#define RX_BD_WRAP (1 << 13)
153#define RX_BD_IRQ (1 << 14) /* interrupt request enable */
154#define RX_BD_EMPTY (1 << 15)
155#define RX_BD_LEN(x) (((x) & 0xffff) << 16)
156
157#define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \
158 RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS)
159
160#define ETHOC_BUFSIZ 1536
161#define ETHOC_ZLEN 64
162#define ETHOC_BD_BASE 0x400
163#define ETHOC_TIMEOUT (HZ / 2)
164#define ETHOC_MII_TIMEOUT (1 + (HZ / 5))
165
166/**
167 * struct ethoc - driver-private device structure
168 * @num_tx: number of send buffers
169 * @cur_tx: last send buffer written
170 * @dty_tx: last buffer actually sent
171 * @num_rx: number of receive buffers
172 * @cur_rx: current receive buffer
173 */
174struct ethoc {
175 u32 num_tx;
176 u32 cur_tx;
177 u32 dty_tx;
178 u32 num_rx;
179 u32 cur_rx;
180};
181
182/**
183 * struct ethoc_bd - buffer descriptor
184 * @stat: buffer statistics
185 * @addr: physical memory address
186 */
187struct ethoc_bd {
188 u32 stat;
189 u32 addr;
190};
191
Vasili Galka9f680d22014-08-26 13:46:17 +0300192static inline u32 ethoc_read(struct eth_device *dev, size_t offset)
Thomas Chouf6569882010-04-15 22:32:38 +0800193{
194 return readl(dev->iobase + offset);
195}
196
Vasili Galka9f680d22014-08-26 13:46:17 +0300197static inline void ethoc_write(struct eth_device *dev, size_t offset, u32 data)
Thomas Chouf6569882010-04-15 22:32:38 +0800198{
199 writel(data, dev->iobase + offset);
200}
201
202static inline void ethoc_read_bd(struct eth_device *dev, int index,
203 struct ethoc_bd *bd)
204{
Vasili Galka9f680d22014-08-26 13:46:17 +0300205 size_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
Thomas Chouf6569882010-04-15 22:32:38 +0800206 bd->stat = ethoc_read(dev, offset + 0);
207 bd->addr = ethoc_read(dev, offset + 4);
208}
209
210static inline void ethoc_write_bd(struct eth_device *dev, int index,
211 const struct ethoc_bd *bd)
212{
Vasili Galka9f680d22014-08-26 13:46:17 +0300213 size_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
Thomas Chouf6569882010-04-15 22:32:38 +0800214 ethoc_write(dev, offset + 0, bd->stat);
215 ethoc_write(dev, offset + 4, bd->addr);
216}
217
Thomas Chou3ac9d6c2010-04-27 20:20:27 +0800218static int ethoc_set_mac_address(struct eth_device *dev)
Thomas Chouf6569882010-04-15 22:32:38 +0800219{
220 u8 *mac = dev->enetaddr;
221
222 ethoc_write(dev, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
223 (mac[4] << 8) | (mac[5] << 0));
224 ethoc_write(dev, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0));
Thomas Chou3ac9d6c2010-04-27 20:20:27 +0800225 return 0;
Thomas Chouf6569882010-04-15 22:32:38 +0800226}
227
228static inline void ethoc_ack_irq(struct eth_device *dev, u32 mask)
229{
230 ethoc_write(dev, INT_SOURCE, mask);
231}
232
233static inline void ethoc_enable_rx_and_tx(struct eth_device *dev)
234{
235 u32 mode = ethoc_read(dev, MODER);
236 mode |= MODER_RXEN | MODER_TXEN;
237 ethoc_write(dev, MODER, mode);
238}
239
240static inline void ethoc_disable_rx_and_tx(struct eth_device *dev)
241{
242 u32 mode = ethoc_read(dev, MODER);
243 mode &= ~(MODER_RXEN | MODER_TXEN);
244 ethoc_write(dev, MODER, mode);
245}
246
247static int ethoc_init_ring(struct eth_device *dev)
248{
249 struct ethoc *priv = (struct ethoc *)dev->priv;
250 struct ethoc_bd bd;
251 int i;
252
253 priv->cur_tx = 0;
254 priv->dty_tx = 0;
255 priv->cur_rx = 0;
256
257 /* setup transmission buffers */
258 bd.stat = TX_BD_IRQ | TX_BD_CRC;
259
260 for (i = 0; i < priv->num_tx; i++) {
261 if (i == priv->num_tx - 1)
262 bd.stat |= TX_BD_WRAP;
263
264 ethoc_write_bd(dev, i, &bd);
265 }
266
267 bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
268
269 for (i = 0; i < priv->num_rx; i++) {
270 bd.addr = (u32)NetRxPackets[i];
271 if (i == priv->num_rx - 1)
272 bd.stat |= RX_BD_WRAP;
273
Stefan Kristiansson83ea1302011-11-04 02:38:06 +0000274 flush_dcache_range(bd.addr, bd.addr + PKTSIZE_ALIGN);
Thomas Chouf6569882010-04-15 22:32:38 +0800275 ethoc_write_bd(dev, priv->num_tx + i, &bd);
276 }
277
278 return 0;
279}
280
281static int ethoc_reset(struct eth_device *dev)
282{
283 u32 mode;
284
285 /* TODO: reset controller? */
286
287 ethoc_disable_rx_and_tx(dev);
288
289 /* TODO: setup registers */
290
291 /* enable FCS generation and automatic padding */
292 mode = ethoc_read(dev, MODER);
293 mode |= MODER_CRC | MODER_PAD;
294 ethoc_write(dev, MODER, mode);
295
296 /* set full-duplex mode */
297 mode = ethoc_read(dev, MODER);
298 mode |= MODER_FULLD;
299 ethoc_write(dev, MODER, mode);
300 ethoc_write(dev, IPGT, 0x15);
301
302 ethoc_ack_irq(dev, INT_MASK_ALL);
303 ethoc_enable_rx_and_tx(dev);
304 return 0;
305}
306
307static int ethoc_init(struct eth_device *dev, bd_t * bd)
308{
309 struct ethoc *priv = (struct ethoc *)dev->priv;
310 printf("ethoc\n");
311
Thomas Chouf6569882010-04-15 22:32:38 +0800312 priv->num_tx = 1;
313 priv->num_rx = PKTBUFSRX;
314 ethoc_write(dev, TX_BD_NUM, priv->num_tx);
315 ethoc_init_ring(dev);
316 ethoc_reset(dev);
317
318 return 0;
319}
320
321static int ethoc_update_rx_stats(struct ethoc_bd *bd)
322{
323 int ret = 0;
324
325 if (bd->stat & RX_BD_TL) {
326 debug("ETHOC: " "RX: frame too long\n");
327 ret++;
328 }
329
330 if (bd->stat & RX_BD_SF) {
331 debug("ETHOC: " "RX: frame too short\n");
332 ret++;
333 }
334
335 if (bd->stat & RX_BD_DN)
336 debug("ETHOC: " "RX: dribble nibble\n");
337
338 if (bd->stat & RX_BD_CRC) {
339 debug("ETHOC: " "RX: wrong CRC\n");
340 ret++;
341 }
342
343 if (bd->stat & RX_BD_OR) {
344 debug("ETHOC: " "RX: overrun\n");
345 ret++;
346 }
347
348 if (bd->stat & RX_BD_LC) {
349 debug("ETHOC: " "RX: late collision\n");
350 ret++;
351 }
352
353 return ret;
354}
355
356static int ethoc_rx(struct eth_device *dev, int limit)
357{
358 struct ethoc *priv = (struct ethoc *)dev->priv;
359 int count;
360
361 for (count = 0; count < limit; ++count) {
362 u32 entry;
363 struct ethoc_bd bd;
364
365 entry = priv->num_tx + (priv->cur_rx % priv->num_rx);
366 ethoc_read_bd(dev, entry, &bd);
367 if (bd.stat & RX_BD_EMPTY)
368 break;
369
370 debug("%s(): RX buffer %d, %x received\n",
371 __func__, priv->cur_rx, bd.stat);
372 if (ethoc_update_rx_stats(&bd) == 0) {
373 int size = bd.stat >> 16;
374 size -= 4; /* strip the CRC */
375 NetReceive((void *)bd.addr, size);
376 }
377
378 /* clear the buffer descriptor so it can be reused */
Stefan Kristiansson83ea1302011-11-04 02:38:06 +0000379 flush_dcache_range(bd.addr, bd.addr + PKTSIZE_ALIGN);
Thomas Chouf6569882010-04-15 22:32:38 +0800380 bd.stat &= ~RX_BD_STATS;
381 bd.stat |= RX_BD_EMPTY;
382 ethoc_write_bd(dev, entry, &bd);
383 priv->cur_rx++;
384 }
385
386 return count;
387}
388
389static int ethoc_update_tx_stats(struct ethoc_bd *bd)
390{
391 if (bd->stat & TX_BD_LC)
392 debug("ETHOC: " "TX: late collision\n");
393
394 if (bd->stat & TX_BD_RL)
395 debug("ETHOC: " "TX: retransmit limit\n");
396
397 if (bd->stat & TX_BD_UR)
398 debug("ETHOC: " "TX: underrun\n");
399
400 if (bd->stat & TX_BD_CS)
401 debug("ETHOC: " "TX: carrier sense lost\n");
402
403 return 0;
404}
405
406static void ethoc_tx(struct eth_device *dev)
407{
408 struct ethoc *priv = (struct ethoc *)dev->priv;
409 u32 entry = priv->dty_tx % priv->num_tx;
410 struct ethoc_bd bd;
411
412 ethoc_read_bd(dev, entry, &bd);
413 if ((bd.stat & TX_BD_READY) == 0)
414 (void)ethoc_update_tx_stats(&bd);
415}
416
Joe Hershberger10cbe3b2012-05-22 18:36:19 +0000417static int ethoc_send(struct eth_device *dev, void *packet, int length)
Thomas Chouf6569882010-04-15 22:32:38 +0800418{
419 struct ethoc *priv = (struct ethoc *)dev->priv;
420 struct ethoc_bd bd;
421 u32 entry;
422 u32 pending;
423 int tmo;
424
425 entry = priv->cur_tx % priv->num_tx;
426 ethoc_read_bd(dev, entry, &bd);
427 if (unlikely(length < ETHOC_ZLEN))
428 bd.stat |= TX_BD_PAD;
429 else
430 bd.stat &= ~TX_BD_PAD;
431 bd.addr = (u32)packet;
432
Stefan Kristiansson83ea1302011-11-04 02:38:06 +0000433 flush_dcache_range(bd.addr, bd.addr + length);
Thomas Chouf6569882010-04-15 22:32:38 +0800434 bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
435 bd.stat |= TX_BD_LEN(length);
436 ethoc_write_bd(dev, entry, &bd);
437
438 /* start transmit */
439 bd.stat |= TX_BD_READY;
440 ethoc_write_bd(dev, entry, &bd);
441
442 /* wait for transfer to succeed */
443 tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
444 while (1) {
445 pending = ethoc_read(dev, INT_SOURCE);
446 ethoc_ack_irq(dev, pending & ~INT_MASK_RX);
447 if (pending & INT_MASK_BUSY)
448 debug("%s(): packet dropped\n", __func__);
449
450 if (pending & INT_MASK_TX) {
451 ethoc_tx(dev);
452 break;
453 }
454 if (get_timer(0) >= tmo) {
455 debug("%s(): timed out\n", __func__);
456 return -1;
457 }
458 }
459
460 debug("%s(): packet sent\n", __func__);
461 return 0;
462}
463
464static void ethoc_halt(struct eth_device *dev)
465{
466 ethoc_disable_rx_and_tx(dev);
467}
468
469static int ethoc_recv(struct eth_device *dev)
470{
471 u32 pending;
472
473 pending = ethoc_read(dev, INT_SOURCE);
474 ethoc_ack_irq(dev, pending);
475 if (pending & INT_MASK_BUSY)
476 debug("%s(): packet dropped\n", __func__);
477 if (pending & INT_MASK_RX) {
478 debug("%s(): rx irq\n", __func__);
479 ethoc_rx(dev, PKTBUFSRX);
480 }
481
482 return 0;
483}
484
485int ethoc_initialize(u8 dev_num, int base_addr)
486{
487 struct ethoc *priv;
488 struct eth_device *dev;
489
490 priv = malloc(sizeof(*priv));
491 if (!priv)
492 return 0;
493 dev = malloc(sizeof(*dev));
494 if (!dev) {
495 free(priv);
496 return 0;
497 }
498
499 memset(dev, 0, sizeof(*dev));
500 dev->priv = priv;
501 dev->iobase = base_addr;
502 dev->init = ethoc_init;
503 dev->halt = ethoc_halt;
504 dev->send = ethoc_send;
505 dev->recv = ethoc_recv;
Thomas Chou3ac9d6c2010-04-27 20:20:27 +0800506 dev->write_hwaddr = ethoc_set_mac_address;
Thomas Chouf6569882010-04-15 22:32:38 +0800507 sprintf(dev->name, "%s-%hu", "ETHOC", dev_num);
508
509 eth_register(dev);
510 return 1;
511}