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Daniel Hellstromc2b7da52008-03-28 20:22:53 +01001/* Gaisler.com GRETH 10/100/1000 Ethernet MAC driver
2 *
3 * Driver use polling mode (no Interrupt)
4 *
5 * (C) Copyright 2007
6 * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Daniel Hellstromc2b7da52008-03-28 20:22:53 +01009 */
10
Daniel Hellstrom6644c192010-10-27 09:24:13 +020011/* #define DEBUG */
12
Daniel Hellstromc2b7da52008-03-28 20:22:53 +010013#include <common.h>
14#include <command.h>
15#include <net.h>
Ben Warren89973f82008-08-31 22:22:04 -070016#include <netdev.h>
Daniel Hellstromc2b7da52008-03-28 20:22:53 +010017#include <malloc.h>
18#include <asm/processor.h>
19#include <ambapp.h>
20#include <asm/leon.h>
21
Daniel Hellstromc2b7da52008-03-28 20:22:53 +010022#include "greth.h"
23
24/* Default to 3s timeout on autonegotiation */
25#ifndef GRETH_PHY_TIMEOUT_MS
26#define GRETH_PHY_TIMEOUT_MS 3000
27#endif
28
Daniel Hellstrome780d822010-10-22 11:26:49 +020029/* Default to PHY adrress 0 not not specified */
30#ifdef CONFIG_SYS_GRLIB_GRETH_PHYADDR
31#define GRETH_PHY_ADR_DEFAULT CONFIG_SYS_GRLIB_GRETH_PHYADDR
32#else
33#define GRETH_PHY_ADR_DEFAULT 0
34#endif
35
Daniel Hellstromc2b7da52008-03-28 20:22:53 +010036/* ByPass Cache when reading regs */
37#define GRETH_REGLOAD(addr) SPARC_NOCACHE_READ(addr)
38/* Write-through cache ==> no bypassing needed on writes */
Daniel Hellstrome3ce6862010-10-27 09:39:46 +020039#define GRETH_REGSAVE(addr,data) (*(volatile unsigned int *)(addr) = (data))
Daniel Hellstromc2b7da52008-03-28 20:22:53 +010040#define GRETH_REGORIN(addr,data) GRETH_REGSAVE(addr,GRETH_REGLOAD(addr)|data)
41#define GRETH_REGANDIN(addr,data) GRETH_REGSAVE(addr,GRETH_REGLOAD(addr)&data)
42
43#define GRETH_RXBD_CNT 4
44#define GRETH_TXBD_CNT 1
45
46#define GRETH_RXBUF_SIZE 1540
47#define GRETH_BUF_ALIGN 4
48#define GRETH_RXBUF_EFF_SIZE \
49 ( (GRETH_RXBUF_SIZE&~(GRETH_BUF_ALIGN-1))+GRETH_BUF_ALIGN )
50
51typedef struct {
52 greth_regs *regs;
53 int irq;
54 struct eth_device *dev;
55
56 /* Hardware info */
57 unsigned char phyaddr;
58 int gbit_mac;
59
60 /* Current operating Mode */
61 int gb; /* GigaBit */
62 int fd; /* Full Duplex */
63 int sp; /* 10/100Mbps speed (1=100,0=10) */
64 int auto_neg; /* Auto negotiate done */
65
66 unsigned char hwaddr[6]; /* MAC Address */
67
68 /* Descriptors */
69 greth_bd *rxbd_base, *rxbd_max;
70 greth_bd *txbd_base, *txbd_max;
71
72 greth_bd *rxbd_curr;
73
74 /* rx buffers in rx descriptors */
75 void *rxbuf_base; /* (GRETH_RXBUF_SIZE+ALIGNBYTES) * GRETH_RXBD_CNT */
76
77 /* unused for gbit_mac, temp buffer for sending packets with unligned
78 * start.
79 * Pointer to packet allocated with malloc.
80 */
81 void *txbuf;
82
83 struct {
84 /* rx status */
85 unsigned int rx_packets,
86 rx_crc_errors, rx_frame_errors, rx_length_errors, rx_errors;
87
88 /* tx stats */
89 unsigned int tx_packets,
90 tx_latecol_errors,
91 tx_underrun_errors, tx_limit_errors, tx_errors;
92 } stats;
93} greth_priv;
94
95/* Read MII register 'addr' from core 'regs' */
Daniel Hellstrome780d822010-10-22 11:26:49 +020096static int read_mii(int phyaddr, int regaddr, volatile greth_regs * regs)
Daniel Hellstromc2b7da52008-03-28 20:22:53 +010097{
98 while (GRETH_REGLOAD(&regs->mdio) & GRETH_MII_BUSY) {
99 }
100
Daniel Hellstrome780d822010-10-22 11:26:49 +0200101 GRETH_REGSAVE(&regs->mdio, ((phyaddr & 0x1F) << 11) | ((regaddr & 0x1F) << 6) | 2);
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100102
103 while (GRETH_REGLOAD(&regs->mdio) & GRETH_MII_BUSY) {
104 }
105
106 if (!(GRETH_REGLOAD(&regs->mdio) & GRETH_MII_NVALID)) {
107 return (GRETH_REGLOAD(&regs->mdio) >> 16) & 0xFFFF;
108 } else {
109 return -1;
110 }
111}
112
Daniel Hellstrome780d822010-10-22 11:26:49 +0200113static void write_mii(int phyaddr, int regaddr, int data, volatile greth_regs * regs)
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100114{
115 while (GRETH_REGLOAD(&regs->mdio) & GRETH_MII_BUSY) {
116 }
117
118 GRETH_REGSAVE(&regs->mdio,
Daniel Hellstrome780d822010-10-22 11:26:49 +0200119 ((data & 0xFFFF) << 16) | ((phyaddr & 0x1F) << 11) |
120 ((regaddr & 0x1F) << 6) | 1);
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100121
122 while (GRETH_REGLOAD(&regs->mdio) & GRETH_MII_BUSY) {
123 }
124
125}
126
127/* init/start hardware and allocate descriptor buffers for rx side
128 *
129 */
130int greth_init(struct eth_device *dev, bd_t * bis)
131{
132 int i;
133
134 greth_priv *greth = dev->priv;
135 greth_regs *regs = greth->regs;
Daniel Hellstrom6644c192010-10-27 09:24:13 +0200136
137 debug("greth_init\n");
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100138
Daniel Hellstrom533b67d2010-10-22 11:34:01 +0200139 /* Reset core */
140 GRETH_REGSAVE(&regs->control, (GRETH_RESET | (greth->gb << 8) |
141 (greth->sp << 7) | (greth->fd << 4)));
142
143 /* Wait for Reset to complete */
144 while ( GRETH_REGLOAD(&regs->control) & GRETH_RESET) ;
145
146 GRETH_REGSAVE(&regs->control,
147 ((greth->gb << 8) | (greth->sp << 7) | (greth->fd << 4)));
148
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100149 if (!greth->rxbd_base) {
150
151 /* allocate descriptors */
152 greth->rxbd_base = (greth_bd *)
153 memalign(0x1000, GRETH_RXBD_CNT * sizeof(greth_bd));
154 greth->txbd_base = (greth_bd *)
Daniel Hellstromed52d122010-10-22 11:36:39 +0200155 memalign(0x1000, GRETH_TXBD_CNT * sizeof(greth_bd));
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100156
157 /* allocate buffers to all descriptors */
158 greth->rxbuf_base =
159 malloc(GRETH_RXBUF_EFF_SIZE * GRETH_RXBD_CNT);
160 }
161
162 /* initate rx decriptors */
163 for (i = 0; i < GRETH_RXBD_CNT; i++) {
164 greth->rxbd_base[i].addr = (unsigned int)
165 greth->rxbuf_base + (GRETH_RXBUF_EFF_SIZE * i);
166 /* enable desciptor & set wrap bit if last descriptor */
167 if (i >= (GRETH_RXBD_CNT - 1)) {
168 greth->rxbd_base[i].stat = GRETH_BD_EN | GRETH_BD_WR;
169 } else {
170 greth->rxbd_base[i].stat = GRETH_BD_EN;
171 }
172 }
173
174 /* initiate indexes */
175 greth->rxbd_curr = greth->rxbd_base;
176 greth->rxbd_max = greth->rxbd_base + (GRETH_RXBD_CNT - 1);
177 greth->txbd_max = greth->txbd_base + (GRETH_TXBD_CNT - 1);
178 /*
179 * greth->txbd_base->addr = 0;
180 * greth->txbd_base->stat = GRETH_BD_WR;
181 */
182
183 /* initate tx decriptors */
184 for (i = 0; i < GRETH_TXBD_CNT; i++) {
185 greth->txbd_base[i].addr = 0;
186 /* enable desciptor & set wrap bit if last descriptor */
Daniel Hellstromed52d122010-10-22 11:36:39 +0200187 if (i >= (GRETH_TXBD_CNT - 1)) {
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100188 greth->txbd_base[i].stat = GRETH_BD_WR;
189 } else {
190 greth->txbd_base[i].stat = 0;
191 }
192 }
193
194 /**** SET HARDWARE REGS ****/
195
196 /* Set pointer to tx/rx descriptor areas */
197 GRETH_REGSAVE(&regs->rx_desc_p, (unsigned int)&greth->rxbd_base[0]);
198 GRETH_REGSAVE(&regs->tx_desc_p, (unsigned int)&greth->txbd_base[0]);
199
200 /* Enable Transmitter, GRETH will now scan descriptors for packets
201 * to transmitt */
Daniel Hellstrom6644c192010-10-27 09:24:13 +0200202 debug("greth_init: enabling receiver\n");
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100203 GRETH_REGORIN(&regs->control, GRETH_RXEN);
204
205 return 0;
206}
207
208/* Initiate PHY to a relevant speed
209 * return:
210 * - 0 = success
211 * - 1 = timeout/fail
212 */
213int greth_init_phy(greth_priv * dev, bd_t * bis)
214{
215 greth_regs *regs = dev->regs;
216 int tmp, tmp1, tmp2, i;
217 unsigned int start, timeout;
Daniel Hellstrome780d822010-10-22 11:26:49 +0200218 int phyaddr = GRETH_PHY_ADR_DEFAULT;
219
220#ifndef CONFIG_SYS_GRLIB_GRETH_PHYADDR
221 /* If BSP doesn't provide a hardcoded PHY address the driver will
222 * try to autodetect PHY address by stopping the search on the first
223 * PHY address which has REG0 implemented.
224 */
225 for (i=0; i<32; i++) {
226 tmp = read_mii(i, 0, regs);
227 if ( (tmp != 0) && (tmp != 0xffff) ) {
228 phyaddr = i;
229 break;
230 }
231 }
232#endif
233
234 /* Save PHY Address */
235 dev->phyaddr = phyaddr;
236
237 debug("GRETH PHY ADDRESS: %d\n", phyaddr);
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100238
239 /* X msecs to ticks */
240 timeout = usec2ticks(GRETH_PHY_TIMEOUT_MS * 1000);
241
242 /* Get system timer0 current value
243 * Total timeout is 5s
244 */
245 start = get_timer(0);
246
247 /* get phy control register default values */
248
Daniel Hellstrome780d822010-10-22 11:26:49 +0200249 while ((tmp = read_mii(phyaddr, 0, regs)) & 0x8000) {
250 if (get_timer(start) > timeout) {
251 debug("greth_init_phy: PHY read 1 failed\n");
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100252 return 1; /* Fail */
Daniel Hellstrome780d822010-10-22 11:26:49 +0200253 }
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100254 }
255
256 /* reset PHY and wait for completion */
Daniel Hellstrome780d822010-10-22 11:26:49 +0200257 write_mii(phyaddr, 0, 0x8000 | tmp, regs);
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100258
Daniel Hellstrome780d822010-10-22 11:26:49 +0200259 while (((tmp = read_mii(phyaddr, 0, regs))) & 0x8000) {
260 if (get_timer(start) > timeout) {
261 debug("greth_init_phy: PHY read 2 failed\n");
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100262 return 1; /* Fail */
Daniel Hellstrome780d822010-10-22 11:26:49 +0200263 }
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100264 }
265
266 /* Check if PHY is autoneg capable and then determine operating
267 * mode, otherwise force it to 10 Mbit halfduplex
268 */
269 dev->gb = 0;
270 dev->fd = 0;
271 dev->sp = 0;
272 dev->auto_neg = 0;
273 if (!((tmp >> 12) & 1)) {
Daniel Hellstrome780d822010-10-22 11:26:49 +0200274 write_mii(phyaddr, 0, 0, regs);
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100275 } else {
276 /* wait for auto negotiation to complete and then check operating mode */
277 dev->auto_neg = 1;
278 i = 0;
Daniel Hellstrome780d822010-10-22 11:26:49 +0200279 while (!(((tmp = read_mii(phyaddr, 1, regs)) >> 5) & 1)) {
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100280 if (get_timer(start) > timeout) {
281 printf("Auto negotiation timed out. "
282 "Selecting default config\n");
Daniel Hellstrome780d822010-10-22 11:26:49 +0200283 tmp = read_mii(phyaddr, 0, regs);
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100284 dev->gb = ((tmp >> 6) & 1)
285 && !((tmp >> 13) & 1);
286 dev->sp = !((tmp >> 6) & 1)
287 && ((tmp >> 13) & 1);
288 dev->fd = (tmp >> 8) & 1;
289 goto auto_neg_done;
290 }
291 }
292 if ((tmp >> 8) & 1) {
Daniel Hellstrome780d822010-10-22 11:26:49 +0200293 tmp1 = read_mii(phyaddr, 9, regs);
294 tmp2 = read_mii(phyaddr, 10, regs);
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100295 if ((tmp1 & GRETH_MII_EXTADV_1000FD) &&
296 (tmp2 & GRETH_MII_EXTPRT_1000FD)) {
297 dev->gb = 1;
298 dev->fd = 1;
299 }
300 if ((tmp1 & GRETH_MII_EXTADV_1000HD) &&
301 (tmp2 & GRETH_MII_EXTPRT_1000HD)) {
302 dev->gb = 1;
303 dev->fd = 0;
304 }
305 }
306 if ((dev->gb == 0) || ((dev->gb == 1) && (dev->gbit_mac == 0))) {
Daniel Hellstrome780d822010-10-22 11:26:49 +0200307 tmp1 = read_mii(phyaddr, 4, regs);
308 tmp2 = read_mii(phyaddr, 5, regs);
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100309 if ((tmp1 & GRETH_MII_100TXFD) &&
310 (tmp2 & GRETH_MII_100TXFD)) {
311 dev->sp = 1;
312 dev->fd = 1;
313 }
314 if ((tmp1 & GRETH_MII_100TXHD) &&
315 (tmp2 & GRETH_MII_100TXHD)) {
316 dev->sp = 1;
317 dev->fd = 0;
318 }
319 if ((tmp1 & GRETH_MII_10FD) && (tmp2 & GRETH_MII_10FD)) {
320 dev->fd = 1;
321 }
322 if ((dev->gb == 1) && (dev->gbit_mac == 0)) {
323 dev->gb = 0;
324 dev->fd = 0;
Daniel Hellstrome780d822010-10-22 11:26:49 +0200325 write_mii(phyaddr, 0, dev->sp << 13, regs);
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100326 }
327 }
328
329 }
330 auto_neg_done:
Daniel Hellstrom6644c192010-10-27 09:24:13 +0200331 debug("%s GRETH Ethermac at [0x%x] irq %d. Running \
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100332 %d Mbps %s duplex\n", dev->gbit_mac ? "10/100/1000" : "10/100", (unsigned int)(regs), (unsigned int)(dev->irq), dev->gb ? 1000 : (dev->sp ? 100 : 10), dev->fd ? "full" : "half");
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100333 /* Read out PHY info if extended registers are available */
334 if (tmp & 1) {
Daniel Hellstrome780d822010-10-22 11:26:49 +0200335 tmp1 = read_mii(phyaddr, 2, regs);
336 tmp2 = read_mii(phyaddr, 3, regs);
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100337 tmp1 = (tmp1 << 6) | ((tmp2 >> 10) & 0x3F);
338 tmp = tmp2 & 0xF;
339
340 tmp2 = (tmp2 >> 4) & 0x3F;
Daniel Hellstrom6644c192010-10-27 09:24:13 +0200341 debug("PHY: Vendor %x Device %x Revision %d\n", tmp1,
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100342 tmp2, tmp);
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100343 } else {
344 printf("PHY info not available\n");
345 }
346
347 /* set speed and duplex bits in control register */
348 GRETH_REGORIN(&regs->control,
349 (dev->gb << 8) | (dev->sp << 7) | (dev->fd << 4));
350
351 return 0;
352}
353
354void greth_halt(struct eth_device *dev)
355{
356 greth_priv *greth;
357 greth_regs *regs;
358 int i;
Daniel Hellstrom6644c192010-10-27 09:24:13 +0200359
360 debug("greth_halt\n");
361
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100362 if (!dev || !dev->priv)
363 return;
364
365 greth = dev->priv;
366 regs = greth->regs;
367
368 if (!regs)
369 return;
370
371 /* disable receiver/transmitter by clearing the enable bits */
372 GRETH_REGANDIN(&regs->control, ~(GRETH_RXEN | GRETH_TXEN));
373
374 /* reset rx/tx descriptors */
375 if (greth->rxbd_base) {
376 for (i = 0; i < GRETH_RXBD_CNT; i++) {
377 greth->rxbd_base[i].stat =
378 (i >= (GRETH_RXBD_CNT - 1)) ? GRETH_BD_WR : 0;
379 }
380 }
381
382 if (greth->txbd_base) {
383 for (i = 0; i < GRETH_TXBD_CNT; i++) {
384 greth->txbd_base[i].stat =
385 (i >= (GRETH_TXBD_CNT - 1)) ? GRETH_BD_WR : 0;
386 }
387 }
388}
389
Joe Hershberger10cbe3b2012-05-22 18:36:19 +0000390int greth_send(struct eth_device *dev, void *eth_data, int data_length)
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100391{
392 greth_priv *greth = dev->priv;
393 greth_regs *regs = greth->regs;
394 greth_bd *txbd;
395 void *txbuf;
396 unsigned int status;
Daniel Hellstrom6644c192010-10-27 09:24:13 +0200397
398 debug("greth_send\n");
399
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100400 /* send data, wait for data to be sent, then return */
401 if (((unsigned int)eth_data & (GRETH_BUF_ALIGN - 1))
402 && !greth->gbit_mac) {
403 /* data not aligned as needed by GRETH 10/100, solve this by allocating 4 byte aligned buffer
404 * and copy data to before giving it to GRETH.
405 */
406 if (!greth->txbuf) {
407 greth->txbuf = malloc(GRETH_RXBUF_SIZE);
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100408 }
409
410 txbuf = greth->txbuf;
411
412 /* copy data info buffer */
413 memcpy((char *)txbuf, (char *)eth_data, data_length);
414
415 /* keep buffer to next time */
416 } else {
417 txbuf = (void *)eth_data;
418 }
419 /* get descriptor to use, only 1 supported... hehe easy */
420 txbd = greth->txbd_base;
421
422 /* setup descriptor to wrap around to it self */
423 txbd->addr = (unsigned int)txbuf;
424 txbd->stat = GRETH_BD_EN | GRETH_BD_WR | data_length;
425
426 /* Remind Core which descriptor to use when sending */
427 GRETH_REGSAVE(&regs->tx_desc_p, (unsigned int)txbd);
428
429 /* initate send by enabling transmitter */
430 GRETH_REGORIN(&regs->control, GRETH_TXEN);
431
432 /* Wait for data to be sent */
433 while ((status = GRETH_REGLOAD(&txbd->stat)) & GRETH_BD_EN) {
434 ;
435 }
436
437 /* was the packet transmitted succesfully? */
438 if (status & GRETH_TXBD_ERR_AL) {
439 greth->stats.tx_limit_errors++;
440 }
441
442 if (status & GRETH_TXBD_ERR_UE) {
443 greth->stats.tx_underrun_errors++;
444 }
445
446 if (status & GRETH_TXBD_ERR_LC) {
447 greth->stats.tx_latecol_errors++;
448 }
449
450 if (status &
451 (GRETH_TXBD_ERR_LC | GRETH_TXBD_ERR_UE | GRETH_TXBD_ERR_AL)) {
452 /* any error */
453 greth->stats.tx_errors++;
454 return -1;
455 }
456
457 /* bump tx packet counter */
458 greth->stats.tx_packets++;
459
460 /* return succefully */
461 return 0;
462}
463
464int greth_recv(struct eth_device *dev)
465{
466 greth_priv *greth = dev->priv;
467 greth_regs *regs = greth->regs;
468 greth_bd *rxbd;
469 unsigned int status, len = 0, bad;
Marek Vasutfa2afe02012-07-27 08:04:32 +0000470 char *d;
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100471 int enable = 0;
472 int i;
Daniel Hellstrom6644c192010-10-27 09:24:13 +0200473
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100474 /* Receive One packet only, but clear as many error packets as there are
475 * available.
476 */
477 {
478 /* current receive descriptor */
479 rxbd = greth->rxbd_curr;
480
481 /* get status of next received packet */
482 status = GRETH_REGLOAD(&rxbd->stat);
483
484 bad = 0;
485
486 /* stop if no more packets received */
487 if (status & GRETH_BD_EN) {
488 goto done;
489 }
Daniel Hellstrom6644c192010-10-27 09:24:13 +0200490
Marek Vasutfa2afe02012-07-27 08:04:32 +0000491 debug("greth_recv: packet 0x%x, 0x%x, len: %d\n",
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100492 (unsigned int)rxbd, status, status & GRETH_BD_LEN);
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100493
494 /* Check status for errors.
495 */
496 if (status & GRETH_RXBD_ERR_FT) {
497 greth->stats.rx_length_errors++;
498 bad = 1;
499 }
500 if (status & (GRETH_RXBD_ERR_AE | GRETH_RXBD_ERR_OE)) {
501 greth->stats.rx_frame_errors++;
502 bad = 1;
503 }
504 if (status & GRETH_RXBD_ERR_CRC) {
505 greth->stats.rx_crc_errors++;
506 bad = 1;
507 }
508 if (bad) {
509 greth->stats.rx_errors++;
510 printf
511 ("greth_recv: Bad packet (%d, %d, %d, 0x%08x, %d)\n",
512 greth->stats.rx_length_errors,
513 greth->stats.rx_frame_errors,
514 greth->stats.rx_crc_errors, status,
515 greth->stats.rx_packets);
516 /* print all rx descriptors */
517 for (i = 0; i < GRETH_RXBD_CNT; i++) {
518 printf("[%d]: Stat=0x%lx, Addr=0x%lx\n", i,
519 GRETH_REGLOAD(&greth->rxbd_base[i].stat),
Daniel Hellstrome780d822010-10-22 11:26:49 +0200520 GRETH_REGLOAD(&greth->rxbd_base[i].addr));
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100521 }
522 } else {
523 /* Process the incoming packet. */
524 len = status & GRETH_BD_LEN;
525 d = (char *)rxbd->addr;
Daniel Hellstrom6644c192010-10-27 09:24:13 +0200526
527 debug
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100528 ("greth_recv: new packet, length: %d. data: %x %x %x %x %x %x %x %x\n",
529 len, d[0], d[1], d[2], d[3], d[4], d[5], d[6],
530 d[7]);
Daniel Hellstrom6644c192010-10-27 09:24:13 +0200531
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100532 /* flush all data cache to make sure we're not reading old packet data */
533 sparc_dcache_flush_all();
534
535 /* pass packet on to network subsystem */
536 NetReceive((void *)d, len);
537
538 /* bump stats counters */
539 greth->stats.rx_packets++;
540
541 /* bad is now 0 ==> will stop loop */
542 }
543
544 /* reenable descriptor to receive more packet with this descriptor, wrap around if needed */
545 rxbd->stat =
546 GRETH_BD_EN |
547 (((unsigned int)greth->rxbd_curr >=
548 (unsigned int)greth->rxbd_max) ? GRETH_BD_WR : 0);
549 enable = 1;
550
551 /* increase index */
552 greth->rxbd_curr =
553 ((unsigned int)greth->rxbd_curr >=
554 (unsigned int)greth->rxbd_max) ? greth->
555 rxbd_base : (greth->rxbd_curr + 1);
556
Daniel Hellstrome780d822010-10-22 11:26:49 +0200557 }
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100558
559 if (enable) {
560 GRETH_REGORIN(&regs->control, GRETH_RXEN);
561 }
562 done:
Mike Williams16263082011-07-22 04:01:30 +0000563 /* return positive length of packet or 0 if non received */
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100564 return len;
565}
566
567void greth_set_hwaddr(greth_priv * greth, unsigned char *mac)
568{
569 /* save new MAC address */
570 greth->dev->enetaddr[0] = greth->hwaddr[0] = mac[0];
571 greth->dev->enetaddr[1] = greth->hwaddr[1] = mac[1];
572 greth->dev->enetaddr[2] = greth->hwaddr[2] = mac[2];
573 greth->dev->enetaddr[3] = greth->hwaddr[3] = mac[3];
574 greth->dev->enetaddr[4] = greth->hwaddr[4] = mac[4];
575 greth->dev->enetaddr[5] = greth->hwaddr[5] = mac[5];
576 greth->regs->esa_msb = (mac[0] << 8) | mac[1];
577 greth->regs->esa_lsb =
578 (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5];
Daniel Hellstrom6644c192010-10-27 09:24:13 +0200579
580 debug("GRETH: New MAC address: %02x:%02x:%02x:%02x:%02x:%02x\n",
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100581 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100582}
583
584int greth_initialize(bd_t * bis)
585{
586 greth_priv *greth;
587 ambapp_apbdev apbdev;
588 struct eth_device *dev;
589 int i;
590 char *addr_str, *end;
591 unsigned char addr[6];
Daniel Hellstrom6644c192010-10-27 09:24:13 +0200592
593 debug("Scanning for GRETH\n");
594
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100595 /* Find Device & IRQ via AMBA Plug&Play information */
596 if (ambapp_apb_first(VENDOR_GAISLER, GAISLER_ETHMAC, &apbdev) != 1) {
597 return -1; /* GRETH not found */
598 }
599
600 greth = (greth_priv *) malloc(sizeof(greth_priv));
601 dev = (struct eth_device *)malloc(sizeof(struct eth_device));
602 memset(dev, 0, sizeof(struct eth_device));
603 memset(greth, 0, sizeof(greth_priv));
604
605 greth->regs = (greth_regs *) apbdev.address;
606 greth->irq = apbdev.irq;
Marek Vasutfa2afe02012-07-27 08:04:32 +0000607 debug("Found GRETH at %p, irq %d\n", greth->regs, greth->irq);
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100608 dev->priv = (void *)greth;
609 dev->iobase = (unsigned int)greth->regs;
610 dev->init = greth_init;
611 dev->halt = greth_halt;
612 dev->send = greth_send;
613 dev->recv = greth_recv;
614 greth->dev = dev;
615
616 /* Reset Core */
617 GRETH_REGSAVE(&greth->regs->control, GRETH_RESET);
618
619 /* Wait for core to finish reset cycle */
620 while (GRETH_REGLOAD(&greth->regs->control) & GRETH_RESET) ;
621
622 /* Get the phy address which assumed to have been set
623 correctly with the reset value in hardware */
624 greth->phyaddr = (GRETH_REGLOAD(&greth->regs->mdio) >> 11) & 0x1F;
625
626 /* Check if mac is gigabit capable */
627 greth->gbit_mac = (GRETH_REGLOAD(&greth->regs->control) >> 27) & 1;
628
629 /* Make descriptor string */
630 if (greth->gbit_mac) {
Daniel Hellstrom64394662010-10-21 15:08:11 +0200631 sprintf(dev->name, "GRETH_10/100/GB");
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100632 } else {
Daniel Hellstrom64394662010-10-21 15:08:11 +0200633 sprintf(dev->name, "GRETH_10/100");
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100634 }
635
636 /* initiate PHY, select speed/duplex depending on connected PHY */
637 if (greth_init_phy(greth, bis)) {
638 /* Failed to init PHY (timedout) */
Marek Vasutfa2afe02012-07-27 08:04:32 +0000639 debug("GRETH[%p]: Failed to init PHY\n", greth->regs);
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100640 return -1;
641 }
642
643 /* Register Device to EtherNet subsystem */
644 eth_register(dev);
645
646 /* Get MAC address */
647 if ((addr_str = getenv("ethaddr")) != NULL) {
648 for (i = 0; i < 6; i++) {
649 addr[i] =
650 addr_str ? simple_strtoul(addr_str, &end, 16) : 0;
651 if (addr_str) {
652 addr_str = (*end) ? end + 1 : end;
653 }
654 }
655 } else {
656 /* HW Address not found in environment, Set default HW address */
657 addr[0] = GRETH_HWADDR_0; /* MSB */
658 addr[1] = GRETH_HWADDR_1;
659 addr[2] = GRETH_HWADDR_2;
660 addr[3] = GRETH_HWADDR_3;
661 addr[4] = GRETH_HWADDR_4;
662 addr[5] = GRETH_HWADDR_5; /* LSB */
663 }
664
665 /* set and remember MAC address */
666 greth_set_hwaddr(greth, addr);
667
Marek Vasutfa2afe02012-07-27 08:04:32 +0000668 debug("GRETH[%p]: Initialized successfully\n", greth->regs);
Ben Warrenfc363ce2008-07-09 01:04:19 -0700669 return 0;
Daniel Hellstromc2b7da52008-03-28 20:22:53 +0100670}