blob: 1dec4e35e0a706d2410dbdc4c36439c13c8f0c9b [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Guennadi Liakhovetskib30de3c2009-02-07 01:18:07 +01002/*
3 * Copyright (C) 2009
4 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
5 *
Stefano Babicd8e0ca82011-08-21 10:45:44 +02006 * Copyright (C) 2011
7 * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
Guennadi Liakhovetskib30de3c2009-02-07 01:18:07 +01008 */
9#include <common.h>
Simon Glass441d0cf2014-10-01 19:57:26 -060010#include <errno.h>
11#include <dm.h>
12#include <malloc.h>
Stefano Babicc4ea1422010-07-06 17:05:06 +020013#include <asm/arch/imx-regs.h>
Stefano Babicd8e0ca82011-08-21 10:45:44 +020014#include <asm/gpio.h>
Stefano Babicc4ea1422010-07-06 17:05:06 +020015#include <asm/io.h>
Walter Lozanoa2845c92020-07-29 12:31:18 -030016#include <dt-structs.h>
17#include <mapmem.h>
Guennadi Liakhovetskib30de3c2009-02-07 01:18:07 +010018
Stefano Babicd8e0ca82011-08-21 10:45:44 +020019enum mxc_gpio_direction {
20 MXC_GPIO_DIRECTION_IN,
21 MXC_GPIO_DIRECTION_OUT,
22};
23
Simon Glass441d0cf2014-10-01 19:57:26 -060024#define GPIO_PER_BANK 32
25
26struct mxc_gpio_plat {
Walter Lozanoa2845c92020-07-29 12:31:18 -030027#if CONFIG_IS_ENABLED(OF_PLATDATA)
28 /* Put this first since driver model will copy the data here */
29 struct dtd_gpio_mxc dtplat;
30#endif
Peng Fan637a7692015-02-10 14:46:33 +080031 int bank_index;
Simon Glass441d0cf2014-10-01 19:57:26 -060032 struct gpio_regs *regs;
33};
34
35struct mxc_bank_info {
Simon Glass441d0cf2014-10-01 19:57:26 -060036 struct gpio_regs *regs;
37};
38
Simon Glassbcee8d62019-12-06 21:41:35 -070039#if !CONFIG_IS_ENABLED(DM_GPIO)
Lukasz Majewski01941372019-06-09 22:54:40 +020040#define GPIO_TO_PORT(n) ((n) / 32)
Stefano Babicd8e0ca82011-08-21 10:45:44 +020041
Guennadi Liakhovetskib30de3c2009-02-07 01:18:07 +010042/* GPIO port description */
43static unsigned long gpio_ports[] = {
Stefano Babicc4ea1422010-07-06 17:05:06 +020044 [0] = GPIO1_BASE_ADDR,
45 [1] = GPIO2_BASE_ADDR,
46 [2] = GPIO3_BASE_ADDR,
Tom Rini2568bd62022-11-19 18:45:27 -050047#if defined(CONFIG_MX51) || \
Adrian Alonso26dd3462015-08-11 11:19:51 -050048 defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
Peng Fancd357ad2018-11-20 10:19:25 +000049 defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
Giulio Benettiabd98e02020-01-10 15:47:03 +010050 defined(CONFIG_ARCH_IMX8) || defined(CONFIG_IMXRT1050)
Stefano Babicc4ea1422010-07-06 17:05:06 +020051 [3] = GPIO4_BASE_ADDR,
52#endif
Tom Rini2568bd62022-11-19 18:45:27 -050053#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
Peng Fancd357ad2018-11-20 10:19:25 +000054 defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
Giulio Benettiabd98e02020-01-10 15:47:03 +010055 defined(CONFIG_ARCH_IMX8) || defined(CONFIG_IMXRT1050)
Liu Hui-R6434301643ec2011-01-03 22:27:38 +000056 [4] = GPIO5_BASE_ADDR,
Giulio Benettiabd98e02020-01-10 15:47:03 +010057#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
58 defined(CONFIG_IMX8M) || defined(CONFIG_IMXRT1050))
Liu Hui-R6434301643ec2011-01-03 22:27:38 +000059 [5] = GPIO6_BASE_ADDR,
treme71c39d2012-08-25 05:30:33 +000060#endif
Peng Fanf2753b02015-07-20 19:28:31 +080061#endif
Peng Fan8b2a31f2018-10-18 14:28:27 +020062#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
63 defined(CONFIG_ARCH_IMX8)
Fabio Estevam290e7cf2018-01-03 12:33:05 -020064#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
Liu Hui-R6434301643ec2011-01-03 22:27:38 +000065 [6] = GPIO7_BASE_ADDR,
66#endif
Peng Fanf2753b02015-07-20 19:28:31 +080067#endif
Peng Fan8b2a31f2018-10-18 14:28:27 +020068#if defined(CONFIG_ARCH_IMX8)
69 [7] = GPIO8_BASE_ADDR,
70#endif
Guennadi Liakhovetskib30de3c2009-02-07 01:18:07 +010071};
72
Stefano Babicd8e0ca82011-08-21 10:45:44 +020073static int mxc_gpio_direction(unsigned int gpio,
74 enum mxc_gpio_direction direction)
Guennadi Liakhovetskib30de3c2009-02-07 01:18:07 +010075{
Vikram Narayananbe282552012-04-10 04:26:20 +000076 unsigned int port = GPIO_TO_PORT(gpio);
Stefano Babicc4ea1422010-07-06 17:05:06 +020077 struct gpio_regs *regs;
Guennadi Liakhovetskib30de3c2009-02-07 01:18:07 +010078 u32 l;
79
80 if (port >= ARRAY_SIZE(gpio_ports))
Joe Hershberger365d6072011-11-11 15:55:36 -060081 return -1;
Guennadi Liakhovetskib30de3c2009-02-07 01:18:07 +010082
83 gpio &= 0x1f;
84
Stefano Babicc4ea1422010-07-06 17:05:06 +020085 regs = (struct gpio_regs *)gpio_ports[port];
86
87 l = readl(&regs->gpio_dir);
88
Guennadi Liakhovetskib30de3c2009-02-07 01:18:07 +010089 switch (direction) {
Stefano Babicc4ea1422010-07-06 17:05:06 +020090 case MXC_GPIO_DIRECTION_OUT:
Guennadi Liakhovetskib30de3c2009-02-07 01:18:07 +010091 l |= 1 << gpio;
92 break;
Stefano Babicc4ea1422010-07-06 17:05:06 +020093 case MXC_GPIO_DIRECTION_IN:
Guennadi Liakhovetskib30de3c2009-02-07 01:18:07 +010094 l &= ~(1 << gpio);
95 }
Stefano Babicc4ea1422010-07-06 17:05:06 +020096 writel(l, &regs->gpio_dir);
Guennadi Liakhovetskib30de3c2009-02-07 01:18:07 +010097
98 return 0;
99}
100
Joe Hershberger365d6072011-11-11 15:55:36 -0600101int gpio_set_value(unsigned gpio, int value)
Guennadi Liakhovetskib30de3c2009-02-07 01:18:07 +0100102{
Vikram Narayananbe282552012-04-10 04:26:20 +0000103 unsigned int port = GPIO_TO_PORT(gpio);
Stefano Babicc4ea1422010-07-06 17:05:06 +0200104 struct gpio_regs *regs;
Guennadi Liakhovetskib30de3c2009-02-07 01:18:07 +0100105 u32 l;
106
107 if (port >= ARRAY_SIZE(gpio_ports))
Joe Hershberger365d6072011-11-11 15:55:36 -0600108 return -1;
Guennadi Liakhovetskib30de3c2009-02-07 01:18:07 +0100109
110 gpio &= 0x1f;
111
Stefano Babicc4ea1422010-07-06 17:05:06 +0200112 regs = (struct gpio_regs *)gpio_ports[port];
113
114 l = readl(&regs->gpio_dr);
Guennadi Liakhovetskib30de3c2009-02-07 01:18:07 +0100115 if (value)
116 l |= 1 << gpio;
117 else
118 l &= ~(1 << gpio);
Stefano Babicc4ea1422010-07-06 17:05:06 +0200119 writel(l, &regs->gpio_dr);
Joe Hershberger365d6072011-11-11 15:55:36 -0600120
121 return 0;
Guennadi Liakhovetskib30de3c2009-02-07 01:18:07 +0100122}
Stefano Babic7d27cd02010-04-13 12:07:00 +0200123
Joe Hershberger365d6072011-11-11 15:55:36 -0600124int gpio_get_value(unsigned gpio)
Stefano Babic7d27cd02010-04-13 12:07:00 +0200125{
Vikram Narayananbe282552012-04-10 04:26:20 +0000126 unsigned int port = GPIO_TO_PORT(gpio);
Stefano Babicc4ea1422010-07-06 17:05:06 +0200127 struct gpio_regs *regs;
Joe Hershberger365d6072011-11-11 15:55:36 -0600128 u32 val;
Stefano Babic7d27cd02010-04-13 12:07:00 +0200129
130 if (port >= ARRAY_SIZE(gpio_ports))
Joe Hershberger365d6072011-11-11 15:55:36 -0600131 return -1;
Stefano Babic7d27cd02010-04-13 12:07:00 +0200132
133 gpio &= 0x1f;
134
Stefano Babicc4ea1422010-07-06 17:05:06 +0200135 regs = (struct gpio_regs *)gpio_ports[port];
136
Benoît Thébaudeau5dafa452012-08-20 10:55:41 +0000137 val = (readl(&regs->gpio_psr) >> gpio) & 0x01;
Stefano Babic7d27cd02010-04-13 12:07:00 +0200138
Joe Hershberger365d6072011-11-11 15:55:36 -0600139 return val;
Stefano Babic7d27cd02010-04-13 12:07:00 +0200140}
Stefano Babicd8e0ca82011-08-21 10:45:44 +0200141
Joe Hershberger365d6072011-11-11 15:55:36 -0600142int gpio_request(unsigned gpio, const char *label)
Stefano Babicd8e0ca82011-08-21 10:45:44 +0200143{
Vikram Narayananbe282552012-04-10 04:26:20 +0000144 unsigned int port = GPIO_TO_PORT(gpio);
Stefano Babicd8e0ca82011-08-21 10:45:44 +0200145 if (port >= ARRAY_SIZE(gpio_ports))
Joe Hershberger365d6072011-11-11 15:55:36 -0600146 return -1;
Stefano Babicd8e0ca82011-08-21 10:45:44 +0200147 return 0;
148}
149
Joe Hershberger365d6072011-11-11 15:55:36 -0600150int gpio_free(unsigned gpio)
Stefano Babicd8e0ca82011-08-21 10:45:44 +0200151{
Joe Hershberger365d6072011-11-11 15:55:36 -0600152 return 0;
Stefano Babicd8e0ca82011-08-21 10:45:44 +0200153}
154
Joe Hershberger365d6072011-11-11 15:55:36 -0600155int gpio_direction_input(unsigned gpio)
Stefano Babicd8e0ca82011-08-21 10:45:44 +0200156{
Joe Hershberger365d6072011-11-11 15:55:36 -0600157 return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_IN);
Stefano Babicd8e0ca82011-08-21 10:45:44 +0200158}
159
Joe Hershberger365d6072011-11-11 15:55:36 -0600160int gpio_direction_output(unsigned gpio, int value)
Stefano Babicd8e0ca82011-08-21 10:45:44 +0200161{
Dirk Behme04c79cb2013-07-15 15:58:27 +0200162 int ret = gpio_set_value(gpio, value);
Stefano Babicd8e0ca82011-08-21 10:45:44 +0200163
164 if (ret < 0)
165 return ret;
166
Dirk Behme04c79cb2013-07-15 15:58:27 +0200167 return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_OUT);
Stefano Babicd8e0ca82011-08-21 10:45:44 +0200168}
Simon Glass441d0cf2014-10-01 19:57:26 -0600169#endif
170
Simon Glassbcee8d62019-12-06 21:41:35 -0700171#if CONFIG_IS_ENABLED(DM_GPIO)
Peng Fan99c0ae12015-02-10 14:46:34 +0800172#include <fdtdec.h>
Simon Glass441d0cf2014-10-01 19:57:26 -0600173static int mxc_gpio_is_output(struct gpio_regs *regs, int offset)
174{
175 u32 val;
176
177 val = readl(&regs->gpio_dir);
178
179 return val & (1 << offset) ? 1 : 0;
180}
181
182static void mxc_gpio_bank_direction(struct gpio_regs *regs, int offset,
183 enum mxc_gpio_direction direction)
184{
185 u32 l;
186
187 l = readl(&regs->gpio_dir);
188
189 switch (direction) {
190 case MXC_GPIO_DIRECTION_OUT:
191 l |= 1 << offset;
192 break;
193 case MXC_GPIO_DIRECTION_IN:
194 l &= ~(1 << offset);
195 }
196 writel(l, &regs->gpio_dir);
197}
198
199static void mxc_gpio_bank_set_value(struct gpio_regs *regs, int offset,
200 int value)
201{
202 u32 l;
203
204 l = readl(&regs->gpio_dr);
205 if (value)
206 l |= 1 << offset;
207 else
208 l &= ~(1 << offset);
209 writel(l, &regs->gpio_dr);
210}
211
212static int mxc_gpio_bank_get_value(struct gpio_regs *regs, int offset)
213{
214 return (readl(&regs->gpio_psr) >> offset) & 0x01;
215}
216
Simon Glass441d0cf2014-10-01 19:57:26 -0600217/* set GPIO pin 'gpio' as an input */
218static int mxc_gpio_direction_input(struct udevice *dev, unsigned offset)
219{
220 struct mxc_bank_info *bank = dev_get_priv(dev);
Simon Glass441d0cf2014-10-01 19:57:26 -0600221
222 /* Configure GPIO direction as input. */
223 mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_IN);
224
225 return 0;
226}
227
228/* set GPIO pin 'gpio' as an output, with polarity 'value' */
229static int mxc_gpio_direction_output(struct udevice *dev, unsigned offset,
230 int value)
231{
232 struct mxc_bank_info *bank = dev_get_priv(dev);
Simon Glass441d0cf2014-10-01 19:57:26 -0600233
234 /* Configure GPIO output value. */
235 mxc_gpio_bank_set_value(bank->regs, offset, value);
236
237 /* Configure GPIO direction as output. */
238 mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_OUT);
239
240 return 0;
241}
242
243/* read GPIO IN value of pin 'gpio' */
244static int mxc_gpio_get_value(struct udevice *dev, unsigned offset)
245{
246 struct mxc_bank_info *bank = dev_get_priv(dev);
Simon Glass441d0cf2014-10-01 19:57:26 -0600247
248 return mxc_gpio_bank_get_value(bank->regs, offset);
249}
250
251/* write GPIO OUT value to pin 'gpio' */
252static int mxc_gpio_set_value(struct udevice *dev, unsigned offset,
253 int value)
254{
255 struct mxc_bank_info *bank = dev_get_priv(dev);
Simon Glass441d0cf2014-10-01 19:57:26 -0600256
257 mxc_gpio_bank_set_value(bank->regs, offset, value);
258
259 return 0;
260}
261
Simon Glass441d0cf2014-10-01 19:57:26 -0600262static int mxc_gpio_get_function(struct udevice *dev, unsigned offset)
263{
264 struct mxc_bank_info *bank = dev_get_priv(dev);
265
Simon Glass441d0cf2014-10-01 19:57:26 -0600266 /* GPIOF_FUNC is not implemented yet */
267 if (mxc_gpio_is_output(bank->regs, offset))
268 return GPIOF_OUTPUT;
269 else
270 return GPIOF_INPUT;
271}
272
273static const struct dm_gpio_ops gpio_mxc_ops = {
Simon Glass441d0cf2014-10-01 19:57:26 -0600274 .direction_input = mxc_gpio_direction_input,
275 .direction_output = mxc_gpio_direction_output,
276 .get_value = mxc_gpio_get_value,
277 .set_value = mxc_gpio_set_value,
278 .get_function = mxc_gpio_get_function,
Simon Glass441d0cf2014-10-01 19:57:26 -0600279};
280
Simon Glass441d0cf2014-10-01 19:57:26 -0600281static int mxc_gpio_probe(struct udevice *dev)
282{
283 struct mxc_bank_info *bank = dev_get_priv(dev);
Simon Glassc69cda22020-12-03 16:55:20 -0700284 struct mxc_gpio_plat *plat = dev_get_plat(dev);
Simon Glasse564f052015-03-05 12:25:20 -0700285 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
Simon Glass441d0cf2014-10-01 19:57:26 -0600286 int banknum;
287 char name[18], *str;
288
Walter Lozanoa2845c92020-07-29 12:31:18 -0300289#if CONFIG_IS_ENABLED(OF_PLATDATA)
290 struct dtd_gpio_mxc *dtplat = &plat->dtplat;
291
292 plat->regs = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
293#endif
294
Peng Fan637a7692015-02-10 14:46:33 +0800295 banknum = plat->bank_index;
Ye Lie168eac2020-06-09 20:28:02 -0700296 if (IS_ENABLED(CONFIG_ARCH_IMX8))
297 sprintf(name, "GPIO%d_", banknum);
298 else
299 sprintf(name, "GPIO%d_", banknum + 1);
Simon Glass441d0cf2014-10-01 19:57:26 -0600300 str = strdup(name);
301 if (!str)
302 return -ENOMEM;
303 uc_priv->bank_name = str;
304 uc_priv->gpio_count = GPIO_PER_BANK;
305 bank->regs = plat->regs;
306
307 return 0;
308}
309
Simon Glassd1998a92020-12-03 16:55:21 -0700310static int mxc_gpio_of_to_plat(struct udevice *dev)
Peng Fan99c0ae12015-02-10 14:46:34 +0800311{
Simon Glassc69cda22020-12-03 16:55:20 -0700312 struct mxc_gpio_plat *plat = dev_get_plat(dev);
Walter Lozanoa2845c92020-07-29 12:31:18 -0300313 if (!CONFIG_IS_ENABLED(OF_PLATDATA)) {
314 fdt_addr_t addr;
Tom Rinif1c0b7c2020-08-04 11:11:02 -0400315 addr = dev_read_addr(dev);
Walter Lozanoa2845c92020-07-29 12:31:18 -0300316 if (addr == FDT_ADDR_T_NONE)
317 return -EINVAL;
Peng Fan99c0ae12015-02-10 14:46:34 +0800318
Walter Lozanoa2845c92020-07-29 12:31:18 -0300319 plat->regs = (struct gpio_regs *)addr;
320 }
Simon Glassfb0ea6a2020-12-16 21:20:24 -0700321 plat->bank_index = dev_seq(dev);
Peng Fan99c0ae12015-02-10 14:46:34 +0800322
323 return 0;
324}
325
Ye Li6103e572020-06-09 20:29:51 -0700326static int mxc_gpio_bind(struct udevice *dev)
327{
328 return 0;
329}
330
Peng Fan99c0ae12015-02-10 14:46:34 +0800331static const struct udevice_id mxc_gpio_ids[] = {
332 { .compatible = "fsl,imx35-gpio" },
333 { }
334};
335
Simon Glass441d0cf2014-10-01 19:57:26 -0600336U_BOOT_DRIVER(gpio_mxc) = {
337 .name = "gpio_mxc",
338 .id = UCLASS_GPIO,
339 .ops = &gpio_mxc_ops,
340 .probe = mxc_gpio_probe,
Simon Glassd1998a92020-12-03 16:55:21 -0700341 .of_to_plat = mxc_gpio_of_to_plat,
Simon Glasscaa4daa2020-12-03 16:55:18 -0700342 .plat_auto = sizeof(struct mxc_gpio_plat),
Simon Glass41575d82020-12-03 16:55:17 -0700343 .priv_auto = sizeof(struct mxc_bank_info),
Peng Fan99c0ae12015-02-10 14:46:34 +0800344 .of_match = mxc_gpio_ids,
345 .bind = mxc_gpio_bind,
346};
347
Simon Glassbdf8fd72020-12-28 20:34:57 -0700348DM_DRIVER_ALIAS(gpio_mxc, fsl_imx6q_gpio)
Walter Lozanoa2845c92020-07-29 12:31:18 -0300349
Masahiro Yamada0f925822015-08-12 07:31:55 +0900350#if !CONFIG_IS_ENABLED(OF_CONTROL)
Peng Fan99c0ae12015-02-10 14:46:34 +0800351static const struct mxc_gpio_plat mxc_plat[] = {
352 { 0, (struct gpio_regs *)GPIO1_BASE_ADDR },
353 { 1, (struct gpio_regs *)GPIO2_BASE_ADDR },
354 { 2, (struct gpio_regs *)GPIO3_BASE_ADDR },
Tom Rini2568bd62022-11-19 18:45:27 -0500355#if defined(CONFIG_MX51) || \
Peng Fan8953d862018-01-10 13:20:42 +0800356 defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
Peng Fancd357ad2018-11-20 10:19:25 +0000357 defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
Peng Fan99c0ae12015-02-10 14:46:34 +0800358 { 3, (struct gpio_regs *)GPIO4_BASE_ADDR },
359#endif
Tom Rini2568bd62022-11-19 18:45:27 -0500360#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
Peng Fancd357ad2018-11-20 10:19:25 +0000361 defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
Peng Fan99c0ae12015-02-10 14:46:34 +0800362 { 4, (struct gpio_regs *)GPIO5_BASE_ADDR },
Peng Fancd357ad2018-11-20 10:19:25 +0000363#ifndef CONFIG_IMX8M
Peng Fan99c0ae12015-02-10 14:46:34 +0800364 { 5, (struct gpio_regs *)GPIO6_BASE_ADDR },
365#endif
Peng Fan8953d862018-01-10 13:20:42 +0800366#endif
Peng Fan8b2a31f2018-10-18 14:28:27 +0200367#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_ARCH_IMX8)
Peng Fan99c0ae12015-02-10 14:46:34 +0800368 { 6, (struct gpio_regs *)GPIO7_BASE_ADDR },
369#endif
Peng Fan8b2a31f2018-10-18 14:28:27 +0200370#if defined(CONFIG_ARCH_IMX8)
371 { 7, (struct gpio_regs *)GPIO8_BASE_ADDR },
372#endif
Simon Glass441d0cf2014-10-01 19:57:26 -0600373};
374
Simon Glass20e442a2020-12-28 20:34:54 -0700375U_BOOT_DRVINFOS(mxc_gpios) = {
Simon Glass441d0cf2014-10-01 19:57:26 -0600376 { "gpio_mxc", &mxc_plat[0] },
377 { "gpio_mxc", &mxc_plat[1] },
378 { "gpio_mxc", &mxc_plat[2] },
Tom Rini2568bd62022-11-19 18:45:27 -0500379#if defined(CONFIG_MX51) || \
Peng Fan8953d862018-01-10 13:20:42 +0800380 defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
Peng Fancd357ad2018-11-20 10:19:25 +0000381 defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
Simon Glass441d0cf2014-10-01 19:57:26 -0600382 { "gpio_mxc", &mxc_plat[3] },
383#endif
Tom Rini2568bd62022-11-19 18:45:27 -0500384#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
Peng Fancd357ad2018-11-20 10:19:25 +0000385 defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
Simon Glass441d0cf2014-10-01 19:57:26 -0600386 { "gpio_mxc", &mxc_plat[4] },
Peng Fancd357ad2018-11-20 10:19:25 +0000387#ifndef CONFIG_IMX8M
Simon Glass441d0cf2014-10-01 19:57:26 -0600388 { "gpio_mxc", &mxc_plat[5] },
389#endif
Peng Fan8953d862018-01-10 13:20:42 +0800390#endif
Peng Fan8b2a31f2018-10-18 14:28:27 +0200391#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_ARCH_IMX8)
Simon Glass441d0cf2014-10-01 19:57:26 -0600392 { "gpio_mxc", &mxc_plat[6] },
393#endif
Peng Fan8b2a31f2018-10-18 14:28:27 +0200394#if defined(CONFIG_ARCH_IMX8)
395 { "gpio_mxc", &mxc_plat[7] },
396#endif
Simon Glass441d0cf2014-10-01 19:57:26 -0600397};
398#endif
Peng Fan99c0ae12015-02-10 14:46:34 +0800399#endif