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Stefan Roeseb79316f2005-08-15 12:31:23 +02001#ifndef __KAREF_H__
2#define __KAREF_H__
3/*
4 * (C) Copyright 2005
5 * Sandburst Corporation
6 * Travis B. Sawyer
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27/* Ka Reference Design OFEM FPGA Registers & definitions */
28#include "hal_ka_sc_auto.h"
29#include "hal_ka_of_auto.h"
30
31typedef struct karef_board_id_s {
32 const char name[40];
33} KAREF_BOARD_ID_ST, *KAREF_BOARD_ID_PST;
34
35/* SCAN FPGA */
36typedef struct karef_fpga_regs_s
37{
38 volatile unsigned long revision_ul; /* Read Only */
39 volatile unsigned long reset_ul; /* Read/Write */
40 volatile unsigned long interrupt_ul; /* Read Only */
41 volatile unsigned long mask_ul; /* Read/Write */
42 volatile unsigned long scratch_ul; /* Read/Write */
43 volatile unsigned long scrmask_ul; /* Read/Write */
44 volatile unsigned long status_ul; /* Read Only */
45 volatile unsigned long control_ul; /* Read/Write */
46 volatile unsigned long boardinfo_ul; /* Read Only */
47 volatile unsigned long scan_from0_ul; /* Read Only */
48 volatile unsigned long scan_from1_ul; /* Read Only */
49 volatile unsigned long scan_to0_ul; /* Read/Write */
50 volatile unsigned long scan_to1_ul; /* Read/Write */
51 volatile unsigned long scan_control_ul; /* Read/Write */
52 volatile unsigned long pll_control_ul; /* Read/Write */
53 volatile unsigned long core_clock_cnt_ul; /* Read/Write */
54 volatile unsigned long dr_clock_cnt_ul; /* Read/Write */
55 volatile unsigned long spi_clock_cnt_ul; /* Read/Write */
56 volatile unsigned long brdout_data_ul; /* Read/Write */
57 volatile unsigned long brdout_enable_ul; /* Read/Write */
58 volatile unsigned long brdin_data_ul; /* Read Only */
59 volatile unsigned long misc_ul; /* Read/Write */
Wolfgang Denk77ddac92005-10-13 16:45:02 +020060} __attribute__((packed)) KAREF_FPGA_REGS_ST , * KAREF_FPGA_REGS_PST;
Stefan Roeseb79316f2005-08-15 12:31:23 +020061
62/* OFEM FPGA */
63typedef struct ofem_fpga_regs_s
64{
65 volatile unsigned long revision_ul; /* Read Only */
66 volatile unsigned long reset_ul; /* Read/Write */
67 volatile unsigned long interrupt_ul; /* Read Only */
68 volatile unsigned long mask_ul; /* Read/Write */
69 volatile unsigned long scratch_ul; /* Read/Write */
70 volatile unsigned long scrmask_ul; /* Read/Write */
71 volatile unsigned long control_ul; /* Read/Write */
72 volatile unsigned long mac_flow_ctrl_ul; /* Read/Write */
Wolfgang Denk77ddac92005-10-13 16:45:02 +020073} __attribute__((packed)) OFEM_FPGA_REGS_ST , * OFEM_FPGA_REGS_PST;
Stefan Roeseb79316f2005-08-15 12:31:23 +020074
75
76#endif /* __KAREF_H__ */