blob: bd10ddaed12aa2693c1447d4d714c1da74abfd88 [file] [log] [blame]
wdenk03f5c552004-10-10 21:21:55 +00001/*
Kumar Gala7c57f3e2011-01-11 00:52:35 -06002 * Copyright 2004, 2011 Freescale Semiconductor.
wdenk03f5c552004-10-10 21:21:55 +00003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * mpc8541cds board configuration file
25 *
26 * Please refer to doc/README.mpc85xxcds for more info.
27 *
28 */
wdenk03f5c552004-10-10 21:21:55 +000029#ifndef __CONFIG_H
30#define __CONFIG_H
31
32/* High Level Configuration Options */
33#define CONFIG_BOOKE 1 /* BOOKE */
34#define CONFIG_E500 1 /* BOOKE e500 family */
35#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050036#define CONFIG_CPM2 1 /* has CPM2 */
wdenk03f5c552004-10-10 21:21:55 +000037#define CONFIG_MPC8541 1 /* MPC8541 specific */
38#define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */
39
Wolfgang Denk2ae18242010-10-06 09:05:45 +020040#define CONFIG_SYS_TEXT_BASE 0xfff80000
41
wdenk03f5c552004-10-10 21:21:55 +000042#define CONFIG_PCI
Kumar Gala0151cba2008-10-21 11:33:58 -050043#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020044#define CONFIG_TSEC_ENET /* tsec ethernet support */
wdenk03f5c552004-10-10 21:21:55 +000045#define CONFIG_ENV_OVERWRITE
Jon Loeligerd9b94f22005-07-25 14:05:07 -050046
Kumar Gala2cfaa1a2008-01-16 01:45:10 -060047#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
wdenk03f5c552004-10-10 21:21:55 +000048
Jon Loeliger25eedb22008-03-19 15:02:07 -050049#define CONFIG_FSL_VIA
Jon Loeliger25eedb22008-03-19 15:02:07 -050050
wdenk03f5c552004-10-10 21:21:55 +000051#ifndef __ASSEMBLY__
52extern unsigned long get_clock_freq(void);
53#endif
54#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
55
56/*
57 * These can be toggled for performance analysis, otherwise use default.
58 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020059#define CONFIG_L2_CACHE /* toggle L2 cache */
wdenk03f5c552004-10-10 21:21:55 +000060#define CONFIG_BTB /* toggle branch predition */
wdenk03f5c552004-10-10 21:21:55 +000061
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020062#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
63#define CONFIG_SYS_MEMTEST_END 0x00400000
wdenk03f5c552004-10-10 21:21:55 +000064
Timur Tabie46fedf2011-08-04 18:03:41 -050065#define CONFIG_SYS_CCSRBAR 0xe0000000
66#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
wdenk03f5c552004-10-10 21:21:55 +000067
Jon Loeligeraa11d852008-03-17 15:48:18 -050068/* DDR Setup */
69#define CONFIG_FSL_DDR1
70#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
71#define CONFIG_DDR_SPD
72#undef CONFIG_FSL_DDR_INTERACTIVE
73
74#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
75
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
77#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
wdenk03f5c552004-10-10 21:21:55 +000078
Jon Loeligeraa11d852008-03-17 15:48:18 -050079#define CONFIG_NUM_DDR_CONTROLLERS 1
80#define CONFIG_DIMM_SLOTS_PER_CTLR 1
81#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
82
83/* I2C addresses of SPD EEPROMs */
84#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
wdenk03f5c552004-10-10 21:21:55 +000085
86/*
87 * Make sure required options are set
88 */
89#ifndef CONFIG_SPD_EEPROM
90#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
91#endif
92
Jon Loeliger7202d432005-07-25 11:13:26 -050093#undef CONFIG_CLOCKS_IN_MHZ
94
wdenk03f5c552004-10-10 21:21:55 +000095/*
Jon Loeliger7202d432005-07-25 11:13:26 -050096 * Local Bus Definitions
wdenk03f5c552004-10-10 21:21:55 +000097 */
Jon Loeliger7202d432005-07-25 11:13:26 -050098
99/*
100 * FLASH on the Local Bus
101 * Two banks, 8M each, using the CFI driver.
102 * Boot from BR0/OR0 bank at 0xff00_0000
103 * Alternate BR1/OR1 bank at 0xff80_0000
104 *
105 * BR0, BR1:
106 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
107 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
108 * Port Size = 16 bits = BRx[19:20] = 10
109 * Use GPCM = BRx[24:26] = 000
110 * Valid = BRx[31] = 1
111 *
112 * 0 4 8 12 16 20 24 28
113 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
114 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
115 *
116 * OR0, OR1:
117 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
118 * Reserved ORx[17:18] = 11, confusion here?
119 * CSNT = ORx[20] = 1
120 * ACS = half cycle delay = ORx[21:22] = 11
121 * SCY = 6 = ORx[24:27] = 0110
122 * TRLX = use relaxed timing = ORx[29] = 1
123 * EAD = use external address latch delay = OR[31] = 1
124 *
125 * 0 4 8 12 16 20 24 28
126 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
127 */
128
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */
wdenk03f5c552004-10-10 21:21:55 +0000130
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_BR0_PRELIM 0xff801001
132#define CONFIG_SYS_BR1_PRELIM 0xff001001
wdenk03f5c552004-10-10 21:21:55 +0000133
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_OR0_PRELIM 0xff806e65
135#define CONFIG_SYS_OR1_PRELIM 0xff806e65
wdenk03f5c552004-10-10 21:21:55 +0000136
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE}
138#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
139#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
140#undef CONFIG_SYS_FLASH_CHECKSUM
141#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
142#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
wdenk03f5c552004-10-10 21:21:55 +0000143
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200144#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
wdenk03f5c552004-10-10 21:21:55 +0000145
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200146#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_FLASH_CFI
148#define CONFIG_SYS_FLASH_EMPTY_INFO
wdenk03f5c552004-10-10 21:21:55 +0000149
wdenk03f5c552004-10-10 21:21:55 +0000150
151/*
Jon Loeliger7202d432005-07-25 11:13:26 -0500152 * SDRAM on the Local Bus
wdenk03f5c552004-10-10 21:21:55 +0000153 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
155#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
wdenk03f5c552004-10-10 21:21:55 +0000156
157/*
158 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
wdenk03f5c552004-10-10 21:21:55 +0000160 *
161 * For BR2, need:
162 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
163 * port-size = 32-bits = BR2[19:20] = 11
164 * no parity checking = BR2[21:22] = 00
165 * SDRAM for MSEL = BR2[24:26] = 011
166 * Valid = BR[31] = 1
167 *
168 * 0 4 8 12 16 20 24 28
169 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
170 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
wdenk03f5c552004-10-10 21:21:55 +0000172 * FIXME: the top 17 bits of BR2.
173 */
174
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_BR2_PRELIM 0xf0001861
wdenk03f5c552004-10-10 21:21:55 +0000176
177/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
wdenk03f5c552004-10-10 21:21:55 +0000179 *
180 * For OR2, need:
181 * 64MB mask for AM, OR2[0:7] = 1111 1100
182 * XAM, OR2[17:18] = 11
183 * 9 columns OR2[19-21] = 010
184 * 13 rows OR2[23-25] = 100
185 * EAD set for extra time OR[31] = 1
186 *
187 * 0 4 8 12 16 20 24 28
188 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
189 */
190
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_OR2_PRELIM 0xfc006901
wdenk03f5c552004-10-10 21:21:55 +0000192
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
194#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
195#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
196#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
wdenk03f5c552004-10-10 21:21:55 +0000197
198/*
wdenk03f5c552004-10-10 21:21:55 +0000199 * Common settings for all Local Bus SDRAM commands.
200 * At run time, either BSMA1516 (for CPU 1.1)
201 * or BSMA1617 (for CPU 1.0) (old)
202 * is OR'ed in too.
203 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500204#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
205 | LSDMR_PRETOACT7 \
206 | LSDMR_ACTTORW7 \
207 | LSDMR_BL8 \
208 | LSDMR_WRC4 \
209 | LSDMR_CL3 \
210 | LSDMR_RFEN \
wdenk03f5c552004-10-10 21:21:55 +0000211 )
212
213/*
214 * The CADMUS registers are connected to CS3 on CDS.
215 * The new memory map places CADMUS at 0xf8000000.
216 *
217 * For BR3, need:
218 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
219 * port-size = 8-bits = BR[19:20] = 01
220 * no parity checking = BR[21:22] = 00
221 * GPMC for MSEL = BR[24:26] = 000
222 * Valid = BR[31] = 1
223 *
224 * 0 4 8 12 16 20 24 28
225 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
226 *
227 * For OR3, need:
228 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
229 * disable buffer ctrl OR[19] = 0
230 * CSNT OR[20] = 1
231 * ACS OR[21:22] = 11
232 * XACS OR[23] = 1
233 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
234 * SETA OR[28] = 0
235 * TRLX OR[29] = 1
236 * EHTR OR[30] = 1
237 * EAD extra time OR[31] = 1
238 *
239 * 0 4 8 12 16 20 24 28
240 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
241 */
242
Jon Loeliger25eedb22008-03-19 15:02:07 -0500243#define CONFIG_FSL_CADMUS
244
wdenk03f5c552004-10-10 21:21:55 +0000245#define CADMUS_BASE_ADDR 0xf8000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_BR3_PRELIM 0xf8000801
247#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
wdenk03f5c552004-10-10 21:21:55 +0000248
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_INIT_RAM_LOCK 1
250#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200251#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
wdenk03f5c552004-10-10 21:21:55 +0000252
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200253#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk03f5c552004-10-10 21:21:55 +0000255
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
257#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
wdenk03f5c552004-10-10 21:21:55 +0000258
259/* Serial Port */
260#define CONFIG_CONS_INDEX 2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_NS16550
262#define CONFIG_SYS_NS16550_SERIAL
263#define CONFIG_SYS_NS16550_REG_SIZE 1
264#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
wdenk03f5c552004-10-10 21:21:55 +0000265
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk03f5c552004-10-10 21:21:55 +0000267 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
268
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
270#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
wdenk03f5c552004-10-10 21:21:55 +0000271
272/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_HUSH_PARSER
274#ifdef CONFIG_SYS_HUSH_PARSER
275#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenk03f5c552004-10-10 21:21:55 +0000276#endif
277
Matthew McClintock0e163872006-06-28 10:43:36 -0500278/* pass open firmware flat tree */
Kumar Galab90d2542007-11-29 00:11:44 -0600279#define CONFIG_OF_LIBFDT 1
280#define CONFIG_OF_BOARD_SETUP 1
281#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Matthew McClintock0e163872006-06-28 10:43:36 -0500282
Jon Loeliger20476722006-10-20 15:50:15 -0500283/*
284 * I2C
285 */
286#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
287#define CONFIG_HARD_I2C /* I2C with hardware support*/
wdenk03f5c552004-10-10 21:21:55 +0000288#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
290#define CONFIG_SYS_I2C_SLAVE 0x7F
291#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
292#define CONFIG_SYS_I2C_OFFSET 0x3000
wdenk03f5c552004-10-10 21:21:55 +0000293
Timur Tabie8d18542008-07-18 16:52:23 +0200294/* EEPROM */
295#define CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#define CONFIG_SYS_I2C_EEPROM_CCID
297#define CONFIG_SYS_ID_EEPROM
298#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
299#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
Timur Tabie8d18542008-07-18 16:52:23 +0200300
wdenk03f5c552004-10-10 21:21:55 +0000301/*
302 * General PCI
Sergei Shtylyov362dd832006-12-27 22:07:15 +0300303 * Memory space is mapped 1-1, but I/O space must start from 0.
wdenk03f5c552004-10-10 21:21:55 +0000304 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600305#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala10795f42008-12-02 16:08:36 -0600306#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600307#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600309#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600310#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
312#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
wdenk03f5c552004-10-10 21:21:55 +0000313
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600314#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
Kumar Gala10795f42008-12-02 16:08:36 -0600315#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600316#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600318#define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600319#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
321#define CONFIG_SYS_PCI2_IO_SIZE 0x100000 /* 1M */
wdenk03f5c552004-10-10 21:21:55 +0000322
Randy Vinson7f3f2bd2007-02-27 19:42:22 -0700323#ifdef CONFIG_LEGACY
324#define BRIDGE_ID 17
325#define VIA_ID 2
326#else
327#define BRIDGE_ID 28
328#define VIA_ID 4
329#endif
wdenk03f5c552004-10-10 21:21:55 +0000330
331#if defined(CONFIG_PCI)
332
Matthew McClintockbf1dfff2006-06-28 10:46:13 -0500333#define CONFIG_MPC85XX_PCI2
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200334#define CONFIG_PCI_PNP /* do pci plug-and-play */
wdenk03f5c552004-10-10 21:21:55 +0000335
336#undef CONFIG_EEPRO100
337#undef CONFIG_TULIP
338
wdenk03f5c552004-10-10 21:21:55 +0000339#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
wdenk03f5c552004-10-10 21:21:55 +0000341
342#endif /* CONFIG_PCI */
343
344
345#if defined(CONFIG_TSEC_ENET)
346
wdenk03f5c552004-10-10 21:21:55 +0000347#define CONFIG_MII 1 /* MII PHY management */
Kim Phillips255a35772007-05-16 16:52:19 -0500348#define CONFIG_TSEC1 1
349#define CONFIG_TSEC1_NAME "TSEC0"
350#define CONFIG_TSEC2 1
351#define CONFIG_TSEC2_NAME "TSEC1"
wdenk03f5c552004-10-10 21:21:55 +0000352#define TSEC1_PHY_ADDR 0
353#define TSEC2_PHY_ADDR 1
wdenk03f5c552004-10-10 21:21:55 +0000354#define TSEC1_PHYIDX 0
355#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500356#define TSEC1_FLAGS TSEC_GIGABIT
357#define TSEC2_FLAGS TSEC_GIGABIT
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500358
359/* Options are: TSEC[0-1] */
360#define CONFIG_ETHPRIME "TSEC0"
wdenk03f5c552004-10-10 21:21:55 +0000361
362#endif /* CONFIG_TSEC_ENET */
363
wdenk03f5c552004-10-10 21:21:55 +0000364/*
365 * Environment
366 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200367#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200368#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200369#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
370#define CONFIG_ENV_SIZE 0x2000
wdenk03f5c552004-10-10 21:21:55 +0000371
372#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200373#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk03f5c552004-10-10 21:21:55 +0000374
Jon Loeliger2835e512007-06-13 13:22:08 -0500375/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500376 * BOOTP options
377 */
378#define CONFIG_BOOTP_BOOTFILESIZE
379#define CONFIG_BOOTP_BOOTPATH
380#define CONFIG_BOOTP_GATEWAY
381#define CONFIG_BOOTP_HOSTNAME
382
383
384/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500385 * Command line configuration.
386 */
387#include <config_cmd_default.h>
388
389#define CONFIG_CMD_PING
390#define CONFIG_CMD_I2C
391#define CONFIG_CMD_MII
Kumar Gala82ac8c92007-12-07 12:04:30 -0600392#define CONFIG_CMD_ELF
Kumar Gala1c9aa762008-09-22 23:40:42 -0500393#define CONFIG_CMD_IRQ
394#define CONFIG_CMD_SETEXPR
Becky Bruce199e2622010-06-17 11:37:25 -0500395#define CONFIG_CMD_REGINFO
Jon Loeliger2835e512007-06-13 13:22:08 -0500396
wdenk03f5c552004-10-10 21:21:55 +0000397#if defined(CONFIG_PCI)
Jon Loeliger2835e512007-06-13 13:22:08 -0500398 #define CONFIG_CMD_PCI
wdenk03f5c552004-10-10 21:21:55 +0000399#endif
Jon Loeliger2835e512007-06-13 13:22:08 -0500400
wdenk03f5c552004-10-10 21:21:55 +0000401
402#undef CONFIG_WATCHDOG /* watchdog disabled */
403
404/*
405 * Miscellaneous configurable options
406 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kim Phillips5be58f52010-07-14 19:47:18 -0500408#define CONFIG_CMDLINE_EDITING /* Command-line editing */
409#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200410#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
411#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger2835e512007-06-13 13:22:08 -0500412#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200413#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk03f5c552004-10-10 21:21:55 +0000414#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200415#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk03f5c552004-10-10 21:21:55 +0000416#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200417#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
418#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
419#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
420#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
wdenk03f5c552004-10-10 21:21:55 +0000421
422/*
423 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500424 * have to be in the first 64 MB of memory, since this is
wdenk03f5c552004-10-10 21:21:55 +0000425 * the maximum mapped by the Linux kernel during initialization.
426 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500427#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
428#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
wdenk03f5c552004-10-10 21:21:55 +0000429
Jon Loeliger2835e512007-06-13 13:22:08 -0500430#if defined(CONFIG_CMD_KGDB)
wdenk03f5c552004-10-10 21:21:55 +0000431#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
432#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
433#endif
434
wdenk03f5c552004-10-10 21:21:55 +0000435/*
436 * Environment Configuration
437 */
438
439/* The mac addresses for all ethernet interface */
440#if defined(CONFIG_TSEC_ENET)
Andy Fleming10327dc2007-08-16 16:35:02 -0500441#define CONFIG_HAS_ETH0
wdenk03f5c552004-10-10 21:21:55 +0000442#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
wdenke2ffd592004-12-31 09:32:47 +0000443#define CONFIG_HAS_ETH1
wdenk03f5c552004-10-10 21:21:55 +0000444#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
wdenke2ffd592004-12-31 09:32:47 +0000445#define CONFIG_HAS_ETH2
wdenk03f5c552004-10-10 21:21:55 +0000446#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
447#endif
448
449#define CONFIG_IPADDR 192.168.1.253
450
451#define CONFIG_HOSTNAME unknown
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000452#define CONFIG_ROOTPATH "/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000453#define CONFIG_BOOTFILE "your.uImage"
wdenk03f5c552004-10-10 21:21:55 +0000454
455#define CONFIG_SERVERIP 192.168.1.1
456#define CONFIG_GATEWAYIP 192.168.1.1
457#define CONFIG_NETMASK 255.255.255.0
458
459#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
460
461#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
462#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
463
464#define CONFIG_BAUDRATE 115200
465
466#define CONFIG_EXTRA_ENV_SETTINGS \
467 "netdev=eth0\0" \
468 "consoledev=ttyS1\0" \
Andy Fleming8272dc22006-09-13 10:33:35 -0500469 "ramdiskaddr=600000\0" \
470 "ramdiskfile=your.ramdisk.u-boot\0" \
471 "fdtaddr=400000\0" \
472 "fdtfile=your.fdt.dtb\0"
wdenk03f5c552004-10-10 21:21:55 +0000473
474#define CONFIG_NFSBOOTCOMMAND \
475 "setenv bootargs root=/dev/nfs rw " \
476 "nfsroot=$serverip:$rootpath " \
477 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
478 "console=$consoledev,$baudrate $othbootargs;" \
479 "tftp $loadaddr $bootfile;" \
Andy Fleming8272dc22006-09-13 10:33:35 -0500480 "tftp $fdtaddr $fdtfile;" \
481 "bootm $loadaddr - $fdtaddr"
wdenk03f5c552004-10-10 21:21:55 +0000482
483#define CONFIG_RAMBOOTCOMMAND \
484 "setenv bootargs root=/dev/ram rw " \
485 "console=$consoledev,$baudrate $othbootargs;" \
486 "tftp $ramdiskaddr $ramdiskfile;" \
487 "tftp $loadaddr $bootfile;" \
488 "bootm $loadaddr $ramdiskaddr"
489
490#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
491
wdenk03f5c552004-10-10 21:21:55 +0000492#endif /* __CONFIG_H */