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Magnus Lilja8449f282009-07-01 01:07:55 +02001/*
2 *
3 * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
4 *
5 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26
27#include <common.h>
Ben Warren736fead2009-07-20 22:01:11 -070028#include <netdev.h>
Stefano Babic86271112011-03-14 15:43:56 +010029#include <asm/arch/clock.h>
30#include <asm/arch/imx-regs.h>
Fabio Estevamb73850f2011-04-10 08:17:50 +000031#include <watchdog.h>
Magnus Lilja8449f282009-07-01 01:07:55 +020032
33DECLARE_GLOBAL_DATA_PTR;
34
Fabio Estevamb73850f2011-04-10 08:17:50 +000035#ifdef CONFIG_HW_WATCHDOG
36void hw_watchdog_reset(void)
37{
38 mxc_hw_watchdog_reset();
39}
40#endif
41
Magnus Lilja8449f282009-07-01 01:07:55 +020042int dram_init(void)
43{
Fabio Estevamed3df722011-02-09 01:17:55 +000044 /* dram_init must store complete ramsize in gd->ram_size */
Albert ARIBAUDa55d23c2011-07-03 05:55:33 +000045 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
Fabio Estevamed3df722011-02-09 01:17:55 +000046 PHYS_SDRAM_1_SIZE);
47 return 0;
48}
49
Fabio Estevam9b6442f2011-02-09 01:17:56 +000050int board_early_init_f(void)
Magnus Lilja8449f282009-07-01 01:07:55 +020051{
52 /* CS5: CPLD incl. network controller */
53 __REG(CSCR_U(5)) = 0x0000d843;
54 __REG(CSCR_L(5)) = 0x22252521;
55 __REG(CSCR_A(5)) = 0x22220a00;
56
57 /* Setup UART1 and SPI2 pins */
58 mx31_uart1_hw_init();
59 mx31_spi2_hw_init();
60
Fabio Estevam9b6442f2011-02-09 01:17:56 +000061 return 0;
62}
63
64int board_init(void)
65{
Magnus Lilja8449f282009-07-01 01:07:55 +020066 /* adress of boot parameters */
67 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
68
69 return 0;
70}
71
Fabio Estevamb73850f2011-04-10 08:17:50 +000072int board_late_init(void)
73{
74#ifdef CONFIG_HW_WATCHDOG
75 mxc_hw_watchdog_enable();
76#endif
77 return 0;
78}
79
Magnus Lilja8449f282009-07-01 01:07:55 +020080int checkboard(void)
81{
Fabio Estevame9e07902011-04-18 07:38:12 +000082 printf("Board: MX31PDK\n");
Magnus Lilja8449f282009-07-01 01:07:55 +020083 return 0;
84}
Ben Warren736fead2009-07-20 22:01:11 -070085
86int board_eth_init(bd_t *bis)
87{
88 int rc = 0;
89#ifdef CONFIG_SMC911X
90 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
91#endif
92 return rc;
93}