blob: 698c4cf0c511e7bf507a8f62549ca3de3a3703af [file] [log] [blame]
Stefano Babiceae49882011-01-20 08:05:15 +00001/*
2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
3 *
4 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21
22#include <config.h>
23#include <asm/arch/imx-regs.h>
Stefano Babica4814a62011-09-05 04:32:28 +000024#include <generated/asm-offsets.h>
Stefano Babiceae49882011-01-20 08:05:15 +000025#include "mx35pdk.h"
26
27/*
28 * return soc version
29 * 0x10: TO1
30 * 0x20: TO2
31 * 0x30: TO3
32 */
33.macro check_soc_version ret, tmp
34 ldr \tmp, =IIM_BASE_ADDR
35 ldr \ret, [\tmp, #IIM_SREV]
36 cmp \ret, #0x00
37 moveq \tmp, #ROMPATCH_REV
38 ldreq \ret, [\tmp]
39 moveq \ret, \ret, lsl #4
40 addne \ret, \ret, #0x10
41.endm
42
43/*
44 * AIPS setup - Only setup MPROTx registers.
45 * The PACR default values are good.
46 */
47.macro init_aips
48 /*
49 * Set all MPROTx to be non-bufferable, trusted for R/W,
50 * not forced to user-mode.
51 */
52 ldr r0, =AIPS1_BASE_ADDR
53 ldr r1, =AIPS_MPR_CONFIG
54 str r1, [r0, #0x00]
55 str r1, [r0, #0x04]
56 ldr r0, =AIPS2_BASE_ADDR
57 str r1, [r0, #0x00]
58 str r1, [r0, #0x04]
59
60 /*
61 * Clear the on and off peripheral modules Supervisor Protect bit
62 * for SDMA to access them. Did not change the AIPS control registers
63 * (offset 0x20) access type
64 */
65 ldr r0, =AIPS1_BASE_ADDR
66 ldr r1, =AIPS_OPACR_CONFIG
67 str r1, [r0, #0x40]
68 str r1, [r0, #0x44]
69 str r1, [r0, #0x48]
70 str r1, [r0, #0x4C]
71 str r1, [r0, #0x50]
72 ldr r0, =AIPS2_BASE_ADDR
73 str r1, [r0, #0x40]
74 str r1, [r0, #0x44]
75 str r1, [r0, #0x48]
76 str r1, [r0, #0x4C]
77 str r1, [r0, #0x50]
78.endm
79
80/* MAX (Multi-Layer AHB Crossbar Switch) setup */
81.macro init_max
82 ldr r0, =MAX_BASE_ADDR
83 /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
84 ldr r1, =MAX_MPR_CONFIG
85 str r1, [r0, #0x000] /* for S0 */
86 str r1, [r0, #0x100] /* for S1 */
87 str r1, [r0, #0x200] /* for S2 */
88 str r1, [r0, #0x300] /* for S3 */
89 str r1, [r0, #0x400] /* for S4 */
90 /* SGPCR - always park on last master */
91 ldr r1, =MAX_SGPCR_CONFIG
92 str r1, [r0, #0x010] /* for S0 */
93 str r1, [r0, #0x110] /* for S1 */
94 str r1, [r0, #0x210] /* for S2 */
95 str r1, [r0, #0x310] /* for S3 */
96 str r1, [r0, #0x410] /* for S4 */
97 /* MGPCR - restore default values */
98 ldr r1, =MAX_MGPCR_CONFIG
99 str r1, [r0, #0x800] /* for M0 */
100 str r1, [r0, #0x900] /* for M1 */
101 str r1, [r0, #0xA00] /* for M2 */
102 str r1, [r0, #0xB00] /* for M3 */
103 str r1, [r0, #0xC00] /* for M4 */
104 str r1, [r0, #0xD00] /* for M5 */
105.endm
106
107/* M3IF setup */
108.macro init_m3if
109 /* Configure M3IF registers */
110 ldr r1, =M3IF_BASE_ADDR
111 /*
112 * M3IF Control Register (M3IFCTL)
113 * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
114 * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
115 * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
116 * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
117 * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
118 * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
119 * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
120 * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
121 * ------------
122 * 0x00000040
123 */
124 ldr r0, =M3IF_CONFIG
125 str r0, [r1] /* M3IF control reg */
126.endm
127
128/* CPLD on CS5 setup */
129.macro init_debug_board
130 ldr r0, =DBG_BASE_ADDR
131 ldr r1, =DBG_CSCR_U_CONFIG
132 str r1, [r0, #0x00]
133 ldr r1, =DBG_CSCR_L_CONFIG
134 str r1, [r0, #0x04]
135 ldr r1, =DBG_CSCR_A_CONFIG
136 str r1, [r0, #0x08]
137.endm
138
139/* clock setup */
140.macro init_clock
141 ldr r0, =CCM_BASE_ADDR
142
143 /* default CLKO to 1/32 of the ARM core*/
144 ldr r1, [r0, #CLKCTL_COSR]
145 bic r1, r1, #0x00000FF00
146 bic r1, r1, #0x0000000FF
147 mov r2, #0x00006C00
148 add r2, r2, #0x67
149 orr r1, r1, r2
150 str r1, [r0, #CLKCTL_COSR]
151
152 ldr r2, =CCM_CCMR_CONFIG
153 str r2, [r0, #CLKCTL_CCMR]
154
155 check_soc_version r1, r2
156 cmp r1, #CHIP_REV_2_0
157 ldrhs r3, =CCM_MPLL_532_HZ
158 bhs 1f
159 ldr r2, [r0, #CLKCTL_PDR0]
160 tst r2, #CLKMODE_CONSUMER
161 ldrne r3, =CCM_MPLL_532_HZ /* consumer path*/
162 ldreq r3, =CCM_MPLL_399_HZ /* auto path*/
1631:
164 str r3, [r0, #CLKCTL_MPCTL]
165
166 ldr r1, =CCM_PPLL_300_HZ
167 str r1, [r0, #CLKCTL_PPCTL]
168
169 ldr r1, =CCM_PDR0_CONFIG
170 bic r1, r1, #0x800000
171 str r1, [r0, #CLKCTL_PDR0]
172
173 ldr r1, [r0, #CLKCTL_CGR0]
174 orr r1, r1, #0x0C300000
175 str r1, [r0, #CLKCTL_CGR0]
176
177 ldr r1, [r0, #CLKCTL_CGR1]
178 orr r1, r1, #0x00000C00
179 orr r1, r1, #0x00000003
180 str r1, [r0, #CLKCTL_CGR1]
181.endm
182
183.macro setup_sdram
184 ldr r0, =ESDCTL_BASE_ADDR
185 mov r3, #0x2000
186 str r3, [r0, #0x0]
187 str r3, [r0, #0x8]
188
189 /*ip(r12) has used to save lr register in upper calling*/
190 mov fp, lr
191
192 mov r5, #0x00
193 mov r2, #0x00
194 mov r1, #CSD0_BASE_ADDR
195 bl setup_sdram_bank
Stefano Babic6b5acfc2011-08-02 14:42:36 +0200196
197 mov r5, #0x00
198 mov r2, #0x00
199 mov r1, #CSD1_BASE_ADDR
200 bl setup_sdram_bank
Stefano Babiceae49882011-01-20 08:05:15 +0000201
202 mov lr, fp
203
2041:
205 ldr r3, =ESDCTL_DELAY_LINE5
206 str r3, [r0, #0x30]
207.endm
208
209.globl lowlevel_init
210lowlevel_init:
211 mov r10, lr
212
213 mrc 15, 0, r1, c1, c0, 0
214
215 mrc 15, 0, r0, c1, c0, 1
216 orr r0, r0, #7
217 mcr 15, 0, r0, c1, c0, 1
218 orr r1, r1, #(1<<11)
219
220 /* Set unaligned access enable */
221 orr r1, r1, #(1<<22)
222
223 /* Set low int latency enable */
224 orr r1, r1, #(1<<21)
225
226 mcr 15, 0, r1, c1, c0, 0
227
228 mov r0, #0
229
230 /* Set branch prediction enable */
231 mcr 15, 0, r0, c15, c2, 4
232
233 mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
234 mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
235 mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
236
237 /*
238 * initializes very early AIPS
239 * Then it also initializes Multi-Layer AHB Crossbar Switch,
240 * M3IF
241 * Also setup the Peripheral Port Remap register inside the core
242 */
243 ldr r0, =0x40000015 /* start from AIPS 2GB region */
244 mcr p15, 0, r0, c15, c2, 4
245
246 init_aips
247
248 init_max
249
250 init_m3if
251
252 init_clock
253 init_debug_board
254
255 cmp pc, #PHYS_SDRAM_1
256 blo init_sdram_start
257 cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
258 blo skip_sdram_setup
259
260init_sdram_start:
261 /*init_sdram*/
262 setup_sdram
263
264skip_sdram_setup:
265 mov lr, r10
266 mov pc, lr
267
268
269/*
270 * r0: ESDCTL control base, r1: sdram slot base
271 * r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base
272 */
273setup_sdram_bank:
274 mov r3, #0xE
275 tst r2, #0x1
276 orreq r3, r3, #0x300 /*DDR2*/
277 str r3, [r0, #0x10]
278 bic r3, r3, #0x00A
279 str r3, [r0, #0x10]
280 beq 2f
281
282 mov r3, #0x20000
2831: subs r3, r3, #1
284 bne 1b
285
2862: tst r2, #0x1
287 ldreq r3, =ESDCTL_DDR2_CONFIG
288 ldrne r3, =ESDCTL_MDDR_CONFIG
289 cmp r1, #CSD1_BASE_ADDR
290 strlo r3, [r0, #0x4]
291 strhs r3, [r0, #0xC]
292
293 ldr r3, =ESDCTL_0x92220000
294 strlo r3, [r0, #0x0]
295 strhs r3, [r0, #0x8]
296 mov r3, #0xDA
297 ldr r4, =ESDCTL_PRECHARGE
298 strb r3, [r1, r4]
299
300 tst r2, #0x1
301 bne skip_set_mode
302
303 cmp r1, #CSD1_BASE_ADDR
304 ldr r3, =ESDCTL_0xB2220000
305 strlo r3, [r0, #0x0]
306 strhs r3, [r0, #0x8]
307 mov r3, #0xDA
308 ldr r4, =ESDCTL_DDR2_EMR2
309 strb r3, [r1, r4]
310 ldr r4, =ESDCTL_DDR2_EMR3
311 strb r3, [r1, r4]
312 ldr r4, =ESDCTL_DDR2_EN_DLL
313 strb r3, [r1, r4]
314 ldr r4, =ESDCTL_DDR2_RESET_DLL
315 strb r3, [r1, r4]
316
317 ldr r3, =ESDCTL_0x92220000
318 strlo r3, [r0, #0x0]
319 strhs r3, [r0, #0x8]
320 mov r3, #0xDA
321 ldr r4, =ESDCTL_PRECHARGE
322 strb r3, [r1, r4]
323
324skip_set_mode:
325 cmp r1, #CSD1_BASE_ADDR
326 ldr r3, =ESDCTL_0xA2220000
327 strlo r3, [r0, #0x0]
328 strhs r3, [r0, #0x8]
329 mov r3, #0xDA
330 strb r3, [r1]
331 strb r3, [r1]
332
333 ldr r3, =ESDCTL_0xB2220000
334 strlo r3, [r0, #0x0]
335 strhs r3, [r0, #0x8]
336 tst r2, #0x1
337 ldreq r4, =ESDCTL_DDR2_MR
338 ldrne r4, =ESDCTL_MDDR_MR
339 mov r3, #0xDA
340 strb r3, [r1, r4]
341 ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT
342 streqb r3, [r1, r4]
343 ldreq r4, =ESDCTL_DDR2_EN_DLL
344 ldrne r4, =ESDCTL_MDDR_EMR
345 strb r3, [r1, r4]
346
347 cmp r1, #CSD1_BASE_ADDR
348 ldr r3, =ESDCTL_0x82228080
349 strlo r3, [r0, #0x0]
350 strhs r3, [r0, #0x8]
351
352 tst r2, #0x1
353 moveq r4, #0x20000
354 movne r4, #0x200
3551: subs r4, r4, #1
356 bne 1b
357
358 str r3, [r1, #0x100]
359 ldr r4, [r1, #0x100]
360 cmp r3, r4
361 movne r3, #1
362 moveq r3, #0
363
364 mov pc, lr