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Heiko Schocher258c37b2008-08-21 20:44:49 +02001/*
2 * (C) Copyright 2008
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
5 * (C) Copyright 2003-2005
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/*
31 * High Level Configuration Options
32 * (easy to change)
33 */
34
35#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
36#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
37#define CONFIG_MUCMC52 1 /* MUCMC52 board */
38
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020039#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
Heiko Schocher258c37b2008-08-21 20:44:49 +020040
41#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
42#define BOOTFLAG_WARM 0x02 /* Software reboot */
43
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
45#if (CONFIG_COMMANDS & CONFIG_SYS_CMD_KGDB)
46# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Heiko Schocher258c37b2008-08-21 20:44:49 +020047#endif
48
49#define CONFIG_BOARD_EARLY_INIT_R
50
51#define CONFIG_LAST_STAGE_INIT
52
53#define CONFIG_HIGH_BATS 1 /* High BATs supported */
54/*
55 * Serial console configuration
56 */
57#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
58#define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
Heiko Schocher258c37b2008-08-21 20:44:49 +020060
61/* Partitions */
62#define CONFIG_DOS_PARTITION
63
64/*
65 * Command line configuration.
66 */
67#include <config_cmd_default.h>
68
69#define CONFIG_CMD_DATE
70#define CONFIG_CMD_DISPLAY
71#define CONFIG_CMD_DHCP
72#define CONFIG_CMD_EEPROM
73#define CONFIG_CMD_FAT
74#define CONFIG_CMD_I2C
75#define CONFIG_CMD_DTT
76#define CONFIG_CMD_IDE
77#define CONFIG_CMD_MII
78#define CONFIG_CMD_NFS
79#define CONFIG_CMD_PCI
80#define CONFIG_CMD_PING
81#define CONFIG_CMD_SNTP
82
83#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
84
85#if (TEXT_BASE == 0xFFF00000) /* Boot low */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086# define CONFIG_SYS_LOWBOOT 1
Heiko Schocher258c37b2008-08-21 20:44:49 +020087#endif
88
89/*
90 * Autobooting
91 */
92#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
93
94#define CONFIG_PREBOOT "echo;" \
95 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
96 "echo"
97
98#undef CONFIG_BOOTARGS
99
100#define CONFIG_EXTRA_ENV_SETTINGS \
101 "netdev=eth0\0" \
102 "nfsargs=setenv bootargs root=/dev/nfs rw " \
103 "nfsroot=${serverip}:${rootpath}\0" \
104 "ramargs=setenv bootargs root=/dev/ram rw\0" \
105 "addip=setenv bootargs ${bootargs} " \
106 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
107 ":${hostname}:${netdev}:off panic=1\0" \
108 "flash_nfs=run nfsargs addip;" \
109 "bootm ${kernel_addr}\0" \
110 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
111 "rootpath=/opt/eldk/ppc_82xx\0" \
112 ""
113
114#define CONFIG_BOOTCOMMAND "run net_nfs"
115
116#define CONFIG_MISC_INIT_R 1
117
118/*
119 * IPB Bus clocking configuration.
120 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
Heiko Schocher258c37b2008-08-21 20:44:49 +0200122
123/*
124 * I2C configuration
125 */
126#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
Heiko Schocher258c37b2008-08-21 20:44:49 +0200128
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
130#define CONFIG_SYS_I2C_SLAVE 0x7F
Heiko Schocher258c37b2008-08-21 20:44:49 +0200131
132/*
133 * EEPROM configuration
134 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
136#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
137#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
138#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
Heiko Schocher258c37b2008-08-21 20:44:49 +0200139
140/*
141 * RTC configuration
142 */
143#define CONFIG_RTC_PCF8563
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_I2C_RTC_ADDR 0x51
Heiko Schocher258c37b2008-08-21 20:44:49 +0200145
146/* I2C SYSMON (LM75) */
147#define CONFIG_DTT_LM81 1 /* ON Semi's LM75 */
148#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_DTT_MAX_TEMP 70
150#define CONFIG_SYS_DTT_LOW_TEMP -30
151#define CONFIG_SYS_DTT_HYSTERESIS 3
Heiko Schocher258c37b2008-08-21 20:44:49 +0200152
153/*
154 * Flash configuration
155 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_FLASH_BASE 0xFF800000
Heiko Schocher258c37b2008-08-21 20:44:49 +0200157
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */
159#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max num of sects on one chip */
Heiko Schocher258c37b2008-08-21 20:44:49 +0200160
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200161#define CONFIG_ENV_ADDR (TEXT_BASE+0x40000) /* second sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
Heiko Schocher258c37b2008-08-21 20:44:49 +0200163 (= chip selects) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
165#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
Heiko Schocher258c37b2008-08-21 20:44:49 +0200166
167#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_FLASH_CFI
169#define CONFIG_SYS_FLASH_EMPTY_INFO
170#define CONFIG_SYS_FLASH_CFI_AMD_RESET
Heiko Schocher258c37b2008-08-21 20:44:49 +0200171
172/*
173 * Environment settings
174 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200175#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200176#define CONFIG_ENV_SIZE 0x4000
177#define CONFIG_ENV_SECT_SIZE 0x20000
178#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
179#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Heiko Schocher258c37b2008-08-21 20:44:49 +0200180
181/*
182 * Memory map
183 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_MBAR 0xF0000000
185#define CONFIG_SYS_SDRAM_BASE 0x00000000
186#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
187#define CONFIG_SYS_DISPLAY_BASE 0x80600000
188#define CONFIG_SYS_STATUS1_BASE 0x80600200
189#define CONFIG_SYS_STATUS2_BASE 0x80600300
190#define CONFIG_SYS_PMI_UNI_BASE 0x80800000
191#define CONFIG_SYS_PMI_BROAD_BASE 0x80810000
Heiko Schocher258c37b2008-08-21 20:44:49 +0200192
193/* Settings for XLB = 132 MHz */
194#define SDRAM_DDR 1
195#define SDRAM_MODE 0x018D0000
196#define SDRAM_EMODE 0x40090000
197#define SDRAM_CONTROL 0x714f0f00
198#define SDRAM_CONFIG1 0x73722930
199#define SDRAM_CONFIG2 0x47770000
200#define SDRAM_TAPDELAY 0x10000000
201
202/* Use ON-Chip SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Heiko Schocher258c37b2008-08-21 20:44:49 +0200204#ifdef CONFIG_POST
205/* preserve space for the post_word at end of on-chip SRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
Heiko Schocher258c37b2008-08-21 20:44:49 +0200207#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
Heiko Schocher258c37b2008-08-21 20:44:49 +0200209#endif
210
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
212#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
213#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Heiko Schocher258c37b2008-08-21 20:44:49 +0200214
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
216#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
217# define CONFIG_SYS_RAMBOOT 1
Heiko Schocher258c37b2008-08-21 20:44:49 +0200218#endif
219
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
221#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 128 kB for malloc() */
222#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Heiko Schocher258c37b2008-08-21 20:44:49 +0200223
224/*
225 * Ethernet configuration
226 */
227#define CONFIG_MPC5xxx_FEC 1
228#define CONFIG_PHY_ADDR 0x00
229#define CONFIG_MII 1 /* MII PHY management */
230
231/*
232 * GPIO configuration
233 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_GPS_PORT_CONFIG 0x8D550644
Heiko Schocher258c37b2008-08-21 20:44:49 +0200235
236/*use Hardware WDT */
237#define CONFIG_HW_WATCHDOG
238
239/*
240 * Miscellaneous configurable options
241 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_LONGHELP /* undef to save memory */
243#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
244#if (CONFIG_COMMANDS & CONFIG_SYS_CMD_KGDB)
245#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Heiko Schocher258c37b2008-08-21 20:44:49 +0200246#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Heiko Schocher258c37b2008-08-21 20:44:49 +0200248#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
250#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
251#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Heiko Schocher258c37b2008-08-21 20:44:49 +0200252
253/* Enable an alternate, more extensive memory test */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_ALT_MEMTEST
Heiko Schocher258c37b2008-08-21 20:44:49 +0200255
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
257#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
Heiko Schocher258c37b2008-08-21 20:44:49 +0200258
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Heiko Schocher258c37b2008-08-21 20:44:49 +0200260
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Heiko Schocher258c37b2008-08-21 20:44:49 +0200262
263/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264 * Enable loopw commando. This has only affect, if CONFIG_SYS_CMD_MEM is defined,
Heiko Schocher258c37b2008-08-21 20:44:49 +0200265 * which is normally part of the default commands (CFV_CMD_DFL)
266 */
267#define CONFIG_LOOPW
268
269/*
270 * Various low-level settings
271 */
272#if defined(CONFIG_MPC5200)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
274#define CONFIG_SYS_HID0_FINAL HID0_ICE
Heiko Schocher258c37b2008-08-21 20:44:49 +0200275#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_HID0_INIT 0
277#define CONFIG_SYS_HID0_FINAL 0
Heiko Schocher258c37b2008-08-21 20:44:49 +0200278#endif
279
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
281#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
282#define CONFIG_SYS_BOOTCS_CFG 0x0004FB00
283#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
284#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
Heiko Schocher258c37b2008-08-21 20:44:49 +0200285
286/* 8Mbit SRAM @0x80100000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_CS1_START 0x80100000
288#define CONFIG_SYS_CS1_SIZE 0x00100000
289#define CONFIG_SYS_CS1_CFG 0x00019B00
Heiko Schocher258c37b2008-08-21 20:44:49 +0200290
291/* FRAM 32Kbyte @0x80700000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_CS2_START 0x80700000
293#define CONFIG_SYS_CS2_SIZE 0x00008000
294#define CONFIG_SYS_CS2_CFG 0x00019800
Heiko Schocher258c37b2008-08-21 20:44:49 +0200295
296/* Display H1, Status Inputs, EPLD @0x80600000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_CS3_START 0x80600000
298#define CONFIG_SYS_CS3_SIZE 0x00100000
299#define CONFIG_SYS_CS3_CFG 0x00019800
Heiko Schocher258c37b2008-08-21 20:44:49 +0200300
301/* PMI Unicast 32Kbyte @0x80800000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_CS6_START CONFIG_SYS_PMI_UNI_BASE
303#define CONFIG_SYS_CS6_SIZE 0x00008000
304#define CONFIG_SYS_CS6_CFG 0xFFFFF930
Heiko Schocher258c37b2008-08-21 20:44:49 +0200305
306/* PMI Broadcast 32Kbyte @0x80810000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#define CONFIG_SYS_CS7_START CONFIG_SYS_PMI_BROAD_BASE
308#define CONFIG_SYS_CS7_SIZE 0x00008000
309#define CONFIG_SYS_CS7_CFG 0xFF00F930
Heiko Schocher258c37b2008-08-21 20:44:49 +0200310
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_CS_BURST 0x00000000
312#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
Heiko Schocher258c37b2008-08-21 20:44:49 +0200313
314/*-----------------------------------------------------------------------
315 * IDE/ATA stuff Supports IDE harddisk
316 *-----------------------------------------------------------------------
317 */
318
319#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
320
321#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
322#undef CONFIG_IDE_LED /* LED for ide not supported */
323
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
325#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */
Heiko Schocher258c37b2008-08-21 20:44:49 +0200326
327#define CONFIG_IDE_PREINIT 1
328
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Heiko Schocher258c37b2008-08-21 20:44:49 +0200330
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
Heiko Schocher258c37b2008-08-21 20:44:49 +0200332
333/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
Heiko Schocher258c37b2008-08-21 20:44:49 +0200335
336/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
Heiko Schocher258c37b2008-08-21 20:44:49 +0200338
339/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
Heiko Schocher258c37b2008-08-21 20:44:49 +0200341
342/* Interval between registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343#define CONFIG_SYS_ATA_STRIDE 4
Heiko Schocher258c37b2008-08-21 20:44:49 +0200344
345#define CONFIG_ATAPI 1
346
347/*
348 * PCI Mapping:
349 * 0x40000000 - 0x4fffffff - PCI Memory
350 * 0x50000000 - 0x50ffffff - PCI IO Space
351 */
352#define CONFIG_PCI 1
353#define CONFIG_PCI_PNP 1
354#define CONFIG_PCI_SCAN_SHOW 1
355#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
356
357#define CONFIG_PCI_MEM_BUS 0x40000000
358#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
359#define CONFIG_PCI_MEM_SIZE 0x10000000
360
361#define CONFIG_PCI_IO_BUS 0x50000000
362#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
363#define CONFIG_PCI_IO_SIZE 0x01000000
364
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200365#define CONFIG_SYS_ISA_IO CONFIG_PCI_IO_BUS
Heiko Schocher258c37b2008-08-21 20:44:49 +0200366
367/*---------------------------------------------------------------------*/
368/* Display addresses */
369/*---------------------------------------------------------------------*/
370
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200371#define CONFIG_SYS_DISP_CHR_RAM (CONFIG_SYS_DISPLAY_BASE + 0x38)
372#define CONFIG_SYS_DISP_CWORD (CONFIG_SYS_DISPLAY_BASE + 0x30)
Heiko Schocher258c37b2008-08-21 20:44:49 +0200373
374#endif /* __CONFIG_H */