blob: 1eaa89f3f44b03e09d99b9a1eb51a2910e644922 [file] [log] [blame]
Stefan Roeseae691e52009-01-21 17:24:49 +01001/*
2 * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Stefan Roeseae691e52009-01-21 17:24:49 +01005 */
6
7#include <common.h>
8#include <asm/io.h>
9#include "vct.h"
10
11/*
12 * Find out to which of the 2 gpio modules the pin specified in the
13 * argument belongs:
14 * GPIO_MODULE yields 0 for pins 0 to 31,
15 * 1 for pins 32 to 63
16 */
17#define GPIO_MODULE(pin) ((pin) >> 5)
18
19/*
20 * Bit position within a 32-bit peripheral register (where every
21 * bit is one bitslice)
22 */
23#define MASK(pin) (1 << ((pin) & 0x1F))
24#define BASE_ADDR(mod) module_base[mod]
25
26/*
27 * Lookup table for transforming gpio module number 0 to 2 to
28 * address offsets
29 */
30static u32 module_base[] = {
31 GPIO1_BASE,
32 GPIO2_BASE
33};
34
35static void clrsetbits(u32 addr, u32 and_mask, u32 or_mask)
36{
37 reg_write(addr, (reg_read(addr) & ~and_mask) | or_mask);
38}
39
40int vct_gpio_dir(int pin, int dir)
41{
42 u32 gpio_base;
43
44 gpio_base = BASE_ADDR(GPIO_MODULE(pin));
45
46 if (dir == 0)
47 clrsetbits(GPIO_SWPORTA_DDR(gpio_base), MASK(pin), 0);
48 else
49 clrsetbits(GPIO_SWPORTA_DDR(gpio_base), 0, MASK(pin));
50
51 return 0;
52}
53
54void vct_gpio_set(int pin, int val)
55{
56 u32 gpio_base;
57
58 gpio_base = BASE_ADDR(GPIO_MODULE(pin));
59
60 if (val == 0)
61 clrsetbits(GPIO_SWPORTA_DR(gpio_base), MASK(pin), 0);
62 else
63 clrsetbits(GPIO_SWPORTA_DR(gpio_base), 0, MASK(pin));
64}
65
66int vct_gpio_get(int pin)
67{
68 u32 gpio_base;
69 u32 value;
70
71 gpio_base = BASE_ADDR(GPIO_MODULE(pin));
72 value = reg_read(GPIO_EXT_PORTA(gpio_base));
73
74 return ((value & MASK(pin)) ? 1 : 0);
75}