Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 1 | /* |
Haiying Wang | 3d98b85 | 2007-01-22 12:37:30 -0600 | [diff] [blame] | 2 | * Copyright 2006, 2007 Freescale Semiconductor. |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 3 | * |
| 4 | * See file CREDITS for list of people who contributed to this |
| 5 | * project. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
Ed Swarthout | 63cec58 | 2007-08-02 14:09:49 -0500 | [diff] [blame] | 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | */ |
| 22 | |
| 23 | #include <common.h> |
| 24 | #include <pci.h> |
| 25 | #include <asm/processor.h> |
| 26 | #include <asm/immap_86xx.h> |
Ed Swarthout | 63cec58 | 2007-08-02 14:09:49 -0500 | [diff] [blame] | 27 | #include <asm/immap_fsl_pci.h> |
Kumar Gala | 6a8e569 | 2008-08-26 15:01:35 -0500 | [diff] [blame] | 28 | #include <asm/fsl_ddr_sdram.h> |
Haiying Wang | 3d98b85 | 2007-01-22 12:37:30 -0600 | [diff] [blame] | 29 | #include <asm/io.h> |
Jon Loeliger | ea9f739 | 2007-11-28 14:47:18 -0600 | [diff] [blame] | 30 | #include <libfdt.h> |
| 31 | #include <fdt_support.h> |
Ben Warren | 0b252f5 | 2008-08-31 21:41:08 -0700 | [diff] [blame] | 32 | #include <netdev.h> |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 33 | |
Jon Loeliger | 4ce9177 | 2007-08-15 12:20:40 -0500 | [diff] [blame] | 34 | #include "../common/pixis.h" |
Jon Loeliger | 4d3d729 | 2006-05-31 11:24:28 -0500 | [diff] [blame] | 35 | |
Becky Bruce | 4c77de3 | 2008-10-31 17:13:32 -0500 | [diff] [blame] | 36 | phys_size_t fixed_sdram(void); |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 37 | |
Jon Loeliger | 80e955c | 2006-08-22 12:25:27 -0500 | [diff] [blame] | 38 | int board_early_init_f(void) |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 39 | { |
Jon Loeliger | cb5965f | 2006-05-31 12:44:44 -0500 | [diff] [blame] | 40 | return 0; |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 41 | } |
| 42 | |
Jon Loeliger | 80e955c | 2006-08-22 12:25:27 -0500 | [diff] [blame] | 43 | int checkboard(void) |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 44 | { |
Wolfgang Denk | 9b55a25 | 2008-07-11 01:16:00 +0200 | [diff] [blame] | 45 | printf ("Board: MPC8641HPCN, System ID: 0x%02x, " |
| 46 | "System Version: 0x%02x, FPGA Version: 0x%02x\n", |
Kumar Gala | 7de8c21 | 2008-06-19 01:45:27 -0500 | [diff] [blame] | 47 | in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), |
| 48 | in8(PIXIS_BASE + PIXIS_PVER)); |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 49 | return 0; |
| 50 | } |
| 51 | |
| 52 | |
Becky Bruce | 9973e3c | 2008-06-09 16:03:40 -0500 | [diff] [blame] | 53 | phys_size_t |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 54 | initdram(int board_type) |
| 55 | { |
Becky Bruce | 4c77de3 | 2008-10-31 17:13:32 -0500 | [diff] [blame] | 56 | phys_size_t dram_size = 0; |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 57 | |
| 58 | #if defined(CONFIG_SPD_EEPROM) |
Kumar Gala | 6a8e569 | 2008-08-26 15:01:35 -0500 | [diff] [blame] | 59 | dram_size = fsl_ddr_sdram(); |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 60 | #else |
Jon Loeliger | 80e955c | 2006-08-22 12:25:27 -0500 | [diff] [blame] | 61 | dram_size = fixed_sdram(); |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 62 | #endif |
| 63 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 64 | #if defined(CONFIG_SYS_RAMBOOT) |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 65 | puts(" DDR: "); |
| 66 | return dram_size; |
| 67 | #endif |
Jon Loeliger | cb5965f | 2006-05-31 12:44:44 -0500 | [diff] [blame] | 68 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 69 | puts(" DDR: "); |
| 70 | return dram_size; |
| 71 | } |
| 72 | |
| 73 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 74 | #if !defined(CONFIG_SPD_EEPROM) |
Jon Loeliger | 5c9efb3 | 2006-04-27 10:15:16 -0500 | [diff] [blame] | 75 | /* |
| 76 | * Fixed sdram init -- doesn't use serial presence detect. |
| 77 | */ |
Becky Bruce | 4c77de3 | 2008-10-31 17:13:32 -0500 | [diff] [blame] | 78 | phys_size_t |
Jon Loeliger | 80e955c | 2006-08-22 12:25:27 -0500 | [diff] [blame] | 79 | fixed_sdram(void) |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 80 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 81 | #if !defined(CONFIG_SYS_RAMBOOT) |
| 82 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
Jon Loeliger | 80e955c | 2006-08-22 12:25:27 -0500 | [diff] [blame] | 83 | volatile ccsr_ddr_t *ddr = &immap->im_ddr1; |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 84 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 85 | ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; |
| 86 | ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; |
| 87 | ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; |
| 88 | ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; |
| 89 | ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; |
| 90 | ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; |
| 91 | ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1; |
| 92 | ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; |
| 93 | ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; |
| 94 | ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; |
| 95 | ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; |
| 96 | ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL; |
| 97 | ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS; |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 98 | |
| 99 | #if defined (CONFIG_DDR_ECC) |
| 100 | ddr->err_disable = 0x0000008D; |
| 101 | ddr->err_sbe = 0x00ff0000; |
| 102 | #endif |
| 103 | asm("sync;isync"); |
Jon Loeliger | cb5965f | 2006-05-31 12:44:44 -0500 | [diff] [blame] | 104 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 105 | udelay(500); |
| 106 | |
| 107 | #if defined (CONFIG_DDR_ECC) |
| 108 | /* Enable ECC checking */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 109 | ddr->sdram_cfg_1 = (CONFIG_SYS_DDR_CONTROL | 0x20000000); |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 110 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 111 | ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CONTROL; |
| 112 | ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 113 | #endif |
| 114 | asm("sync; isync"); |
Jon Loeliger | cb5965f | 2006-05-31 12:44:44 -0500 | [diff] [blame] | 115 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 116 | udelay(500); |
| 117 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 118 | return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 119 | } |
| 120 | #endif /* !defined(CONFIG_SPD_EEPROM) */ |
| 121 | |
| 122 | |
| 123 | #if defined(CONFIG_PCI) |
Becky Bruce | 98693b8 | 2008-10-31 17:14:00 -0500 | [diff] [blame] | 124 | static struct pci_controller pci1_hose; |
Jon Loeliger | 80e955c | 2006-08-22 12:25:27 -0500 | [diff] [blame] | 125 | #endif /* CONFIG_PCI */ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 126 | |
Ed Swarthout | 63cec58 | 2007-08-02 14:09:49 -0500 | [diff] [blame] | 127 | #ifdef CONFIG_PCI2 |
| 128 | static struct pci_controller pci2_hose; |
| 129 | #endif /* CONFIG_PCI2 */ |
| 130 | |
| 131 | int first_free_busno = 0; |
| 132 | |
Kumar Gala | c2083e0 | 2008-10-22 14:38:55 -0500 | [diff] [blame] | 133 | extern int fsl_pci_setup_inbound_windows(struct pci_region *r); |
| 134 | extern void fsl_pci_init(struct pci_controller *hose); |
Ed Swarthout | 63cec58 | 2007-08-02 14:09:49 -0500 | [diff] [blame] | 135 | |
Jon Loeliger | 80e955c | 2006-08-22 12:25:27 -0500 | [diff] [blame] | 136 | void pci_init_board(void) |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 137 | { |
Ed Swarthout | 63cec58 | 2007-08-02 14:09:49 -0500 | [diff] [blame] | 138 | #ifdef CONFIG_PCI1 |
| 139 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 140 | volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; |
Ed Swarthout | 63cec58 | 2007-08-02 14:09:49 -0500 | [diff] [blame] | 141 | struct pci_controller *hose = &pci1_hose; |
Kumar Gala | c2083e0 | 2008-10-22 14:38:55 -0500 | [diff] [blame] | 142 | struct pci_region *r = hose->regions; |
Becky Bruce | af5d100 | 2008-10-31 17:14:14 -0500 | [diff] [blame] | 143 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; |
| 144 | volatile ccsr_gur_t *gur = &immap->im_gur; |
| 145 | uint devdisr = gur->devdisr; |
| 146 | uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL) |
| 147 | >> MPC8641_PORDEVSR_IO_SEL_SHIFT; |
Kumar Gala | c2083e0 | 2008-10-22 14:38:55 -0500 | [diff] [blame] | 148 | |
Ed Swarthout | 63cec58 | 2007-08-02 14:09:49 -0500 | [diff] [blame] | 149 | #ifdef DEBUG |
Jon Loeliger | a551cee | 2008-02-20 14:22:26 -0600 | [diff] [blame] | 150 | uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA) |
| 151 | >> MPC8641_PORBMSR_HA_SHIFT; |
Ed Swarthout | 63cec58 | 2007-08-02 14:09:49 -0500 | [diff] [blame] | 152 | uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); |
| 153 | #endif |
| 154 | if ((io_sel == 2 || io_sel == 3 || io_sel == 5 |
| 155 | || io_sel == 6 || io_sel == 7 || io_sel == 0xF) |
| 156 | && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { |
| 157 | debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); |
| 158 | debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det); |
| 159 | if (pci->pme_msg_det) { |
| 160 | pci->pme_msg_det = 0xffffffff; |
| 161 | debug(" with errors. Clearing. Now 0x%08x", |
| 162 | pci->pme_msg_det); |
| 163 | } |
| 164 | debug("\n"); |
| 165 | |
Ed Swarthout | 63cec58 | 2007-08-02 14:09:49 -0500 | [diff] [blame] | 166 | /* outbound memory */ |
Kumar Gala | c2083e0 | 2008-10-22 14:38:55 -0500 | [diff] [blame] | 167 | pci_set_region(r++, |
Becky Bruce | 49f46f3 | 2009-02-03 18:10:53 -0600 | [diff] [blame] | 168 | CONFIG_SYS_PCI1_MEM_BUS, |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 169 | CONFIG_SYS_PCI1_MEM_PHYS, |
| 170 | CONFIG_SYS_PCI1_MEM_SIZE, |
Ed Swarthout | 63cec58 | 2007-08-02 14:09:49 -0500 | [diff] [blame] | 171 | PCI_REGION_MEM); |
| 172 | |
| 173 | /* outbound io */ |
Kumar Gala | c2083e0 | 2008-10-22 14:38:55 -0500 | [diff] [blame] | 174 | pci_set_region(r++, |
Becky Bruce | 49f46f3 | 2009-02-03 18:10:53 -0600 | [diff] [blame] | 175 | CONFIG_SYS_PCI1_IO_BUS, |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 176 | CONFIG_SYS_PCI1_IO_PHYS, |
| 177 | CONFIG_SYS_PCI1_IO_SIZE, |
Ed Swarthout | 63cec58 | 2007-08-02 14:09:49 -0500 | [diff] [blame] | 178 | PCI_REGION_IO); |
| 179 | |
Becky Bruce | 2ecca34 | 2009-02-03 18:10:49 -0600 | [diff] [blame] | 180 | /* inbound */ |
| 181 | r += fsl_pci_setup_inbound_windows(r); |
| 182 | |
Kumar Gala | c2083e0 | 2008-10-22 14:38:55 -0500 | [diff] [blame] | 183 | hose->region_count = r - hose->regions; |
Ed Swarthout | 63cec58 | 2007-08-02 14:09:49 -0500 | [diff] [blame] | 184 | |
| 185 | hose->first_busno=first_free_busno; |
| 186 | pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); |
| 187 | |
| 188 | fsl_pci_init(hose); |
| 189 | |
| 190 | first_free_busno=hose->last_busno+1; |
| 191 | printf (" PCI-EXPRESS 1 on bus %02x - %02x\n", |
| 192 | hose->first_busno,hose->last_busno); |
| 193 | |
| 194 | /* |
| 195 | * Activate ULI1575 legacy chip by performing a fake |
| 196 | * memory access. Needed to make ULI RTC work. |
| 197 | */ |
Becky Bruce | 49f46f3 | 2009-02-03 18:10:53 -0600 | [diff] [blame] | 198 | in_be32((unsigned *) ((char *)(CONFIG_SYS_PCI1_MEM_VIRT |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 199 | + CONFIG_SYS_PCI1_MEM_SIZE - 0x1000000))); |
Ed Swarthout | 63cec58 | 2007-08-02 14:09:49 -0500 | [diff] [blame] | 200 | |
| 201 | } else { |
| 202 | puts("PCI-EXPRESS 1: Disabled\n"); |
| 203 | } |
| 204 | } |
| 205 | #else |
| 206 | puts("PCI-EXPRESS1: Disabled\n"); |
| 207 | #endif /* CONFIG_PCI1 */ |
| 208 | |
| 209 | #ifdef CONFIG_PCI2 |
| 210 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 211 | volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR; |
Ed Swarthout | 63cec58 | 2007-08-02 14:09:49 -0500 | [diff] [blame] | 212 | struct pci_controller *hose = &pci2_hose; |
Kumar Gala | c2083e0 | 2008-10-22 14:38:55 -0500 | [diff] [blame] | 213 | struct pci_region *r = hose->regions; |
Ed Swarthout | 63cec58 | 2007-08-02 14:09:49 -0500 | [diff] [blame] | 214 | |
Ed Swarthout | 63cec58 | 2007-08-02 14:09:49 -0500 | [diff] [blame] | 215 | /* outbound memory */ |
Kumar Gala | c2083e0 | 2008-10-22 14:38:55 -0500 | [diff] [blame] | 216 | pci_set_region(r++, |
Becky Bruce | 49f46f3 | 2009-02-03 18:10:53 -0600 | [diff] [blame] | 217 | CONFIG_SYS_PCI2_MEM_BUS, |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 218 | CONFIG_SYS_PCI2_MEM_PHYS, |
| 219 | CONFIG_SYS_PCI2_MEM_SIZE, |
Ed Swarthout | 63cec58 | 2007-08-02 14:09:49 -0500 | [diff] [blame] | 220 | PCI_REGION_MEM); |
| 221 | |
| 222 | /* outbound io */ |
Kumar Gala | c2083e0 | 2008-10-22 14:38:55 -0500 | [diff] [blame] | 223 | pci_set_region(r++, |
Becky Bruce | 49f46f3 | 2009-02-03 18:10:53 -0600 | [diff] [blame] | 224 | CONFIG_SYS_PCI2_IO_BUS, |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 225 | CONFIG_SYS_PCI2_IO_PHYS, |
| 226 | CONFIG_SYS_PCI2_IO_SIZE, |
Ed Swarthout | 63cec58 | 2007-08-02 14:09:49 -0500 | [diff] [blame] | 227 | PCI_REGION_IO); |
| 228 | |
Becky Bruce | 2ecca34 | 2009-02-03 18:10:49 -0600 | [diff] [blame] | 229 | /* inbound */ |
| 230 | r += fsl_pci_setup_inbound_windows(r); |
| 231 | |
Kumar Gala | c2083e0 | 2008-10-22 14:38:55 -0500 | [diff] [blame] | 232 | hose->region_count = r - hose->regions; |
Ed Swarthout | 63cec58 | 2007-08-02 14:09:49 -0500 | [diff] [blame] | 233 | |
| 234 | hose->first_busno=first_free_busno; |
| 235 | pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); |
| 236 | |
| 237 | fsl_pci_init(hose); |
| 238 | |
| 239 | first_free_busno=hose->last_busno+1; |
| 240 | printf (" PCI-EXPRESS 2 on bus %02x - %02x\n", |
| 241 | hose->first_busno,hose->last_busno); |
| 242 | } |
| 243 | #else |
| 244 | puts("PCI-EXPRESS 2: Disabled\n"); |
| 245 | #endif /* CONFIG_PCI2 */ |
| 246 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 247 | } |
| 248 | |
Jon Loeliger | 13f5433 | 2008-02-18 14:01:56 -0600 | [diff] [blame] | 249 | |
Jon Loeliger | ea9f739 | 2007-11-28 14:47:18 -0600 | [diff] [blame] | 250 | #if defined(CONFIG_OF_BOARD_SETUP) |
Kumar Gala | c2083e0 | 2008-10-22 14:38:55 -0500 | [diff] [blame] | 251 | extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, |
Wolfgang Denk | 3cbd823 | 2008-11-02 16:14:22 +0100 | [diff] [blame] | 252 | struct pci_controller *hose); |
Jon Loeliger | 13f5433 | 2008-02-18 14:01:56 -0600 | [diff] [blame] | 253 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 254 | void |
| 255 | ft_board_setup(void *blob, bd_t *bd) |
| 256 | { |
Becky Bruce | d52082b | 2008-11-07 13:46:19 -0600 | [diff] [blame] | 257 | int off; |
| 258 | u64 *tmp; |
| 259 | u32 *addrcells; |
| 260 | |
Jon Loeliger | 13f5433 | 2008-02-18 14:01:56 -0600 | [diff] [blame] | 261 | ft_cpu_setup(blob, bd); |
Jon Loeliger | ea9f739 | 2007-11-28 14:47:18 -0600 | [diff] [blame] | 262 | |
Ed Swarthout | f75e89e | 2007-08-30 01:58:48 -0500 | [diff] [blame] | 263 | #ifdef CONFIG_PCI1 |
Kumar Gala | c2083e0 | 2008-10-22 14:38:55 -0500 | [diff] [blame] | 264 | ft_fsl_pci_setup(blob, "pci0", &pci1_hose); |
Ed Swarthout | f75e89e | 2007-08-30 01:58:48 -0500 | [diff] [blame] | 265 | #endif |
| 266 | #ifdef CONFIG_PCI2 |
Kumar Gala | c2083e0 | 2008-10-22 14:38:55 -0500 | [diff] [blame] | 267 | ft_fsl_pci_setup(blob, "pci1", &pci2_hose); |
Ed Swarthout | f75e89e | 2007-08-30 01:58:48 -0500 | [diff] [blame] | 268 | #endif |
Becky Bruce | d52082b | 2008-11-07 13:46:19 -0600 | [diff] [blame] | 269 | |
| 270 | /* |
| 271 | * Warn if it looks like the device tree doesn't match u-boot. |
| 272 | * This is just an estimation, based on the location of CCSR, |
| 273 | * which is defined by the "reg" property in the soc node. |
| 274 | */ |
| 275 | off = fdt_path_offset(blob, "/soc8641"); |
| 276 | addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL); |
| 277 | tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL); |
| 278 | |
| 279 | if (tmp) { |
| 280 | u64 addr; |
Becky Bruce | 3f510db | 2008-11-10 19:45:35 -0600 | [diff] [blame] | 281 | if (addrcells && (*addrcells == 1)) |
Becky Bruce | d52082b | 2008-11-07 13:46:19 -0600 | [diff] [blame] | 282 | addr = *(u32 *)tmp; |
Becky Bruce | 3f510db | 2008-11-10 19:45:35 -0600 | [diff] [blame] | 283 | else |
| 284 | addr = *tmp; |
Becky Bruce | d52082b | 2008-11-07 13:46:19 -0600 | [diff] [blame] | 285 | |
| 286 | if (addr != CONFIG_SYS_CCSRBAR_PHYS) |
| 287 | printf("WARNING: The CCSRBAR address in your .dts " |
| 288 | "does not match the address of the CCSR " |
| 289 | "in u-boot. This means your .dts might " |
| 290 | "be old.\n"); |
| 291 | } |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 292 | } |
| 293 | #endif |
| 294 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 295 | |
Haiying Wang | 239db37 | 2006-07-28 12:41:18 -0400 | [diff] [blame] | 296 | /* |
| 297 | * get_board_sys_clk |
| 298 | * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ |
| 299 | */ |
| 300 | |
Jon Loeliger | 80e955c | 2006-08-22 12:25:27 -0500 | [diff] [blame] | 301 | unsigned long |
| 302 | get_board_sys_clk(ulong dummy) |
Haiying Wang | 239db37 | 2006-07-28 12:41:18 -0400 | [diff] [blame] | 303 | { |
| 304 | u8 i, go_bit, rd_clks; |
| 305 | ulong val = 0; |
| 306 | |
| 307 | go_bit = in8(PIXIS_BASE + PIXIS_VCTL); |
| 308 | go_bit &= 0x01; |
| 309 | |
| 310 | rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0); |
| 311 | rd_clks &= 0x1C; |
| 312 | |
| 313 | /* |
| 314 | * Only if both go bit and the SCLK bit in VCFGEN0 are set |
| 315 | * should we be using the AUX register. Remember, we also set the |
| 316 | * GO bit to boot from the alternate bank on the on-board flash |
| 317 | */ |
| 318 | |
| 319 | if (go_bit) { |
| 320 | if (rd_clks == 0x1c) |
| 321 | i = in8(PIXIS_BASE + PIXIS_AUX); |
| 322 | else |
| 323 | i = in8(PIXIS_BASE + PIXIS_SPD); |
| 324 | } else { |
| 325 | i = in8(PIXIS_BASE + PIXIS_SPD); |
| 326 | } |
| 327 | |
| 328 | i &= 0x07; |
| 329 | |
| 330 | switch (i) { |
| 331 | case 0: |
| 332 | val = 33000000; |
| 333 | break; |
| 334 | case 1: |
| 335 | val = 40000000; |
| 336 | break; |
| 337 | case 2: |
| 338 | val = 50000000; |
| 339 | break; |
| 340 | case 3: |
| 341 | val = 66000000; |
| 342 | break; |
| 343 | case 4: |
| 344 | val = 83000000; |
| 345 | break; |
| 346 | case 5: |
| 347 | val = 100000000; |
| 348 | break; |
| 349 | case 6: |
| 350 | val = 134000000; |
| 351 | break; |
| 352 | case 7: |
| 353 | val = 166000000; |
| 354 | break; |
| 355 | } |
| 356 | |
| 357 | return val; |
| 358 | } |
Ben Warren | 0b252f5 | 2008-08-31 21:41:08 -0700 | [diff] [blame] | 359 | |
| 360 | int board_eth_init(bd_t *bis) |
| 361 | { |
| 362 | /* Initialize TSECs */ |
| 363 | cpu_eth_init(bis); |
| 364 | return pci_eth_init(bis); |
| 365 | } |
Peter Tyser | 4ef630d | 2009-02-05 11:25:25 -0600 | [diff] [blame^] | 366 | |
| 367 | void board_reset(void) |
| 368 | { |
| 369 | out8(PIXIS_BASE + PIXIS_RST, 0); |
| 370 | |
| 371 | while (1) |
| 372 | ; |
| 373 | } |