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Jon Loeligerdebb7352006-04-26 17:58:56 -05001/*
Haiying Wang3d98b852007-01-22 12:37:30 -06002 * Copyright 2006, 2007 Freescale Semiconductor.
Jon Loeligerdebb7352006-04-26 17:58:56 -05003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Ed Swarthout63cec582007-08-02 14:09:49 -050014 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Jon Loeligerdebb7352006-04-26 17:58:56 -050015 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <common.h>
24#include <pci.h>
25#include <asm/processor.h>
26#include <asm/immap_86xx.h>
Ed Swarthout63cec582007-08-02 14:09:49 -050027#include <asm/immap_fsl_pci.h>
Kumar Gala6a8e5692008-08-26 15:01:35 -050028#include <asm/fsl_ddr_sdram.h>
Haiying Wang3d98b852007-01-22 12:37:30 -060029#include <asm/io.h>
Jon Loeligerea9f7392007-11-28 14:47:18 -060030#include <libfdt.h>
31#include <fdt_support.h>
Ben Warren0b252f52008-08-31 21:41:08 -070032#include <netdev.h>
Jon Loeligerdebb7352006-04-26 17:58:56 -050033
Jon Loeliger4ce91772007-08-15 12:20:40 -050034#include "../common/pixis.h"
Jon Loeliger4d3d7292006-05-31 11:24:28 -050035
Becky Bruce4c77de32008-10-31 17:13:32 -050036phys_size_t fixed_sdram(void);
Jon Loeligerdebb7352006-04-26 17:58:56 -050037
Jon Loeliger80e955c2006-08-22 12:25:27 -050038int board_early_init_f(void)
Jon Loeligerdebb7352006-04-26 17:58:56 -050039{
Jon Loeligercb5965f2006-05-31 12:44:44 -050040 return 0;
Jon Loeligerdebb7352006-04-26 17:58:56 -050041}
42
Jon Loeliger80e955c2006-08-22 12:25:27 -050043int checkboard(void)
Jon Loeligerdebb7352006-04-26 17:58:56 -050044{
Wolfgang Denk9b55a252008-07-11 01:16:00 +020045 printf ("Board: MPC8641HPCN, System ID: 0x%02x, "
46 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
Kumar Gala7de8c212008-06-19 01:45:27 -050047 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
48 in8(PIXIS_BASE + PIXIS_PVER));
Jon Loeligerdebb7352006-04-26 17:58:56 -050049 return 0;
50}
51
52
Becky Bruce9973e3c2008-06-09 16:03:40 -050053phys_size_t
Jon Loeligerdebb7352006-04-26 17:58:56 -050054initdram(int board_type)
55{
Becky Bruce4c77de32008-10-31 17:13:32 -050056 phys_size_t dram_size = 0;
Jon Loeligerdebb7352006-04-26 17:58:56 -050057
58#if defined(CONFIG_SPD_EEPROM)
Kumar Gala6a8e5692008-08-26 15:01:35 -050059 dram_size = fsl_ddr_sdram();
Jon Loeligerdebb7352006-04-26 17:58:56 -050060#else
Jon Loeliger80e955c2006-08-22 12:25:27 -050061 dram_size = fixed_sdram();
Jon Loeligerdebb7352006-04-26 17:58:56 -050062#endif
63
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064#if defined(CONFIG_SYS_RAMBOOT)
Jon Loeligerdebb7352006-04-26 17:58:56 -050065 puts(" DDR: ");
66 return dram_size;
67#endif
Jon Loeligercb5965f2006-05-31 12:44:44 -050068
Jon Loeligerdebb7352006-04-26 17:58:56 -050069 puts(" DDR: ");
70 return dram_size;
71}
72
73
Jon Loeligerdebb7352006-04-26 17:58:56 -050074#if !defined(CONFIG_SPD_EEPROM)
Jon Loeliger5c9efb32006-04-27 10:15:16 -050075/*
76 * Fixed sdram init -- doesn't use serial presence detect.
77 */
Becky Bruce4c77de32008-10-31 17:13:32 -050078phys_size_t
Jon Loeliger80e955c2006-08-22 12:25:27 -050079fixed_sdram(void)
Jon Loeligerdebb7352006-04-26 17:58:56 -050080{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#if !defined(CONFIG_SYS_RAMBOOT)
82 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
Jon Loeliger80e955c2006-08-22 12:25:27 -050083 volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
Jon Loeligerdebb7352006-04-26 17:58:56 -050084
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
86 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
87 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
88 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
89 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
90 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
91 ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1;
92 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
93 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
94 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
95 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
96 ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL;
97 ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS;
Jon Loeligerdebb7352006-04-26 17:58:56 -050098
99#if defined (CONFIG_DDR_ECC)
100 ddr->err_disable = 0x0000008D;
101 ddr->err_sbe = 0x00ff0000;
102#endif
103 asm("sync;isync");
Jon Loeligercb5965f2006-05-31 12:44:44 -0500104
Jon Loeligerdebb7352006-04-26 17:58:56 -0500105 udelay(500);
106
107#if defined (CONFIG_DDR_ECC)
108 /* Enable ECC checking */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109 ddr->sdram_cfg_1 = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
Jon Loeligerdebb7352006-04-26 17:58:56 -0500110#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111 ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CONTROL;
112 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
Jon Loeligerdebb7352006-04-26 17:58:56 -0500113#endif
114 asm("sync; isync");
Jon Loeligercb5965f2006-05-31 12:44:44 -0500115
Jon Loeligerdebb7352006-04-26 17:58:56 -0500116 udelay(500);
117#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
Jon Loeligerdebb7352006-04-26 17:58:56 -0500119}
120#endif /* !defined(CONFIG_SPD_EEPROM) */
121
122
123#if defined(CONFIG_PCI)
Becky Bruce98693b82008-10-31 17:14:00 -0500124static struct pci_controller pci1_hose;
Jon Loeliger80e955c2006-08-22 12:25:27 -0500125#endif /* CONFIG_PCI */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500126
Ed Swarthout63cec582007-08-02 14:09:49 -0500127#ifdef CONFIG_PCI2
128static struct pci_controller pci2_hose;
129#endif /* CONFIG_PCI2 */
130
131int first_free_busno = 0;
132
Kumar Galac2083e02008-10-22 14:38:55 -0500133extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
134extern void fsl_pci_init(struct pci_controller *hose);
Ed Swarthout63cec582007-08-02 14:09:49 -0500135
Jon Loeliger80e955c2006-08-22 12:25:27 -0500136void pci_init_board(void)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500137{
Ed Swarthout63cec582007-08-02 14:09:49 -0500138#ifdef CONFIG_PCI1
139{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
Ed Swarthout63cec582007-08-02 14:09:49 -0500141 struct pci_controller *hose = &pci1_hose;
Kumar Galac2083e02008-10-22 14:38:55 -0500142 struct pci_region *r = hose->regions;
Becky Bruceaf5d1002008-10-31 17:14:14 -0500143 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
144 volatile ccsr_gur_t *gur = &immap->im_gur;
145 uint devdisr = gur->devdisr;
146 uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
147 >> MPC8641_PORDEVSR_IO_SEL_SHIFT;
Kumar Galac2083e02008-10-22 14:38:55 -0500148
Ed Swarthout63cec582007-08-02 14:09:49 -0500149#ifdef DEBUG
Jon Loeligera551cee2008-02-20 14:22:26 -0600150 uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
151 >> MPC8641_PORBMSR_HA_SHIFT;
Ed Swarthout63cec582007-08-02 14:09:49 -0500152 uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
153#endif
154 if ((io_sel == 2 || io_sel == 3 || io_sel == 5
155 || io_sel == 6 || io_sel == 7 || io_sel == 0xF)
156 && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
157 debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
158 debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det);
159 if (pci->pme_msg_det) {
160 pci->pme_msg_det = 0xffffffff;
161 debug(" with errors. Clearing. Now 0x%08x",
162 pci->pme_msg_det);
163 }
164 debug("\n");
165
Ed Swarthout63cec582007-08-02 14:09:49 -0500166 /* outbound memory */
Kumar Galac2083e02008-10-22 14:38:55 -0500167 pci_set_region(r++,
Becky Bruce49f46f32009-02-03 18:10:53 -0600168 CONFIG_SYS_PCI1_MEM_BUS,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169 CONFIG_SYS_PCI1_MEM_PHYS,
170 CONFIG_SYS_PCI1_MEM_SIZE,
Ed Swarthout63cec582007-08-02 14:09:49 -0500171 PCI_REGION_MEM);
172
173 /* outbound io */
Kumar Galac2083e02008-10-22 14:38:55 -0500174 pci_set_region(r++,
Becky Bruce49f46f32009-02-03 18:10:53 -0600175 CONFIG_SYS_PCI1_IO_BUS,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176 CONFIG_SYS_PCI1_IO_PHYS,
177 CONFIG_SYS_PCI1_IO_SIZE,
Ed Swarthout63cec582007-08-02 14:09:49 -0500178 PCI_REGION_IO);
179
Becky Bruce2ecca342009-02-03 18:10:49 -0600180 /* inbound */
181 r += fsl_pci_setup_inbound_windows(r);
182
Kumar Galac2083e02008-10-22 14:38:55 -0500183 hose->region_count = r - hose->regions;
Ed Swarthout63cec582007-08-02 14:09:49 -0500184
185 hose->first_busno=first_free_busno;
186 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
187
188 fsl_pci_init(hose);
189
190 first_free_busno=hose->last_busno+1;
191 printf (" PCI-EXPRESS 1 on bus %02x - %02x\n",
192 hose->first_busno,hose->last_busno);
193
194 /*
195 * Activate ULI1575 legacy chip by performing a fake
196 * memory access. Needed to make ULI RTC work.
197 */
Becky Bruce49f46f32009-02-03 18:10:53 -0600198 in_be32((unsigned *) ((char *)(CONFIG_SYS_PCI1_MEM_VIRT
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199 + CONFIG_SYS_PCI1_MEM_SIZE - 0x1000000)));
Ed Swarthout63cec582007-08-02 14:09:49 -0500200
201 } else {
202 puts("PCI-EXPRESS 1: Disabled\n");
203 }
204}
205#else
206 puts("PCI-EXPRESS1: Disabled\n");
207#endif /* CONFIG_PCI1 */
208
209#ifdef CONFIG_PCI2
210{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
Ed Swarthout63cec582007-08-02 14:09:49 -0500212 struct pci_controller *hose = &pci2_hose;
Kumar Galac2083e02008-10-22 14:38:55 -0500213 struct pci_region *r = hose->regions;
Ed Swarthout63cec582007-08-02 14:09:49 -0500214
Ed Swarthout63cec582007-08-02 14:09:49 -0500215 /* outbound memory */
Kumar Galac2083e02008-10-22 14:38:55 -0500216 pci_set_region(r++,
Becky Bruce49f46f32009-02-03 18:10:53 -0600217 CONFIG_SYS_PCI2_MEM_BUS,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218 CONFIG_SYS_PCI2_MEM_PHYS,
219 CONFIG_SYS_PCI2_MEM_SIZE,
Ed Swarthout63cec582007-08-02 14:09:49 -0500220 PCI_REGION_MEM);
221
222 /* outbound io */
Kumar Galac2083e02008-10-22 14:38:55 -0500223 pci_set_region(r++,
Becky Bruce49f46f32009-02-03 18:10:53 -0600224 CONFIG_SYS_PCI2_IO_BUS,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225 CONFIG_SYS_PCI2_IO_PHYS,
226 CONFIG_SYS_PCI2_IO_SIZE,
Ed Swarthout63cec582007-08-02 14:09:49 -0500227 PCI_REGION_IO);
228
Becky Bruce2ecca342009-02-03 18:10:49 -0600229 /* inbound */
230 r += fsl_pci_setup_inbound_windows(r);
231
Kumar Galac2083e02008-10-22 14:38:55 -0500232 hose->region_count = r - hose->regions;
Ed Swarthout63cec582007-08-02 14:09:49 -0500233
234 hose->first_busno=first_free_busno;
235 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
236
237 fsl_pci_init(hose);
238
239 first_free_busno=hose->last_busno+1;
240 printf (" PCI-EXPRESS 2 on bus %02x - %02x\n",
241 hose->first_busno,hose->last_busno);
242}
243#else
244 puts("PCI-EXPRESS 2: Disabled\n");
245#endif /* CONFIG_PCI2 */
246
Jon Loeligerdebb7352006-04-26 17:58:56 -0500247}
248
Jon Loeliger13f54332008-02-18 14:01:56 -0600249
Jon Loeligerea9f7392007-11-28 14:47:18 -0600250#if defined(CONFIG_OF_BOARD_SETUP)
Kumar Galac2083e02008-10-22 14:38:55 -0500251extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100252 struct pci_controller *hose);
Jon Loeliger13f54332008-02-18 14:01:56 -0600253
Jon Loeligerdebb7352006-04-26 17:58:56 -0500254void
255ft_board_setup(void *blob, bd_t *bd)
256{
Becky Bruced52082b2008-11-07 13:46:19 -0600257 int off;
258 u64 *tmp;
259 u32 *addrcells;
260
Jon Loeliger13f54332008-02-18 14:01:56 -0600261 ft_cpu_setup(blob, bd);
Jon Loeligerea9f7392007-11-28 14:47:18 -0600262
Ed Swarthoutf75e89e2007-08-30 01:58:48 -0500263#ifdef CONFIG_PCI1
Kumar Galac2083e02008-10-22 14:38:55 -0500264 ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
Ed Swarthoutf75e89e2007-08-30 01:58:48 -0500265#endif
266#ifdef CONFIG_PCI2
Kumar Galac2083e02008-10-22 14:38:55 -0500267 ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
Ed Swarthoutf75e89e2007-08-30 01:58:48 -0500268#endif
Becky Bruced52082b2008-11-07 13:46:19 -0600269
270 /*
271 * Warn if it looks like the device tree doesn't match u-boot.
272 * This is just an estimation, based on the location of CCSR,
273 * which is defined by the "reg" property in the soc node.
274 */
275 off = fdt_path_offset(blob, "/soc8641");
276 addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL);
277 tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL);
278
279 if (tmp) {
280 u64 addr;
Becky Bruce3f510db2008-11-10 19:45:35 -0600281 if (addrcells && (*addrcells == 1))
Becky Bruced52082b2008-11-07 13:46:19 -0600282 addr = *(u32 *)tmp;
Becky Bruce3f510db2008-11-10 19:45:35 -0600283 else
284 addr = *tmp;
Becky Bruced52082b2008-11-07 13:46:19 -0600285
286 if (addr != CONFIG_SYS_CCSRBAR_PHYS)
287 printf("WARNING: The CCSRBAR address in your .dts "
288 "does not match the address of the CCSR "
289 "in u-boot. This means your .dts might "
290 "be old.\n");
291 }
Jon Loeligerdebb7352006-04-26 17:58:56 -0500292}
293#endif
294
Jon Loeligerdebb7352006-04-26 17:58:56 -0500295
Haiying Wang239db372006-07-28 12:41:18 -0400296/*
297 * get_board_sys_clk
298 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
299 */
300
Jon Loeliger80e955c2006-08-22 12:25:27 -0500301unsigned long
302get_board_sys_clk(ulong dummy)
Haiying Wang239db372006-07-28 12:41:18 -0400303{
304 u8 i, go_bit, rd_clks;
305 ulong val = 0;
306
307 go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
308 go_bit &= 0x01;
309
310 rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
311 rd_clks &= 0x1C;
312
313 /*
314 * Only if both go bit and the SCLK bit in VCFGEN0 are set
315 * should we be using the AUX register. Remember, we also set the
316 * GO bit to boot from the alternate bank on the on-board flash
317 */
318
319 if (go_bit) {
320 if (rd_clks == 0x1c)
321 i = in8(PIXIS_BASE + PIXIS_AUX);
322 else
323 i = in8(PIXIS_BASE + PIXIS_SPD);
324 } else {
325 i = in8(PIXIS_BASE + PIXIS_SPD);
326 }
327
328 i &= 0x07;
329
330 switch (i) {
331 case 0:
332 val = 33000000;
333 break;
334 case 1:
335 val = 40000000;
336 break;
337 case 2:
338 val = 50000000;
339 break;
340 case 3:
341 val = 66000000;
342 break;
343 case 4:
344 val = 83000000;
345 break;
346 case 5:
347 val = 100000000;
348 break;
349 case 6:
350 val = 134000000;
351 break;
352 case 7:
353 val = 166000000;
354 break;
355 }
356
357 return val;
358}
Ben Warren0b252f52008-08-31 21:41:08 -0700359
360int board_eth_init(bd_t *bis)
361{
362 /* Initialize TSECs */
363 cpu_eth_init(bis);
364 return pci_eth_init(bis);
365}
Peter Tyser4ef630d2009-02-05 11:25:25 -0600366
367void board_reset(void)
368{
369 out8(PIXIS_BASE + PIXIS_RST, 0);
370
371 while (1)
372 ;
373}