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Paul Gortmaker91e25762007-01-16 11:38:14 -05001/*
2 * sbc8349.c -- WindRiver SBC8349 board support.
3 * Copyright (c) 2006-2007 Wind River Systems, Inc.
4 *
5 * Paul Gortmaker <paul.gortmaker@windriver.com>
6 * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 *
26 */
27
28#include <common.h>
29#include <ioports.h>
30#include <mpc83xx.h>
31#include <asm/mpc8349_pci.h>
32#include <i2c.h>
Paul Gortmaker91e25762007-01-16 11:38:14 -050033#include <spd_sdram.h>
Jon Loeligera30a5492008-03-04 10:03:03 -060034#include <miiphy.h>
Kim Phillipsb3458d22007-12-20 15:57:28 -060035#if defined(CONFIG_OF_LIBFDT)
Paul Gortmaker2408b3f2007-12-20 12:58:16 -050036#include <libfdt.h>
Paul Gortmaker91e25762007-01-16 11:38:14 -050037#endif
38
39int fixed_sdram(void);
40void sdram_init(void);
41
Peter Tyser0f898602009-05-22 17:23:24 -050042#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
Paul Gortmaker91e25762007-01-16 11:38:14 -050043void ddr_enable_ecc(unsigned int dram_size);
44#endif
45
46#ifdef CONFIG_BOARD_EARLY_INIT_F
47int board_early_init_f (void)
48{
49 return 0;
50}
51#endif
52
53#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
54
Becky Bruce9973e3c2008-06-09 16:03:40 -050055phys_size_t initdram (int board_type)
Paul Gortmaker91e25762007-01-16 11:38:14 -050056{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
Paul Gortmaker91e25762007-01-16 11:38:14 -050058 u32 msize = 0;
59
60 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
61 return -1;
62
Paul Gortmaker91e25762007-01-16 11:38:14 -050063 /* DDR SDRAM - Main SODIMM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
Paul Gortmaker91e25762007-01-16 11:38:14 -050065#if defined(CONFIG_SPD_EEPROM)
66 msize = spd_sdram();
67#else
68 msize = fixed_sdram();
69#endif
70 /*
71 * Initialize SDRAM if it is on local bus.
72 */
73 sdram_init();
74
75#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
76 /*
77 * Initialize and enable DDR ECC.
78 */
79 ddr_enable_ecc(msize * 1024 * 1024);
80#endif
Paul Gortmaker91e25762007-01-16 11:38:14 -050081 /* return total bus SDRAM size(bytes) -- DDR */
82 return (msize * 1024 * 1024);
83}
84
85#if !defined(CONFIG_SPD_EEPROM)
86/*************************************************************************
87 * fixed sdram init -- doesn't use serial presence detect.
88 ************************************************************************/
89int fixed_sdram(void)
90{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
Paul Gortmaker91e25762007-01-16 11:38:14 -050092 u32 msize = 0;
93 u32 ddr_size;
94 u32 ddr_size_log2;
95
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096 msize = CONFIG_SYS_DDR_SIZE;
Paul Gortmaker91e25762007-01-16 11:38:14 -050097 for (ddr_size = msize << 20, ddr_size_log2 = 0;
98 (ddr_size > 1);
99 ddr_size = ddr_size>>1, ddr_size_log2++) {
100 if (ddr_size & 1) {
101 return -1;
102 }
103 }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
Paul Gortmaker91e25762007-01-16 11:38:14 -0500105 im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
106
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#if (CONFIG_SYS_DDR_SIZE != 256)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500108#warning Currently any ddr size other than 256 is not supported
109#endif
110 im->ddr.csbnds[2].csbnds = 0x0000000f;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111 im->ddr.cs_config[2] = CONFIG_SYS_DDR_CONFIG;
Paul Gortmaker91e25762007-01-16 11:38:14 -0500112
113 /* currently we use only one CS, so disable the other banks */
114 im->ddr.cs_config[0] = 0;
115 im->ddr.cs_config[1] = 0;
116 im->ddr.cs_config[3] = 0;
117
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
119 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
Paul Gortmaker91e25762007-01-16 11:38:14 -0500120
121 im->ddr.sdram_cfg =
122 SDRAM_CFG_SREN
123#if defined(CONFIG_DDR_2T_TIMING)
124 | SDRAM_CFG_2T_EN
125#endif
Kim Phillipsbbea46f2007-08-16 22:52:48 -0500126 | SDRAM_CFG_SDRAM_TYPE_DDR1;
Paul Gortmaker91e25762007-01-16 11:38:14 -0500127#if defined (CONFIG_DDR_32BIT)
128 /* for 32-bit mode burst length is 8 */
129 im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
130#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
Paul Gortmaker91e25762007-01-16 11:38:14 -0500132
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
Paul Gortmaker91e25762007-01-16 11:38:14 -0500134 udelay(200);
135
136 /* enable DDR controller */
137 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
138 return msize;
139}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#endif/*!CONFIG_SYS_SPD_EEPROM*/
Paul Gortmaker91e25762007-01-16 11:38:14 -0500141
142
143int checkboard (void)
144{
145 puts("Board: Wind River SBC834x\n");
146 return 0;
147}
148
149/*
150 * if board is fitted with SDRAM
151 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#if defined(CONFIG_SYS_BR2_PRELIM) \
153 && defined(CONFIG_SYS_OR2_PRELIM) \
154 && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
155 && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500156/*
157 * Initialize SDRAM memory on the Local Bus.
158 */
159
160void sdram_init(void)
161{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
Becky Brucef51cdaf2010-06-17 11:37:20 -0500163 volatile fsl_lbc_t *lbc = &immap->im_lbc;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
Paul Gortmaker91e25762007-01-16 11:38:14 -0500165
166 puts("\n SDRAM on Local Bus: ");
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
Paul Gortmaker91e25762007-01-16 11:38:14 -0500168
169 /*
170 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
171 */
172
173 /* setup mtrpt, lsrt and lbcr for LB bus */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
175 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
176 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
Paul Gortmaker91e25762007-01-16 11:38:14 -0500177 asm("sync");
178
179 /*
180 * Configure the SDRAM controller Machine Mode Register.
181 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500183
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500185 asm("sync");
186 *sdram_addr = 0xff;
187 udelay(100);
188
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500190 asm("sync");
191 /*1 times*/
192 *sdram_addr = 0xff;
193 udelay(100);
194 /*2 times*/
195 *sdram_addr = 0xff;
196 udelay(100);
197 /*3 times*/
198 *sdram_addr = 0xff;
199 udelay(100);
200 /*4 times*/
201 *sdram_addr = 0xff;
202 udelay(100);
203 /*5 times*/
204 *sdram_addr = 0xff;
205 udelay(100);
206 /*6 times*/
207 *sdram_addr = 0xff;
208 udelay(100);
209 /*7 times*/
210 *sdram_addr = 0xff;
211 udelay(100);
212 /*8 times*/
213 *sdram_addr = 0xff;
214 udelay(100);
215
216 /* 0x58636733; mode register write operation */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
Paul Gortmaker91e25762007-01-16 11:38:14 -0500218 asm("sync");
219 *sdram_addr = 0xff;
220 udelay(100);
221
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500223 asm("sync");
224 *sdram_addr = 0xff;
225 udelay(100);
226}
227#else
228void sdram_init(void)
229{
230 puts(" SDRAM on Local Bus: Disabled in config\n");
231}
232#endif
233
Paul Gortmaker2408b3f2007-12-20 12:58:16 -0500234#if defined(CONFIG_OF_BOARD_SETUP)
235void ft_board_setup(void *blob, bd_t *bd)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500236{
Paul Gortmaker2408b3f2007-12-20 12:58:16 -0500237 ft_cpu_setup(blob, bd);
238#ifdef CONFIG_PCI
239 ft_pci_setup(blob, bd);
240#endif
Paul Gortmaker91e25762007-01-16 11:38:14 -0500241}
242#endif