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wdenk324f6cf2002-10-07 21:13:39 +00001/*
2 * (C) Copyright 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
wdenk228f29a2002-12-08 09:53:23 +000022 *
23 * Be sure to mark tests to be run before relocation as such with the
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020024 * CONFIG_SYS_POST_PREREL flag so that logging is done correctly if the
wdenk228f29a2002-12-08 09:53:23 +000025 * logbuffer support is enabled.
wdenk324f6cf2002-10-07 21:13:39 +000026 */
27
28#include <common.h>
29
wdenk324f6cf2002-10-07 21:13:39 +000030#include <post.h>
31
Yuri Tikhonov6e8ec682008-05-08 15:42:47 +020032extern int ocm_post_test (int flags);
wdenk324f6cf2002-10-07 21:13:39 +000033extern int cache_post_test (int flags);
34extern int watchdog_post_test (int flags);
35extern int i2c_post_test (int flags);
36extern int rtc_post_test (int flags);
37extern int memory_post_test (int flags);
38extern int cpu_post_test (int flags);
Igor Lisitsina11e0692007-03-28 19:06:19 +040039extern int fpu_post_test (int flags);
wdenk324f6cf2002-10-07 21:13:39 +000040extern int uart_post_test (int flags);
41extern int ether_post_test (int flags);
42extern int spi_post_test (int flags);
43extern int usb_post_test (int flags);
44extern int spr_post_test (int flags);
wdenk4532cb62003-04-27 22:52:51 +000045extern int sysmon_post_test (int flags);
wdenk5a8c51c2004-04-15 21:16:42 +000046extern int dsp_post_test (int flags);
wdenk79fa88f2004-06-07 23:46:25 +000047extern int codec_post_test (int flags);
Pavel Kolesnikov531e3e82007-07-20 15:03:03 +020048extern int ecc_post_test (int flags);
wdenk4532cb62003-04-27 22:52:51 +000049
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +010050extern int dspic_init_post_test (int flags);
51extern int dspic_post_test (int flags);
52extern int gdc_post_test (int flags);
53extern int fpga_post_test (int flags);
54extern int lwmon5_watchdog_post_test(int flags);
55extern int sysmon1_post_test(int flags);
Anatolij Gustschin29fd7ce2010-04-24 19:27:11 +020056extern int coprocessor_post_test(int flags);
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +010057
wdenk4532cb62003-04-27 22:52:51 +000058extern int sysmon_init_f (void);
59
60extern void sysmon_reloc (void);
61
wdenk324f6cf2002-10-07 21:13:39 +000062
63struct post_test post_list[] =
64{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#if CONFIG_POST & CONFIG_SYS_POST_OCM
Yuri Tikhonov6e8ec682008-05-08 15:42:47 +020066 {
67 "OCM test",
68 "ocm",
69 "This test checks on chip memory (OCM).",
Yuri Tikhonov7845d492008-05-08 15:46:02 +020070 POST_ROM | POST_ALWAYS | POST_PREREL | POST_CRITICAL | POST_STOP,
Yuri Tikhonov6e8ec682008-05-08 15:42:47 +020071 &ocm_post_test,
72 NULL,
73 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074 CONFIG_SYS_POST_OCM
Yuri Tikhonov6e8ec682008-05-08 15:42:47 +020075 },
76#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#if CONFIG_POST & CONFIG_SYS_POST_CACHE
wdenk324f6cf2002-10-07 21:13:39 +000078 {
wdenk8bde7f72003-06-27 21:31:46 +000079 "Cache test",
80 "cache",
81 "This test verifies the CPU cache operation.",
82 POST_RAM | POST_ALWAYS,
83 &cache_post_test,
84 NULL,
85 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086 CONFIG_SYS_POST_CACHE
wdenk324f6cf2002-10-07 21:13:39 +000087 },
88#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#if CONFIG_POST & CONFIG_SYS_POST_WATCHDOG
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +010090#if defined(CONFIG_POST_WATCHDOG)
91 CONFIG_POST_WATCHDOG,
92#else
wdenk324f6cf2002-10-07 21:13:39 +000093 {
wdenk8bde7f72003-06-27 21:31:46 +000094 "Watchdog timer test",
95 "watchdog",
96 "This test checks the watchdog timer.",
wdenk8564acf2003-07-14 22:13:32 +000097 POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT,
wdenk8bde7f72003-06-27 21:31:46 +000098 &watchdog_post_test,
99 NULL,
100 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101 CONFIG_SYS_POST_WATCHDOG
wdenk324f6cf2002-10-07 21:13:39 +0000102 },
103#endif
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +0100104#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#if CONFIG_POST & CONFIG_SYS_POST_I2C
wdenk324f6cf2002-10-07 21:13:39 +0000106 {
wdenk8bde7f72003-06-27 21:31:46 +0000107 "I2C test",
108 "i2c",
109 "This test verifies the I2C operation.",
110 POST_RAM | POST_ALWAYS,
111 &i2c_post_test,
112 NULL,
113 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114 CONFIG_SYS_POST_I2C
wdenk324f6cf2002-10-07 21:13:39 +0000115 },
116#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#if CONFIG_POST & CONFIG_SYS_POST_RTC
wdenk324f6cf2002-10-07 21:13:39 +0000118 {
wdenk8bde7f72003-06-27 21:31:46 +0000119 "RTC test",
120 "rtc",
121 "This test verifies the RTC operation.",
wdenk8564acf2003-07-14 22:13:32 +0000122 POST_RAM | POST_SLOWTEST | POST_MANUAL,
wdenk8bde7f72003-06-27 21:31:46 +0000123 &rtc_post_test,
124 NULL,
125 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126 CONFIG_SYS_POST_RTC
wdenk324f6cf2002-10-07 21:13:39 +0000127 },
128#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
wdenk324f6cf2002-10-07 21:13:39 +0000130 {
wdenk8bde7f72003-06-27 21:31:46 +0000131 "Memory test",
132 "memory",
133 "This test checks RAM.",
wdenk8564acf2003-07-14 22:13:32 +0000134 POST_ROM | POST_POWERON | POST_SLOWTEST | POST_PREREL,
wdenk8bde7f72003-06-27 21:31:46 +0000135 &memory_post_test,
136 NULL,
137 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138 CONFIG_SYS_POST_MEMORY
wdenk324f6cf2002-10-07 21:13:39 +0000139 },
140#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#if CONFIG_POST & CONFIG_SYS_POST_CPU
wdenk324f6cf2002-10-07 21:13:39 +0000142 {
wdenk8bde7f72003-06-27 21:31:46 +0000143 "CPU test",
144 "cpu",
145 "This test verifies the arithmetic logic unit of"
146 " CPU.",
147 POST_RAM | POST_ALWAYS,
148 &cpu_post_test,
149 NULL,
150 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151 CONFIG_SYS_POST_CPU
wdenk324f6cf2002-10-07 21:13:39 +0000152 },
153#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#if CONFIG_POST & CONFIG_SYS_POST_FPU
Igor Lisitsina11e0692007-03-28 19:06:19 +0400155 {
156 "FPU test",
157 "fpu",
158 "This test verifies the arithmetic logic unit of"
159 " FPU.",
160 POST_RAM | POST_ALWAYS,
161 &fpu_post_test,
162 NULL,
163 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164 CONFIG_SYS_POST_FPU
Igor Lisitsina11e0692007-03-28 19:06:19 +0400165 },
166#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#if CONFIG_POST & CONFIG_SYS_POST_UART
Stefan Roese834a45d2010-10-07 14:16:25 +0200168#if defined(CONFIG_POST_UART)
169 CONFIG_POST_UART,
170#else
wdenk324f6cf2002-10-07 21:13:39 +0000171 {
wdenk8bde7f72003-06-27 21:31:46 +0000172 "UART test",
173 "uart",
174 "This test verifies the UART operation.",
wdenk8564acf2003-07-14 22:13:32 +0000175 POST_RAM | POST_SLOWTEST | POST_MANUAL,
wdenk8bde7f72003-06-27 21:31:46 +0000176 &uart_post_test,
177 NULL,
178 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179 CONFIG_SYS_POST_UART
wdenk324f6cf2002-10-07 21:13:39 +0000180 },
Stefan Roese834a45d2010-10-07 14:16:25 +0200181#endif /* CONFIG_POST_UART */
wdenk324f6cf2002-10-07 21:13:39 +0000182#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#if CONFIG_POST & CONFIG_SYS_POST_ETHER
wdenk324f6cf2002-10-07 21:13:39 +0000184 {
wdenk8bde7f72003-06-27 21:31:46 +0000185 "ETHERNET test",
186 "ethernet",
187 "This test verifies the ETHERNET operation.",
188 POST_RAM | POST_ALWAYS | POST_MANUAL,
189 &ether_post_test,
190 NULL,
191 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192 CONFIG_SYS_POST_ETHER
wdenk324f6cf2002-10-07 21:13:39 +0000193 },
194#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#if CONFIG_POST & CONFIG_SYS_POST_SPI
wdenk324f6cf2002-10-07 21:13:39 +0000196 {
wdenk8bde7f72003-06-27 21:31:46 +0000197 "SPI test",
198 "spi",
199 "This test verifies the SPI operation.",
200 POST_RAM | POST_ALWAYS | POST_MANUAL,
201 &spi_post_test,
202 NULL,
203 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204 CONFIG_SYS_POST_SPI
wdenk324f6cf2002-10-07 21:13:39 +0000205 },
206#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#if CONFIG_POST & CONFIG_SYS_POST_USB
wdenk324f6cf2002-10-07 21:13:39 +0000208 {
wdenk8bde7f72003-06-27 21:31:46 +0000209 "USB test",
210 "usb",
211 "This test verifies the USB operation.",
212 POST_RAM | POST_ALWAYS | POST_MANUAL,
213 &usb_post_test,
214 NULL,
215 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216 CONFIG_SYS_POST_USB
wdenk324f6cf2002-10-07 21:13:39 +0000217 },
218#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#if CONFIG_POST & CONFIG_SYS_POST_SPR
wdenk324f6cf2002-10-07 21:13:39 +0000220 {
wdenk8bde7f72003-06-27 21:31:46 +0000221 "SPR test",
222 "spr",
223 "This test checks SPR contents.",
Stefan Roeseb2e21422008-01-09 10:38:58 +0100224 POST_RAM | POST_ALWAYS,
wdenk8bde7f72003-06-27 21:31:46 +0000225 &spr_post_test,
226 NULL,
227 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228 CONFIG_SYS_POST_SPR
wdenk324f6cf2002-10-07 21:13:39 +0000229 },
230#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#if CONFIG_POST & CONFIG_SYS_POST_SYSMON
wdenk4532cb62003-04-27 22:52:51 +0000232 {
wdenk8bde7f72003-06-27 21:31:46 +0000233 "SYSMON test",
234 "sysmon",
235 "This test monitors system hardware.",
236 POST_RAM | POST_ALWAYS,
237 &sysmon_post_test,
238 &sysmon_init_f,
239 &sysmon_reloc,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240 CONFIG_SYS_POST_SYSMON
wdenk4532cb62003-04-27 22:52:51 +0000241 },
242#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#if CONFIG_POST & CONFIG_SYS_POST_DSP
wdenk5a8c51c2004-04-15 21:16:42 +0000244 {
245 "DSP test",
246 "dsp",
247 "This test checks any connected DSP(s).",
Sascha Laue5744ddc2008-05-30 09:48:14 +0200248 POST_RAM | POST_ALWAYS | POST_MANUAL,
wdenk5a8c51c2004-04-15 21:16:42 +0000249 &dsp_post_test,
250 NULL,
251 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252 CONFIG_SYS_POST_DSP
wdenk5a8c51c2004-04-15 21:16:42 +0000253 },
254#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#if CONFIG_POST & CONFIG_SYS_POST_CODEC
wdenk79fa88f2004-06-07 23:46:25 +0000256 {
257 "CODEC test",
258 "codec",
259 "This test checks any connected codec(s).",
260 POST_RAM | POST_MANUAL,
261 &codec_post_test,
262 NULL,
263 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264 CONFIG_SYS_POST_CODEC
wdenk79fa88f2004-06-07 23:46:25 +0000265 },
266#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#if CONFIG_POST & CONFIG_SYS_POST_ECC
Pavel Kolesnikov531e3e82007-07-20 15:03:03 +0200268 {
269 "ECC test",
270 "ecc",
Larry Johnson8dafa872008-01-12 23:35:33 -0500271 "This test checks the ECC facility of memory.",
272 POST_ROM | POST_ALWAYS | POST_PREREL,
Pavel Kolesnikov531e3e82007-07-20 15:03:03 +0200273 &ecc_post_test,
274 NULL,
275 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276 CONFIG_SYS_POST_ECC
Pavel Kolesnikov531e3e82007-07-20 15:03:03 +0200277 },
278#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +0100280 CONFIG_POST_BSPEC1,
281#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#if CONFIG_POST & CONFIG_SYS_POST_BSPEC2
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +0100283 CONFIG_POST_BSPEC2,
284#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#if CONFIG_POST & CONFIG_SYS_POST_BSPEC3
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +0100286 CONFIG_POST_BSPEC3,
287#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#if CONFIG_POST & CONFIG_SYS_POST_BSPEC4
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +0100289 CONFIG_POST_BSPEC4,
290#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#if CONFIG_POST & CONFIG_SYS_POST_BSPEC5
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +0100292 CONFIG_POST_BSPEC5,
293#endif
Anatolij Gustschin29fd7ce2010-04-24 19:27:11 +0200294#if CONFIG_POST & CONFIG_SYS_POST_COPROC
295 {
296 "Coprocessors communication test",
297 "coproc_com",
298 "This test checks communication with coprocessors.",
299 POST_RAM | POST_ALWAYS | POST_CRITICAL,
300 &coprocessor_post_test,
301 NULL,
302 NULL,
303 CONFIG_SYS_POST_COPROC
304 }
305#endif
wdenk324f6cf2002-10-07 21:13:39 +0000306};
307
308unsigned int post_list_size = sizeof (post_list) / sizeof (struct post_test);