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Dirk Eibach60083262017-02-22 16:07:23 +01001/*
2 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
3 * Copyright (C) 2016 Mario Six <mario.six@gdsys.cc>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#ifndef _CONFIG_CONTROLCENTERDC_H
9#define _CONFIG_CONTROLCENTERDC_H
10
11/*
12 * High Level Configuration Options (easy to change)
13 */
14#define CONFIG_CUSTOMER_BOARD_SUPPORT
15
16#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
Dirk Eibach60083262017-02-22 16:07:23 +010017#define CONFIG_BOARD_LATE_INIT
Dirk Eibach60083262017-02-22 16:07:23 +010018
19/*
20 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
21 * for DDR ECC byte filling in the SPL before loading the main
22 * U-Boot into it.
23 */
Dirk Eibach60083262017-02-22 16:07:23 +010024
25#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
26
27#define CONFIG_LOADADDR 1000000
28
29/*
30 * Commands configuration
31 */
Dirk Eibach60083262017-02-22 16:07:23 +010032#define CONFIG_CMD_I2C
Dirk Eibach60083262017-02-22 16:07:23 +010033#define CONFIG_CMD_SPI
34
35/* SPI NOR flash default params, used by sf commands */
36#define CONFIG_SF_DEFAULT_BUS 1
37#define CONFIG_SF_DEFAULT_SPEED 1000000
38#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
39
40/*
41 * SDIO/MMC Card Configuration
42 */
43#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE
44
45/*
46 * SATA/SCSI/AHCI configuration
47 */
Dirk Eibach60083262017-02-22 16:07:23 +010048#define CONFIG_SCSI_AHCI_PLAT
49#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
50#define CONFIG_SYS_SCSI_MAX_LUN 1
51#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
52 CONFIG_SYS_SCSI_MAX_LUN)
53
Dirk Eibach60083262017-02-22 16:07:23 +010054/* USB/EHCI configuration */
55#define CONFIG_EHCI_IS_TDI
56
57/* Environment in SPI NOR flash */
Dirk Eibach60083262017-02-22 16:07:23 +010058#define CONFIG_ENV_SPI_BUS 1
59#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
60#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
61#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
62
63#define CONFIG_PHY_MARVELL /* there is a marvell phy */
64#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
65
66/* PCIe support */
67#ifndef CONFIG_SPL_BUILD
68#define CONFIG_PCI
69#define CONFIG_PCI_MVEBU
70#define CONFIG_PCI_PNP
71#define CONFIG_PCI_SCAN_SHOW
72#endif
73
Dirk Eibach60083262017-02-22 16:07:23 +010074/*
75 * Software (bit-bang) MII driver configuration
76 */
77#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
78#define CONFIG_BITBANGMII_MULTI
79
80/* SPL */
81/*
82 * Select the boot device here
83 *
84 * Currently supported are:
85 * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash
86 * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1)
87 */
88#define SPL_BOOT_SPI_NOR_FLASH 1
89#define SPL_BOOT_SDIO_MMC_CARD 2
90#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH
91
92/* Defines for SPL */
Dirk Eibach60083262017-02-22 16:07:23 +010093#define CONFIG_SPL_SIZE (160 << 10)
94
95#if defined(CONFIG_SECURED_MODE_IMAGE)
96#define CONFIG_SPL_TEXT_BASE 0x40002614
97#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x2614)
98#else
99#define CONFIG_SPL_TEXT_BASE 0x40000030
100#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x30)
101#endif
102
103#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
104#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
105
106#ifdef CONFIG_SPL_BUILD
107#define CONFIG_SYS_MALLOC_SIMPLE
108#endif
109
110#define CONFIG_SPL_STACK (0x40000000 + ((212 - 16) << 10))
111#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
112
113#define CONFIG_SPL_LIBCOMMON_SUPPORT
114#define CONFIG_SPL_LIBGENERIC_SUPPORT
115#define CONFIG_SPL_SERIAL_SUPPORT
116#define CONFIG_SPL_I2C_SUPPORT
117
118#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
119/* SPL related SPI defines */
120#define CONFIG_SPL_SPI_LOAD
121#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x30000
122#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
123#endif
124
125#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
126/* SPL related MMC defines */
127#define CONFIG_SPL_MMC_SUPPORT
128#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
129#define CONFIG_SYS_MMC_U_BOOT_OFFS (168 << 10)
130#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS
131#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR (CONFIG_SYS_U_BOOT_OFFS / 512)
132#ifdef CONFIG_SPL_BUILD
133#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
134#endif
135#endif
136
137/*
138 * Environment Configuration
139 */
140#define CONFIG_ENV_OVERWRITE
141
142#define CONFIG_BAUDRATE 115200
143
Mario Six5bc05432018-03-28 14:38:20 +0200144#define CONFIG_HOSTNAME "ccdc"
Dirk Eibach60083262017-02-22 16:07:23 +0100145#define CONFIG_ROOTPATH "/opt/nfsroot"
146#define CONFIG_BOOTFILE "ccdc.img"
147
148#define CONFIG_PREBOOT /* enable preboot variable */
149
150#define CONFIG_EXTRA_ENV_SETTINGS \
151 "netdev=eth1\0" \
152 "consoledev=ttyS1\0" \
153 "u-boot=u-boot.bin\0" \
154 "bootfile_addr=1000000\0" \
155 "keyprogram_addr=3000000\0" \
156 "keyprogram_file=keyprogram.img\0" \
157 "fdtfile=controlcenterdc.dtb\0" \
158 "load=tftpboot ${loadaddr} ${u-boot}\0" \
159 "mmcdev=0:2\0" \
160 "update=sf probe 1:0;" \
161 " sf erase 0 +${filesize};" \
162 " sf write ${fileaddr} 0 ${filesize}\0" \
163 "upd=run load update\0" \
164 "fdt_high=0x10000000\0" \
165 "initrd_high=0x10000000\0" \
166 "loadkeyprogram=tpm flush_keys;" \
167 " mmc rescan;" \
168 " ext4load mmc ${mmcdev} ${keyprogram_addr} ${keyprogram_file};"\
169 " source ${keyprogram_addr}:script@1\0" \
170 "gpio1=gpio@22_25\0" \
171 "gpio2=A29\0" \
172 "blinkseq='0 0 0 0 2 0 2 2 3 1 3 1 0 0 2 2 3 1 3 3 2 0 2 2 3 1 1 1 " \
173 "2 0 2 2 3 1 3 1 0 0 2 0 3 3 3 1 2 0 0 0 3 1 1 1 0 0 0 0'\0" \
174 "bootfail=for i in ${blinkseq}; do" \
175 " if test $i -eq 0; then" \
176 " gpio clear ${gpio1}; gpio set ${gpio2};" \
177 " elif test $i -eq 1; then" \
178 " gpio clear ${gpio1}; gpio clear ${gpio2};" \
179 " elif test $i -eq 2; then" \
180 " gpio set ${gpio1}; gpio set ${gpio2};" \
181 " else;" \
182 " gpio clear ${gpio1}; gpio set ${gpio2};" \
183 " fi; sleep 0.12; done\0"
184
185#define CONFIG_NFSBOOTCOMMAND \
186 "setenv bootargs root=/dev/nfs rw " \
187 "nfsroot=${serverip}:${rootpath} " \
188 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off " \
189 "console=${consoledev},${baudrate} ${othbootargs}; " \
190 "tftpboot ${bootfile_addr} ${bootfile}; " \
191 "bootm ${bootfile_addr}"
192
193#define CONFIG_MMCBOOTCOMMAND \
194 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
195 "console=${consoledev},${baudrate} ${othbootargs}; " \
196 "ext2load mmc 0:2 ${bootfile_addr} ${bootfile}; " \
197 "bootm ${bootfile_addr}"
198
199#define CONFIG_BOOTCOMMAND \
200 "if env exists keyprogram; then;" \
201 " setenv keyprogram; run nfsboot;" \
202 " fi;" \
203 " run dobootfail"
204
205/*
206 * mv-common.h should be defined after CMD configs since it used them
207 * to enable certain macros
208 */
209#include "mv-common.h"
210
211#endif /* _CONFIG_CONTROLCENTERDC_H */