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Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -04001/*
Enric Balletbò i Serradc7a9e62012-03-05 11:32:16 +00002 * Common configuration settings for IGEP technology based boards
3 *
4 * (C) Copyright 2012
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -04005 * ISEE 2007 SL, <www.iseebcn.com>
6 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -04008 */
9
Enric Balletbò i Serradc7a9e62012-03-05 11:32:16 +000010#ifndef __IGEP00X0_H
11#define __IGEP00X0_H
12
Enric Balletbò i Serrae37e9542013-12-06 21:30:24 +010013#define CONFIG_NR_DRAM_BANKS 2
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040014
Enric Balletbò i Serrae37e9542013-12-06 21:30:24 +010015#include <configs/ti_omap3_common.h>
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040016
Tom Rinifa2f81b2016-08-26 13:30:43 -040017/*
18 * We are only ever GP parts and will utilize all of the "downloaded image"
19 * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB).
20 */
Enric Balletbo i Serrae7fbcbc2016-05-03 08:59:24 +020021#undef CONFIG_SPL_TEXT_BASE
Enric Balletbo i Serrae7fbcbc2016-05-03 08:59:24 +020022#define CONFIG_SPL_TEXT_BASE 0x40200000
23
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040024#define CONFIG_MISC_INIT_R
25
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040026#define CONFIG_REVISION_TAG 1
27
Pau Pajuelo195dc232017-08-17 03:09:14 +020028/* GPIO banks */
29#define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 is in GPIO bank 2 */
30#define CONFIG_OMAP3_GPIO_4 /* GPIO96..127 is in GPIO bank 4 */
31
32/* TPS65950 */
33#define PBIASLITEVMODE1 (1 << 8)
34
35/* LED */
36#define IGEP0020_GPIO_LED 27
37#define IGEP0030_GPIO_LED 16
38
39/* Board and revision detection GPIOs */
40#define IGEP0030_USB_TRANSCEIVER_RESET 54
41#define GPIO_IGEP00X0_BOARD_DETECTION 28
42#define GPIO_IGEP00X0_REVISION_DETECTION 129
Javier Martinez Canillas9d4f5422012-12-27 03:36:01 +000043
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040044/* USB device configuration */
45#define CONFIG_USB_DEVICE 1
46#define CONFIG_USB_TTY 1
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040047
48/* Change these to suit your needs */
49#define CONFIG_USBD_VENDORID 0x0451
50#define CONFIG_USBD_PRODUCTID 0x5678
51#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
52#define CONFIG_USBD_PRODUCT_NAME "IGEP"
53
Enric Balletbò i Serra40372242015-09-07 08:28:09 +020054#ifndef CONFIG_SPL_BUILD
Enric Balletbo i Serra304a46c2011-04-19 09:16:36 -040055
Enric Balletbò i Serra40372242015-09-07 08:28:09 +020056/* Environment */
57#define ENV_DEVICE_SETTINGS \
58 "stdin=serial\0" \
59 "stdout=serial\0" \
60 "stderr=serial\0"
61
62#define MEM_LAYOUT_SETTINGS \
63 DEFAULT_LINUX_BOOT_ENV \
64 "scriptaddr=0x87E00000\0" \
65 "pxefile_addr_r=0x87F00000\0"
66
67#define BOOT_TARGET_DEVICES(func) \
68 func(MMC, mmc, 0)
69
70#include <config_distro_bootcmd.h>
71
Pau Pajuelo195dc232017-08-17 03:09:14 +020072#define ENV_FINDFDT \
73 "findfdt="\
74 "if test ${board_name} = igep0020; then " \
75 "if test ${board_rev} = F; then " \
76 "setenv fdtfile omap3-igep0020-rev-f.dtb; " \
77 "else " \
78 "setenv fdtfile omap3-igep0020.dtb; fi; fi; " \
79 "if test ${board_name} = igep0030; then " \
80 "if test ${board_rev} = G; then " \
81 "setenv fdtfile omap3-igep0030-rev-g.dtb; " \
82 "else " \
83 "setenv fdtfile omap3-igep0030.dtb; fi; fi; " \
84 "if test ${fdtfile} = ''; then " \
85 "echo WARNING: Could not determine device tree to use; fi; \0"
86
Enric Balletbò i Serra40372242015-09-07 08:28:09 +020087#define CONFIG_EXTRA_ENV_SETTINGS \
Pau Pajuelo195dc232017-08-17 03:09:14 +020088 ENV_FINDFDT \
Enric Balletbò i Serra40372242015-09-07 08:28:09 +020089 ENV_DEVICE_SETTINGS \
90 MEM_LAYOUT_SETTINGS \
91 BOOTENV
92
93#endif
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040094
Ladislav Michl4b9dc7c2016-07-12 20:28:32 +020095#define CONFIG_MTD_PARTITIONS
Ladislav Michla5debaa2016-07-12 20:28:33 +020096#define CONFIG_SYS_MTDPARTS_RUNTIME
Ladislav Michl4b9dc7c2016-07-12 20:28:32 +020097
98/* OneNAND config */
Ladislav Michl4b9dc7c2016-07-12 20:28:32 +020099#define CONFIG_USE_ONENAND_BOARD_INIT
100#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
101#define CONFIG_SYS_ONENAND_BLOCK_SIZE (128*1024)
Javier Martinez Canillasd271a612012-07-28 01:19:34 +0000102
Ladislav Michl4b9dc7c2016-07-12 20:28:32 +0200103/* NAND config */
Javier Martinez Canillasd271a612012-07-28 01:19:34 +0000104#define CONFIG_SYS_NAND_5_ADDR_CYCLE
105#define CONFIG_SYS_NAND_PAGE_COUNT 64
106#define CONFIG_SYS_NAND_PAGE_SIZE 2048
107#define CONFIG_SYS_NAND_OOBSIZE 64
108#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
Ladislav Michl81fd8582015-10-12 18:09:14 +0200109#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
110#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
111 10, 11, 12, 13, 14, 15, 16, 17, \
112 18, 19, 20, 21, 22, 23, 24, 25, \
113 26, 27, 28, 29, 30, 31, 32, 33, \
114 34, 35, 36, 37, 38, 39, 40, 41, \
115 42, 43, 44, 45, 46, 47, 48, 49, \
116 50, 51, 52, 53, 54, 55, 56, 57, }
Javier Martinez Canillasd271a612012-07-28 01:19:34 +0000117#define CONFIG_SYS_NAND_ECCSIZE 512
Ladislav Michl81fd8582015-10-12 18:09:14 +0200118#define CONFIG_SYS_NAND_ECCBYTES 14
119#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
Ladislav Michl81fd8582015-10-12 18:09:14 +0200120
Ladislav Michl4b9dc7c2016-07-12 20:28:32 +0200121/* UBI configuration */
122#define CONFIG_SPL_UBI 1
123#define CONFIG_SPL_UBI_MAX_VOL_LEBS 256
124#define CONFIG_SPL_UBI_MAX_PEB_SIZE (256*1024)
125#define CONFIG_SPL_UBI_MAX_PEBS 4096
126#define CONFIG_SPL_UBI_VOL_IDS 8
127#define CONFIG_SPL_UBI_LOAD_MONITOR_ID 0
128#define CONFIG_SPL_UBI_LOAD_KERNEL_ID 3
129#define CONFIG_SPL_UBI_LOAD_ARGS_ID 4
130#define CONFIG_SPL_UBI_PEB_OFFSET 4
131#define CONFIG_SPL_UBI_VID_OFFSET 512
132#define CONFIG_SPL_UBI_LEB_START 2048
133#define CONFIG_SPL_UBI_INFO_ADDR 0x88080000
134
135/* environment organization */
Ladislav Michl4b9dc7c2016-07-12 20:28:32 +0200136#define CONFIG_ENV_UBI_PART "UBI"
137#define CONFIG_ENV_UBI_VOLUME "config"
138#define CONFIG_ENV_UBI_VOLUME_REDUND "config_r"
Ladislav Michl4b9dc7c2016-07-12 20:28:32 +0200139#define CONFIG_ENV_SIZE (32*1024)
140
Enric Balletbò i Serradc7a9e62012-03-05 11:32:16 +0000141#endif /* __IGEP00X0_H */