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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 4fb01c4435ae98fdce86ec491ddf3c240f8eb174 / . / arch / arm / dts / am4372.dtsi
blob: c95d1d3b35da3fa908f4a7f5dddaa814e0076c83 [file] [log] [blame]
Mugunthan V N48038c42015-09-28 16:17:51 +0530[diff] [blame]1/*
2 * Device Tree Source for AM4372 SoC
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13
14#include "skeleton.dtsi"
15
16/ {
17 compatible = "ti,am4372", "ti,am43";
18 interrupt-parent = <&wakeupgen>;
19
20
21 aliases {
22 i2c0 = &i2c0;
23 i2c1 = &i2c1;
24 i2c2 = &i2c2;
25 serial0 = &uart0;
26 ethernet0 = &cpsw_emac0;
27 ethernet1 = &cpsw_emac1;
Mugunthan V N4fb01c42015-12-23 20:39:48 +0530[diff] [blame^]28 spi0 = &qspi;
Mugunthan V N48038c42015-09-28 16:17:51 +0530[diff] [blame]29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34 cpu: cpu@0 {
35 compatible = "arm,cortex-a9";
36 device_type = "cpu";
37 reg = <0>;
38
39 clocks = <&dpll_mpu_ck>;
40 clock-names = "cpu";
41
42 clock-latency = <300000>; /* From omap-cpufreq driver */
43 };
44 };
45
46 gic: interrupt-controller@48241000 {
47 compatible = "arm,cortex-a9-gic";
48 interrupt-controller;
49 #interrupt-cells = <3>;
50 reg = <0x48241000 0x1000>,
51 <0x48240100 0x0100>;
52 interrupt-parent = <&gic>;
53 };
54
55 wakeupgen: interrupt-controller@48281000 {
56 compatible = "ti,omap4-wugen-mpu";
57 interrupt-controller;
58 #interrupt-cells = <3>;
59 reg = <0x48281000 0x1000>;
60 interrupt-parent = <&gic>;
61 };
62
63 l2-cache-controller@48242000 {
64 compatible = "arm,pl310-cache";
65 reg = <0x48242000 0x1000>;
66 cache-unified;
67 cache-level = <2>;
68 };
69
70 ocp {
71 compatible = "ti,am4372-l3-noc", "simple-bus";
72 #address-cells = <1>;
73 #size-cells = <1>;
74 ranges;
75 ti,hwmods = "l3_main";
76 reg = <0x44000000 0x400000
77 0x44800000 0x400000>;
78 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
79 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
80
81 l4_wkup: l4_wkup@44c00000 {
82 compatible = "ti,am4-l4-wkup", "simple-bus";
83 #address-cells = <1>;
84 #size-cells = <1>;
85 ranges = <0 0x44c00000 0x287000>;
86
87 prcm: prcm@1f0000 {
88 compatible = "ti,am4-prcm";
89 reg = <0x1f0000 0x11000>;
90
91 prcm_clocks: clocks {
92 #address-cells = <1>;
93 #size-cells = <0>;
94 };
95
96 prcm_clockdomains: clockdomains {
97 };
98 };
99
100 scm: scm@210000 {
101 compatible = "ti,am4-scm", "simple-bus";
102 reg = <0x210000 0x4000>;
103 #address-cells = <1>;
104 #size-cells = <1>;
105 ranges = <0 0x210000 0x4000>;
106
107 am43xx_pinmux: pinmux@800 {
108 compatible = "ti,am437-padconf",
109 "pinctrl-single";
110 reg = <0x800 0x31c>;
111 #address-cells = <1>;
112 #size-cells = <0>;
113 #interrupt-cells = <1>;
114 interrupt-controller;
115 pinctrl-single,register-width = <32>;
116 pinctrl-single,function-mask = <0xffffffff>;
117 };
118
119 scm_conf: scm_conf@0 {
120 compatible = "syscon";
121 reg = <0x0 0x800>;
122 #address-cells = <1>;
123 #size-cells = <1>;
124
125 scm_clocks: clocks {
126 #address-cells = <1>;
127 #size-cells = <0>;
128 };
129 };
130
131 scm_clockdomains: clockdomains {
132 };
133 };
134 };
135
136 emif: emif@4c000000 {
137 compatible = "ti,emif-am4372";
138 reg = <0x4c000000 0x1000000>;
139 ti,hwmods = "emif";
140 };
141
142 edma: edma@49000000 {
143 compatible = "ti,edma3";
144 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
145 reg = <0x49000000 0x10000>,
146 <0x44e10f90 0x10>;
147 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
150 #dma-cells = <1>;
151 };
152
153 uart0: serial@44e09000 {
154 compatible = "ti,am4372-uart","ti,omap2-uart";
155 reg = <0x44e09000 0x2000>;
Mugunthan V N85cf0e62015-11-26 14:49:10 +0530[diff] [blame]156 reg-shift = <2>;
Mugunthan V N48038c42015-09-28 16:17:51 +0530[diff] [blame]157 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
158 ti,hwmods = "uart1";
159 };
160
161 uart1: serial@48022000 {
162 compatible = "ti,am4372-uart","ti,omap2-uart";
163 reg = <0x48022000 0x2000>;
Mugunthan V N85cf0e62015-11-26 14:49:10 +0530[diff] [blame]164 reg-shift = <2>;
Mugunthan V N48038c42015-09-28 16:17:51 +0530[diff] [blame]165 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
166 ti,hwmods = "uart2";
167 status = "disabled";
168 };
169
170 uart2: serial@48024000 {
171 compatible = "ti,am4372-uart","ti,omap2-uart";
172 reg = <0x48024000 0x2000>;
Mugunthan V N85cf0e62015-11-26 14:49:10 +0530[diff] [blame]173 reg-shift = <2>;
Mugunthan V N48038c42015-09-28 16:17:51 +0530[diff] [blame]174 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
175 ti,hwmods = "uart3";
176 status = "disabled";
177 };
178
179 uart3: serial@481a6000 {
180 compatible = "ti,am4372-uart","ti,omap2-uart";
181 reg = <0x481a6000 0x2000>;
Mugunthan V N85cf0e62015-11-26 14:49:10 +0530[diff] [blame]182 reg-shift = <2>;
Mugunthan V N48038c42015-09-28 16:17:51 +0530[diff] [blame]183 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
184 ti,hwmods = "uart4";
185 status = "disabled";
186 };
187
188 uart4: serial@481a8000 {
189 compatible = "ti,am4372-uart","ti,omap2-uart";
190 reg = <0x481a8000 0x2000>;
Mugunthan V N85cf0e62015-11-26 14:49:10 +0530[diff] [blame]191 reg-shift = <2>;
Mugunthan V N48038c42015-09-28 16:17:51 +0530[diff] [blame]192 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
193 ti,hwmods = "uart5";
194 status = "disabled";
195 };
196
197 uart5: serial@481aa000 {
198 compatible = "ti,am4372-uart","ti,omap2-uart";
199 reg = <0x481aa000 0x2000>;
Mugunthan V N85cf0e62015-11-26 14:49:10 +0530[diff] [blame]200 reg-shift = <2>;
Mugunthan V N48038c42015-09-28 16:17:51 +0530[diff] [blame]201 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
202 ti,hwmods = "uart6";
203 status = "disabled";
204 };
205
206 mailbox: mailbox@480C8000 {
207 compatible = "ti,omap4-mailbox";
208 reg = <0x480C8000 0x200>;
209 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
210 ti,hwmods = "mailbox";
211 #mbox-cells = <1>;
212 ti,mbox-num-users = <4>;
213 ti,mbox-num-fifos = <8>;
214 mbox_wkupm3: wkup_m3 {
215 ti,mbox-tx = <0 0 0>;
216 ti,mbox-rx = <0 0 3>;
217 };
218 };
219
220 timer1: timer@44e31000 {
221 compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
222 reg = <0x44e31000 0x400>;
223 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
224 ti,timer-alwon;
225 ti,hwmods = "timer1";
226 };
227
228 timer2: timer@48040000 {
229 compatible = "ti,am4372-timer","ti,am335x-timer";
230 reg = <0x48040000 0x400>;
231 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
232 ti,hwmods = "timer2";
233 };
234
235 timer3: timer@48042000 {
236 compatible = "ti,am4372-timer","ti,am335x-timer";
237 reg = <0x48042000 0x400>;
238 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
239 ti,hwmods = "timer3";
240 status = "disabled";
241 };
242
243 timer4: timer@48044000 {
244 compatible = "ti,am4372-timer","ti,am335x-timer";
245 reg = <0x48044000 0x400>;
246 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
247 ti,timer-pwm;
248 ti,hwmods = "timer4";
249 status = "disabled";
250 };
251
252 timer5: timer@48046000 {
253 compatible = "ti,am4372-timer","ti,am335x-timer";
254 reg = <0x48046000 0x400>;
255 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
256 ti,timer-pwm;
257 ti,hwmods = "timer5";
258 status = "disabled";
259 };
260
261 timer6: timer@48048000 {
262 compatible = "ti,am4372-timer","ti,am335x-timer";
263 reg = <0x48048000 0x400>;
264 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
265 ti,timer-pwm;
266 ti,hwmods = "timer6";
267 status = "disabled";
268 };
269
270 timer7: timer@4804a000 {
271 compatible = "ti,am4372-timer","ti,am335x-timer";
272 reg = <0x4804a000 0x400>;
273 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
274 ti,timer-pwm;
275 ti,hwmods = "timer7";
276 status = "disabled";
277 };
278
279 timer8: timer@481c1000 {
280 compatible = "ti,am4372-timer","ti,am335x-timer";
281 reg = <0x481c1000 0x400>;
282 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
283 ti,hwmods = "timer8";
284 status = "disabled";
285 };
286
287 timer9: timer@4833d000 {
288 compatible = "ti,am4372-timer","ti,am335x-timer";
289 reg = <0x4833d000 0x400>;
290 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
291 ti,hwmods = "timer9";
292 status = "disabled";
293 };
294
295 timer10: timer@4833f000 {
296 compatible = "ti,am4372-timer","ti,am335x-timer";
297 reg = <0x4833f000 0x400>;
298 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
299 ti,hwmods = "timer10";
300 status = "disabled";
301 };
302
303 timer11: timer@48341000 {
304 compatible = "ti,am4372-timer","ti,am335x-timer";
305 reg = <0x48341000 0x400>;
306 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
307 ti,hwmods = "timer11";
308 status = "disabled";
309 };
310
311 counter32k: counter@44e86000 {
312 compatible = "ti,am4372-counter32k","ti,omap-counter32k";
313 reg = <0x44e86000 0x40>;
314 ti,hwmods = "counter_32k";
315 };
316
317 rtc: rtc@44e3e000 {
318 compatible = "ti,am4372-rtc","ti,da830-rtc";
319 reg = <0x44e3e000 0x1000>;
320 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
321 GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
322 ti,hwmods = "rtc";
323 status = "disabled";
324 };
325
326 wdt: wdt@44e35000 {
327 compatible = "ti,am4372-wdt","ti,omap3-wdt";
328 reg = <0x44e35000 0x1000>;
329 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
330 ti,hwmods = "wd_timer2";
331 };
332
333 gpio0: gpio@44e07000 {
334 compatible = "ti,am4372-gpio","ti,omap4-gpio";
335 reg = <0x44e07000 0x1000>;
336 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
337 gpio-controller;
338 #gpio-cells = <2>;
339 interrupt-controller;
340 #interrupt-cells = <2>;
341 ti,hwmods = "gpio1";
342 status = "disabled";
343 };
344
345 gpio1: gpio@4804c000 {
346 compatible = "ti,am4372-gpio","ti,omap4-gpio";
347 reg = <0x4804c000 0x1000>;
348 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
349 gpio-controller;
350 #gpio-cells = <2>;
351 interrupt-controller;
352 #interrupt-cells = <2>;
353 ti,hwmods = "gpio2";
354 status = "disabled";
355 };
356
357 gpio2: gpio@481ac000 {
358 compatible = "ti,am4372-gpio","ti,omap4-gpio";
359 reg = <0x481ac000 0x1000>;
360 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
361 gpio-controller;
362 #gpio-cells = <2>;
363 interrupt-controller;
364 #interrupt-cells = <2>;
365 ti,hwmods = "gpio3";
366 status = "disabled";
367 };
368
369 gpio3: gpio@481ae000 {
370 compatible = "ti,am4372-gpio","ti,omap4-gpio";
371 reg = <0x481ae000 0x1000>;
372 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
373 gpio-controller;
374 #gpio-cells = <2>;
375 interrupt-controller;
376 #interrupt-cells = <2>;
377 ti,hwmods = "gpio4";
378 status = "disabled";
379 };
380
381 gpio4: gpio@48320000 {
382 compatible = "ti,am4372-gpio","ti,omap4-gpio";
383 reg = <0x48320000 0x1000>;
384 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
385 gpio-controller;
386 #gpio-cells = <2>;
387 interrupt-controller;
388 #interrupt-cells = <2>;
389 ti,hwmods = "gpio5";
390 status = "disabled";
391 };
392
393 gpio5: gpio@48322000 {
394 compatible = "ti,am4372-gpio","ti,omap4-gpio";
395 reg = <0x48322000 0x1000>;
396 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
397 gpio-controller;
398 #gpio-cells = <2>;
399 interrupt-controller;
400 #interrupt-cells = <2>;
401 ti,hwmods = "gpio6";
402 status = "disabled";
403 };
404
405 hwspinlock: spinlock@480ca000 {
406 compatible = "ti,omap4-hwspinlock";
407 reg = <0x480ca000 0x1000>;
408 ti,hwmods = "spinlock";
409 #hwlock-cells = <1>;
410 };
411
412 i2c0: i2c@44e0b000 {
413 compatible = "ti,am4372-i2c","ti,omap4-i2c";
414 reg = <0x44e0b000 0x1000>;
415 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
416 ti,hwmods = "i2c1";
417 #address-cells = <1>;
418 #size-cells = <0>;
419 status = "disabled";
420 };
421
422 i2c1: i2c@4802a000 {
423 compatible = "ti,am4372-i2c","ti,omap4-i2c";
424 reg = <0x4802a000 0x1000>;
425 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
426 ti,hwmods = "i2c2";
427 #address-cells = <1>;
428 #size-cells = <0>;
429 status = "disabled";
430 };
431
432 i2c2: i2c@4819c000 {
433 compatible = "ti,am4372-i2c","ti,omap4-i2c";
434 reg = <0x4819c000 0x1000>;
435 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
436 ti,hwmods = "i2c3";
437 #address-cells = <1>;
438 #size-cells = <0>;
439 status = "disabled";
440 };
441
442 spi0: spi@48030000 {
443 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
444 reg = <0x48030000 0x400>;
445 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
446 ti,hwmods = "spi0";
447 #address-cells = <1>;
448 #size-cells = <0>;
449 status = "disabled";
450 };
451
452 mmc1: mmc@48060000 {
453 compatible = "ti,omap4-hsmmc";
454 reg = <0x48060000 0x1000>;
455 ti,hwmods = "mmc1";
456 ti,dual-volt;
457 ti,needs-special-reset;
458 dmas = <&edma 24
459 &edma 25>;
460 dma-names = "tx", "rx";
461 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
462 status = "disabled";
463 };
464
465 mmc2: mmc@481d8000 {
466 compatible = "ti,omap4-hsmmc";
467 reg = <0x481d8000 0x1000>;
468 ti,hwmods = "mmc2";
469 ti,needs-special-reset;
470 dmas = <&edma 2
471 &edma 3>;
472 dma-names = "tx", "rx";
473 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
474 status = "disabled";
475 };
476
477 mmc3: mmc@47810000 {
478 compatible = "ti,omap4-hsmmc";
479 reg = <0x47810000 0x1000>;
480 ti,hwmods = "mmc3";
481 ti,needs-special-reset;
482 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
483 status = "disabled";
484 };
485
486 spi1: spi@481a0000 {
487 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
488 reg = <0x481a0000 0x400>;
489 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
490 ti,hwmods = "spi1";
491 #address-cells = <1>;
492 #size-cells = <0>;
493 status = "disabled";
494 };
495
496 spi2: spi@481a2000 {
497 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
498 reg = <0x481a2000 0x400>;
499 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
500 ti,hwmods = "spi2";
501 #address-cells = <1>;
502 #size-cells = <0>;
503 status = "disabled";
504 };
505
506 spi3: spi@481a4000 {
507 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
508 reg = <0x481a4000 0x400>;
509 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
510 ti,hwmods = "spi3";
511 #address-cells = <1>;
512 #size-cells = <0>;
513 status = "disabled";
514 };
515
516 spi4: spi@48345000 {
517 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
518 reg = <0x48345000 0x400>;
519 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
520 ti,hwmods = "spi4";
521 #address-cells = <1>;
522 #size-cells = <0>;
523 status = "disabled";
524 };
525
526 mac: ethernet@4a100000 {
527 compatible = "ti,am4372-cpsw","ti,cpsw";
528 reg = <0x4a100000 0x800
529 0x4a101200 0x100>;
530 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
531 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
532 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
533 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
534 #address-cells = <1>;
535 #size-cells = <1>;
536 ti,hwmods = "cpgmac0";
537 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
538 clock-names = "fck", "cpts";
539 status = "disabled";
540 cpdma_channels = <8>;
541 ale_entries = <1024>;
542 bd_ram_size = <0x2000>;
543 no_bd_ram = <0>;
544 rx_descs = <64>;
545 mac_control = <0x20>;
546 slaves = <2>;
547 active_slave = <0>;
548 cpts_clock_mult = <0x80000000>;
549 cpts_clock_shift = <29>;
550 ranges;
551
552 davinci_mdio: mdio@4a101000 {
553 compatible = "ti,am4372-mdio","ti,davinci_mdio";
554 reg = <0x4a101000 0x100>;
555 #address-cells = <1>;
556 #size-cells = <0>;
557 ti,hwmods = "davinci_mdio";
558 bus_freq = <1000000>;
559 status = "disabled";
560 };
561
562 cpsw_emac0: slave@4a100200 {
563 /* Filled in by U-Boot */
564 mac-address = [ 00 00 00 00 00 00 ];
565 };
566
567 cpsw_emac1: slave@4a100300 {
568 /* Filled in by U-Boot */
569 mac-address = [ 00 00 00 00 00 00 ];
570 };
571
572 phy_sel: cpsw-phy-sel@44e10650 {
573 compatible = "ti,am43xx-cpsw-phy-sel";
574 reg= <0x44e10650 0x4>;
575 reg-names = "gmii-sel";
576 };
577 };
578
579 epwmss0: epwmss@48300000 {
580 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
581 reg = <0x48300000 0x10>;
582 #address-cells = <1>;
583 #size-cells = <1>;
584 ranges;
585 ti,hwmods = "epwmss0";
586 status = "disabled";
587
588 ecap0: ecap@48300100 {
589 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
590 #pwm-cells = <3>;
591 reg = <0x48300100 0x80>;
592 ti,hwmods = "ecap0";
593 status = "disabled";
594 };
595
596 ehrpwm0: ehrpwm@48300200 {
597 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
598 #pwm-cells = <3>;
599 reg = <0x48300200 0x80>;
600 ti,hwmods = "ehrpwm0";
601 status = "disabled";
602 };
603 };
604
605 epwmss1: epwmss@48302000 {
606 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
607 reg = <0x48302000 0x10>;
608 #address-cells = <1>;
609 #size-cells = <1>;
610 ranges;
611 ti,hwmods = "epwmss1";
612 status = "disabled";
613
614 ecap1: ecap@48302100 {
615 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
616 #pwm-cells = <3>;
617 reg = <0x48302100 0x80>;
618 ti,hwmods = "ecap1";
619 status = "disabled";
620 };
621
622 ehrpwm1: ehrpwm@48302200 {
623 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
624 #pwm-cells = <3>;
625 reg = <0x48302200 0x80>;
626 ti,hwmods = "ehrpwm1";
627 status = "disabled";
628 };
629 };
630
631 epwmss2: epwmss@48304000 {
632 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
633 reg = <0x48304000 0x10>;
634 #address-cells = <1>;
635 #size-cells = <1>;
636 ranges;
637 ti,hwmods = "epwmss2";
638 status = "disabled";
639
640 ecap2: ecap@48304100 {
641 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
642 #pwm-cells = <3>;
643 reg = <0x48304100 0x80>;
644 ti,hwmods = "ecap2";
645 status = "disabled";
646 };
647
648 ehrpwm2: ehrpwm@48304200 {
649 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
650 #pwm-cells = <3>;
651 reg = <0x48304200 0x80>;
652 ti,hwmods = "ehrpwm2";
653 status = "disabled";
654 };
655 };
656
657 epwmss3: epwmss@48306000 {
658 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
659 reg = <0x48306000 0x10>;
660 #address-cells = <1>;
661 #size-cells = <1>;
662 ranges;
663 ti,hwmods = "epwmss3";
664 status = "disabled";
665
666 ehrpwm3: ehrpwm@48306200 {
667 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
668 #pwm-cells = <3>;
669 reg = <0x48306200 0x80>;
670 ti,hwmods = "ehrpwm3";
671 status = "disabled";
672 };
673 };
674
675 epwmss4: epwmss@48308000 {
676 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
677 reg = <0x48308000 0x10>;
678 #address-cells = <1>;
679 #size-cells = <1>;
680 ranges;
681 ti,hwmods = "epwmss4";
682 status = "disabled";
683
684 ehrpwm4: ehrpwm@48308200 {
685 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
686 #pwm-cells = <3>;
687 reg = <0x48308200 0x80>;
688 ti,hwmods = "ehrpwm4";
689 status = "disabled";
690 };
691 };
692
693 epwmss5: epwmss@4830a000 {
694 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
695 reg = <0x4830a000 0x10>;
696 #address-cells = <1>;
697 #size-cells = <1>;
698 ranges;
699 ti,hwmods = "epwmss5";
700 status = "disabled";
701
702 ehrpwm5: ehrpwm@4830a200 {
703 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
704 #pwm-cells = <3>;
705 reg = <0x4830a200 0x80>;
706 ti,hwmods = "ehrpwm5";
707 status = "disabled";
708 };
709 };
710
711 tscadc: tscadc@44e0d000 {
712 compatible = "ti,am3359-tscadc";
713 reg = <0x44e0d000 0x1000>;
714 ti,hwmods = "adc_tsc";
715 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
716 clocks = <&adc_tsc_fck>;
717 clock-names = "fck";
718 status = "disabled";
719
720 tsc {
721 compatible = "ti,am3359-tsc";
722 };
723
724 adc {
725 #io-channel-cells = <1>;
726 compatible = "ti,am3359-adc";
727 };
728
729 };
730
731 sham: sham@53100000 {
732 compatible = "ti,omap5-sham";
733 ti,hwmods = "sham";
734 reg = <0x53100000 0x300>;
735 dmas = <&edma 36>;
736 dma-names = "rx";
737 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
738 };
739
740 aes: aes@53501000 {
741 compatible = "ti,omap4-aes";
742 ti,hwmods = "aes";
743 reg = <0x53501000 0xa0>;
744 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
745 dmas = <&edma 6
746 &edma 5>;
747 dma-names = "tx", "rx";
748 };
749
750 des: des@53701000 {
751 compatible = "ti,omap4-des";
752 ti,hwmods = "des";
753 reg = <0x53701000 0xa0>;
754 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
755 dmas = <&edma 34
756 &edma 33>;
757 dma-names = "tx", "rx";
758 };
759
760 mcasp0: mcasp@48038000 {
761 compatible = "ti,am33xx-mcasp-audio";
762 ti,hwmods = "mcasp0";
763 reg = <0x48038000 0x2000>,
764 <0x46000000 0x400000>;
765 reg-names = "mpu", "dat";
766 interrupts = <80>, <81>;
767 interrupt-names = "tx", "rx";
768 status = "disabled";
769 dmas = <&edma 8>,
770 <&edma 9>;
771 dma-names = "tx", "rx";
772 };
773
774 mcasp1: mcasp@4803C000 {
775 compatible = "ti,am33xx-mcasp-audio";
776 ti,hwmods = "mcasp1";
777 reg = <0x4803C000 0x2000>,
778 <0x46400000 0x400000>;
779 reg-names = "mpu", "dat";
780 interrupts = <82>, <83>;
781 interrupt-names = "tx", "rx";
782 status = "disabled";
783 dmas = <&edma 10>,
784 <&edma 11>;
785 dma-names = "tx", "rx";
786 };
787
788 elm: elm@48080000 {
789 compatible = "ti,am3352-elm";
790 reg = <0x48080000 0x2000>;
791 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
792 ti,hwmods = "elm";
793 clocks = <&l4ls_gclk>;
794 clock-names = "fck";
795 status = "disabled";
796 };
797
798 gpmc: gpmc@50000000 {
799 compatible = "ti,am3352-gpmc";
800 ti,hwmods = "gpmc";
801 clocks = <&l3s_gclk>;
802 clock-names = "fck";
803 reg = <0x50000000 0x2000>;
804 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
805 gpmc,num-cs = <7>;
806 gpmc,num-waitpins = <2>;
807 #address-cells = <2>;
808 #size-cells = <1>;
809 status = "disabled";
810 };
811
812 am43xx_control_usb2phy1: control-phy@44e10620 {
813 compatible = "ti,control-phy-usb2-am437";
814 reg = <0x44e10620 0x4>;
815 reg-names = "power";
816 };
817
818 am43xx_control_usb2phy2: control-phy@0x44e10628 {
819 compatible = "ti,control-phy-usb2-am437";
820 reg = <0x44e10628 0x4>;
821 reg-names = "power";
822 };
823
824 ocp2scp0: ocp2scp@483a8000 {
825 compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
826 #address-cells = <1>;
827 #size-cells = <1>;
828 ranges;
829 ti,hwmods = "ocp2scp0";
830
831 usb2_phy1: phy@483a8000 {
832 compatible = "ti,am437x-usb2";
833 reg = <0x483a8000 0x8000>;
834 ctrl-module = <&am43xx_control_usb2phy1>;
835 clocks = <&usb_phy0_always_on_clk32k>,
836 <&usb_otg_ss0_refclk960m>;
837 clock-names = "wkupclk", "refclk";
838 #phy-cells = <0>;
839 status = "disabled";
840 };
841 };
842
843 ocp2scp1: ocp2scp@483e8000 {
844 compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
845 #address-cells = <1>;
846 #size-cells = <1>;
847 ranges;
848 ti,hwmods = "ocp2scp1";
849
850 usb2_phy2: phy@483e8000 {
851 compatible = "ti,am437x-usb2";
852 reg = <0x483e8000 0x8000>;
853 ctrl-module = <&am43xx_control_usb2phy2>;
854 clocks = <&usb_phy1_always_on_clk32k>,
855 <&usb_otg_ss1_refclk960m>;
856 clock-names = "wkupclk", "refclk";
857 #phy-cells = <0>;
858 status = "disabled";
859 };
860 };
861
862 dwc3_1: omap_dwc3@48380000 {
863 compatible = "ti,am437x-dwc3";
864 ti,hwmods = "usb_otg_ss0";
865 reg = <0x48380000 0x10000>;
866 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
867 #address-cells = <1>;
868 #size-cells = <1>;
869 utmi-mode = <1>;
870 ranges;
871
872 usb1: usb@48390000 {
873 compatible = "synopsys,dwc3";
874 reg = <0x48390000 0x10000>;
875 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
876 phys = <&usb2_phy1>;
877 phy-names = "usb2-phy";
878 maximum-speed = "high-speed";
879 dr_mode = "otg";
880 status = "disabled";
881 snps,dis_u3_susphy_quirk;
882 snps,dis_u2_susphy_quirk;
883 };
884 };
885
886 dwc3_2: omap_dwc3@483c0000 {
887 compatible = "ti,am437x-dwc3";
888 ti,hwmods = "usb_otg_ss1";
889 reg = <0x483c0000 0x10000>;
890 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
891 #address-cells = <1>;
892 #size-cells = <1>;
893 utmi-mode = <1>;
894 ranges;
895
896 usb2: usb@483d0000 {
897 compatible = "synopsys,dwc3";
898 reg = <0x483d0000 0x10000>;
899 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
900 phys = <&usb2_phy2>;
901 phy-names = "usb2-phy";
902 maximum-speed = "high-speed";
903 dr_mode = "otg";
904 status = "disabled";
905 snps,dis_u3_susphy_quirk;
906 snps,dis_u2_susphy_quirk;
907 };
908 };
909
910 qspi: qspi@47900000 {
911 compatible = "ti,am4372-qspi";
Mugunthan V N4fb01c42015-12-23 20:39:48 +0530[diff] [blame^]912 reg = <0x47900000 0x100>,
913 <0x30000000 0x4000000>;
914 reg-names = "qspi_base", "qspi_mmap";
Mugunthan V N48038c42015-09-28 16:17:51 +0530[diff] [blame]915 #address-cells = <1>;
916 #size-cells = <0>;
917 ti,hwmods = "qspi";
918 interrupts = <0 138 0x4>;
919 num-cs = <4>;
920 status = "disabled";
921 };
922
923 hdq: hdq@48347000 {
924 compatible = "ti,am4372-hdq";
925 reg = <0x48347000 0x1000>;
926 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
927 clocks = <&func_12m_clk>;
928 clock-names = "fck";
929 ti,hwmods = "hdq1w";
930 status = "disabled";
931 };
932
933 dss: dss@4832a000 {
934 compatible = "ti,omap3-dss";
935 reg = <0x4832a000 0x200>;
936 status = "disabled";
937 ti,hwmods = "dss_core";
938 clocks = <&disp_clk>;
939 clock-names = "fck";
940 #address-cells = <1>;
941 #size-cells = <1>;
942 ranges;
943
944 dispc: dispc@4832a400 {
945 compatible = "ti,omap3-dispc";
946 reg = <0x4832a400 0x400>;
947 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
948 ti,hwmods = "dss_dispc";
949 clocks = <&disp_clk>;
950 clock-names = "fck";
951 };
952
953 rfbi: rfbi@4832a800 {
954 compatible = "ti,omap3-rfbi";
955 reg = <0x4832a800 0x100>;
956 ti,hwmods = "dss_rfbi";
957 clocks = <&disp_clk>;
958 clock-names = "fck";
959 status = "disabled";
960 };
961 };
962
963 ocmcram: ocmcram@40300000 {
964 compatible = "mmio-sram";
965 reg = <0x40300000 0x40000>; /* 256k */
966 };
967
968 dcan0: can@481cc000 {
969 compatible = "ti,am4372-d_can", "ti,am3352-d_can";
970 ti,hwmods = "d_can0";
971 clocks = <&dcan0_fck>;
972 clock-names = "fck";
973 reg = <0x481cc000 0x2000>;
974 syscon-raminit = <&scm_conf 0x644 0>;
975 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
976 status = "disabled";
977 };
978
979 dcan1: can@481d0000 {
980 compatible = "ti,am4372-d_can", "ti,am3352-d_can";
981 ti,hwmods = "d_can1";
982 clocks = <&dcan1_fck>;
983 clock-names = "fck";
984 reg = <0x481d0000 0x2000>;
985 syscon-raminit = <&scm_conf 0x644 1>;
986 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
987 status = "disabled";
988 };
989
990 vpfe0: vpfe@48326000 {
991 compatible = "ti,am437x-vpfe";
992 reg = <0x48326000 0x2000>;
993 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
994 ti,hwmods = "vpfe0";
995 status = "disabled";
996 };
997
998 vpfe1: vpfe@48328000 {
999 compatible = "ti,am437x-vpfe";
1000 reg = <0x48328000 0x2000>;
1001 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1002 ti,hwmods = "vpfe1";
1003 status = "disabled";
1004 };
1005 };
1006};
1007
1008/include/ "am43xx-clocks.dtsi"