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wdenk5da627a2003-10-09 20:09:04 +00001/* Only eth0 supported for now
2 *
3 * (C) Copyright 2003
4 * Thomas.Lange@corelatus.se
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Wolfgang Denk265817c2005-09-25 00:53:22 +020016 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenk5da627a2003-10-09 20:09:04 +000017 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24#include <config.h>
25
26#ifdef CONFIG_AU1X00
27
Wolfgang Denk265817c2005-09-25 00:53:22 +020028#if defined(CFG_DISCOVER_PHY)
29#error "PHY not supported yet"
wdenk5da627a2003-10-09 20:09:04 +000030/* We just assume that we are running 100FD for now */
31/* We all use switches, right? ;-) */
32#endif
33
wdenka2663ea2003-12-07 18:32:37 +000034/* I assume ethernet behaves like au1000 */
35
wdenk5da627a2003-10-09 20:09:04 +000036#ifdef CONFIG_AU1000
37/* Base address differ between cpu:s */
38#define ETH0_BASE AU1000_ETH0_BASE
39#define MAC0_ENABLE AU1000_MAC0_ENABLE
40#else
wdenka2663ea2003-12-07 18:32:37 +000041#ifdef CONFIG_AU1100
42#define ETH0_BASE AU1100_ETH0_BASE
43#define MAC0_ENABLE AU1100_MAC0_ENABLE
44#else
45#ifdef CONFIG_AU1500
46#define ETH0_BASE AU1500_ETH0_BASE
47#define MAC0_ENABLE AU1500_MAC0_ENABLE
48#else
wdenkff36fd82005-01-09 22:28:56 +000049#ifdef CONFIG_AU1550
50#define ETH0_BASE AU1550_ETH0_BASE
51#define MAC0_ENABLE AU1550_MAC0_ENABLE
52#else
wdenka2663ea2003-12-07 18:32:37 +000053#error "No valid cpu set"
54#endif
55#endif
wdenk5da627a2003-10-09 20:09:04 +000056#endif
wdenkff36fd82005-01-09 22:28:56 +000057#endif
wdenk5da627a2003-10-09 20:09:04 +000058
59#include <common.h>
60#include <malloc.h>
61#include <net.h>
62#include <command.h>
63#include <asm/io.h>
64#include <asm/au1x00.h>
65
Jon Loeliger44312832007-07-09 19:06:00 -050066#if defined(CONFIG_CMD_MII)
Marian Balakowicz63ff0042005-10-28 22:30:33 +020067#include <miiphy.h>
68#endif
69
wdenk5da627a2003-10-09 20:09:04 +000070/* Ethernet Transmit and Receive Buffers */
71#define DBUF_LENGTH 1520
72#define PKT_MAXBUF_SIZE 1518
73
74static char txbuf[DBUF_LENGTH];
75
76static int next_tx;
77static int next_rx;
78
79/* 4 rx and 4 tx fifos */
80#define NO_OF_FIFOS 4
81
82typedef struct{
83 u32 status;
84 u32 addr;
85 u32 len; /* Only used for tx */
86 u32 not_used;
87} mac_fifo_t;
88
89mac_fifo_t mac_fifo[NO_OF_FIFOS];
90
91#define MAX_WAIT 1000
92
Shinya Kuribayashif0132042007-10-27 15:00:25 +090093#if defined(CONFIG_CMD_MII)
94int au1x00_miiphy_read(char *devname, unsigned char addr,
95 unsigned char reg, unsigned short * value)
96{
97 volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
98 volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
99 u32 mii_control;
100 unsigned int timedout = 20;
101
102 while (*mii_control_reg & MAC_MII_BUSY) {
103 udelay(1000);
104 if (--timedout == 0) {
105 printf("au1x00_eth: miiphy_read busy timeout!!\n");
106 return -1;
107 }
108 }
109
110 mii_control = MAC_SET_MII_SELECT_REG(reg) |
111 MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ;
112
113 *mii_control_reg = mii_control;
114
115 timedout = 20;
116 while (*mii_control_reg & MAC_MII_BUSY) {
117 udelay(1000);
118 if (--timedout == 0) {
119 printf("au1x00_eth: miiphy_read busy timeout!!\n");
120 return -1;
121 }
122 }
123 *value = *mii_data_reg;
124 return 0;
125}
126
127int au1x00_miiphy_write(char *devname, unsigned char addr,
128 unsigned char reg, unsigned short value)
129{
130 volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
131 volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
132 u32 mii_control;
133 unsigned int timedout = 20;
134
135 while (*mii_control_reg & MAC_MII_BUSY) {
136 udelay(1000);
137 if (--timedout == 0) {
138 printf("au1x00_eth: miiphy_write busy timeout!!\n");
Shinya Kuribayashi4fbd0742007-10-27 15:22:33 +0900139 return -1;
Shinya Kuribayashif0132042007-10-27 15:00:25 +0900140 }
141 }
142
143 mii_control = MAC_SET_MII_SELECT_REG(reg) |
144 MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE;
145
146 *mii_data_reg = value;
147 *mii_control_reg = mii_control;
148 return 0;
149}
150#endif
151
wdenk5da627a2003-10-09 20:09:04 +0000152static int au1x00_send(struct eth_device* dev, volatile void *packet, int length){
153 volatile mac_fifo_t *fifo_tx =
154 (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
155 int i;
156 int res;
157
158 /* tx fifo should always be idle */
159 fifo_tx[next_tx].len = length;
160 fifo_tx[next_tx].addr = (virt_to_phys(packet))|TX_DMA_ENABLE;
161 au_sync();
162
163 udelay(1);
164 i=0;
165 while(!(fifo_tx[next_tx].addr&TX_T_DONE)){
166 if(i>MAX_WAIT){
167 printf("TX timeout\n");
168 break;
169 }
170 udelay(1);
171 i++;
172 }
173
174 /* Clear done bit */
175 fifo_tx[next_tx].addr = 0;
176 fifo_tx[next_tx].len = 0;
177 au_sync();
178
179 res = fifo_tx[next_tx].status;
180
181 next_tx++;
182 if(next_tx>=NO_OF_FIFOS){
183 next_tx=0;
184 }
185 return(res);
186}
187
188static int au1x00_recv(struct eth_device* dev){
189 volatile mac_fifo_t *fifo_rx =
190 (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
191
192 int length;
193 u32 status;
194
195 for(;;){
196 if(!(fifo_rx[next_rx].addr&RX_T_DONE)){
197 /* Nothing has been received */
198 return(-1);
199 }
200
201 status = fifo_rx[next_rx].status;
202
203 length = status&0x3FFF;
204
205 if(status&RX_ERROR){
206 printf("Rx error 0x%x\n", status);
207 }
208 else{
209 /* Pass the packet up to the protocol layers. */
210 NetReceive(NetRxPackets[next_rx], length - 4);
211 }
212
213 fifo_rx[next_rx].addr = (virt_to_phys(NetRxPackets[next_rx]))|RX_DMA_ENABLE;
214
215 next_rx++;
216 if(next_rx>=NO_OF_FIFOS){
217 next_rx=0;
218 }
219 } /* for */
220
221 return(0); /* Does anyone use this? */
222}
223
224static int au1x00_init(struct eth_device* dev, bd_t * bd){
225
226 volatile u32 *macen = (volatile u32*)MAC0_ENABLE;
227 volatile u32 *mac_ctrl = (volatile u32*)(ETH0_BASE+MAC_CONTROL);
228 volatile u32 *mac_addr_high = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_HIGH);
229 volatile u32 *mac_addr_low = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_LOW);
230 volatile u32 *mac_mcast_high = (volatile u32*)(ETH0_BASE+MAC_MCAST_HIGH);
231 volatile u32 *mac_mcast_low = (volatile u32*)(ETH0_BASE+MAC_MCAST_LOW);
232 volatile mac_fifo_t *fifo_tx =
233 (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
234 volatile mac_fifo_t *fifo_rx =
235 (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
236 int i;
237
Wolfgang Denk4bc12f12005-09-24 22:05:40 +0200238 next_tx = TX_GET_DMA_BUFFER(fifo_tx[0].addr);
239 next_rx = RX_GET_DMA_BUFFER(fifo_rx[0].addr);
wdenk5da627a2003-10-09 20:09:04 +0000240
241 /* We have to enable clocks before releasing reset */
242 *macen = MAC_EN_CLOCK_ENABLE;
243 udelay(10);
244
245 /* Enable MAC0 */
246 /* We have to release reset before accessing registers */
247 *macen = MAC_EN_CLOCK_ENABLE|MAC_EN_RESET0|
248 MAC_EN_RESET1|MAC_EN_RESET2;
249 udelay(10);
250
251 for(i=0;i<NO_OF_FIFOS;i++){
252 fifo_tx[i].len = 0;
253 fifo_tx[i].addr = virt_to_phys(&txbuf[0]);
254 fifo_rx[i].addr = (virt_to_phys(NetRxPackets[i]))|RX_DMA_ENABLE;
255 }
256
257 /* Put mac addr in little endian */
wdenk5da627a2003-10-09 20:09:04 +0000258#define ea eth_get_dev()->enetaddr
Wolfgang Denk265817c2005-09-25 00:53:22 +0200259 *mac_addr_high = (ea[5] << 8) | (ea[4] ) ;
260 *mac_addr_low = (ea[3] << 24) | (ea[2] << 16) |
261 (ea[1] << 8) | (ea[0] ) ;
wdenk5da627a2003-10-09 20:09:04 +0000262#undef ea
wdenk5da627a2003-10-09 20:09:04 +0000263 *mac_mcast_low = 0;
264 *mac_mcast_high = 0;
265
wdenk63f34912004-01-02 15:01:32 +0000266 /* Make sure the MAC buffer is in the correct endian mode */
267#ifdef __LITTLE_ENDIAN
268 *mac_ctrl = MAC_FULL_DUPLEX;
269 udelay(1);
270 *mac_ctrl = MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
271#else
wdenk5da627a2003-10-09 20:09:04 +0000272 *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX;
273 udelay(1);
274 *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
wdenk63f34912004-01-02 15:01:32 +0000275#endif
wdenk5da627a2003-10-09 20:09:04 +0000276
277 return(1);
278}
279
280static void au1x00_halt(struct eth_device* dev){
281}
282
283int au1x00_enet_initialize(bd_t *bis){
284 struct eth_device* dev;
285
Wolfgang Denk95515302006-03-13 01:00:22 +0100286 if ((dev = (struct eth_device*)malloc(sizeof *dev)) == NULL) {
287 puts ("malloc failed\n");
288 return 0;
289 }
290
wdenk5da627a2003-10-09 20:09:04 +0000291 memset(dev, 0, sizeof *dev);
292
Wolfgang Denk95515302006-03-13 01:00:22 +0100293 sprintf(dev->name, "Au1X00 ethernet");
wdenk5da627a2003-10-09 20:09:04 +0000294 dev->iobase = 0;
295 dev->priv = 0;
296 dev->init = au1x00_init;
297 dev->halt = au1x00_halt;
298 dev->send = au1x00_send;
299 dev->recv = au1x00_recv;
300
301 eth_register(dev);
302
Jon Loeliger44312832007-07-09 19:06:00 -0500303#if defined(CONFIG_CMD_MII)
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200304 miiphy_register(dev->name,
305 au1x00_miiphy_read, au1x00_miiphy_write);
306#endif
307
wdenk5da627a2003-10-09 20:09:04 +0000308 return 1;
309}
310
wdenk5da627a2003-10-09 20:09:04 +0000311#endif /* CONFIG_AU1X00 */