blob: de62921b78fd3a7aa7a306e34dc1d2c35fcaf54e [file] [log] [blame]
Andy Yanfe9d4e72017-05-15 18:19:42 +08001/*
2 * (C) Copyright Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7#include <common.h>
8#include <dm.h>
9#include <errno.h>
10#include <sysreset.h>
11#include <asm/io.h>
12#include <asm/arch/clock.h>
13#include <asm/arch/cru_rk3368.h>
14#include <asm/arch/hardware.h>
15#include <linux/err.h>
16
17static void rk3368_pll_enter_slow_mode(struct rk3368_cru *cru)
18{
19 struct rk3368_pll *pll;
20 int i;
21
22 for (i = 0; i < 6; i++) {
23 pll = &cru->pll[i];
24 rk_clrreg(&pll->con3, PLL_MODE_MASK);
25 }
26}
27
28static int rk3368_sysreset_request(struct udevice *dev, enum sysreset_t type)
29{
30 struct rk3368_cru *cru = rockchip_get_cru();
31
32 if (IS_ERR(cru))
33 return PTR_ERR(cru);
34 switch (type) {
35 case SYSRESET_WARM:
36 rk3368_pll_enter_slow_mode(cru);
37 rk_clrsetreg(&cru->glb_rst_con, PMU_GLB_SRST_CTRL_MASK,
38 PMU_RST_BY_SND_GLB_SRST << PMU_GLB_SRST_CTRL_SHIFT);
39 writel(0xeca8, &cru->glb_srst_snd_val);
40 break;
41 case SYSRESET_COLD:
42 rk3368_pll_enter_slow_mode(cru);
43 rk_clrsetreg(&cru->glb_rst_con, PMU_GLB_SRST_CTRL_MASK,
44 PMU_RST_BY_FST_GLB_SRST << PMU_GLB_SRST_CTRL_SHIFT);
45 writel(0xfdb9, &cru->glb_srst_fst_val);
46 break;
47 default:
48 return -EPROTONOSUPPORT;
49 }
50
51 return -EINPROGRESS;
52}
53
54static struct sysreset_ops rk3368_sysreset = {
55 .request = rk3368_sysreset_request,
56};
57
58U_BOOT_DRIVER(sysreset_rk3368) = {
59 .name = "rk3368_sysreset",
60 .id = UCLASS_SYSRESET,
61 .ops = &rk3368_sysreset,
62};