blob: 7f90ae4e59bb9452145ba1a8fcf81ca693f55a59 [file] [log] [blame]
Roberto Cerati45a16932013-04-24 10:46:17 +08001/*
2 * drivers/net/ks8851_mll.c
3 *
4 * Supports:
5 * KS8851 16bit MLL chip from Micrel Inc.
6 *
7 * Copyright (c) 2009 Micrel Inc.
8 *
9 * modified by
10 * (c) 2011 Bticino s.p.a, Roberto Cerati <roberto.cerati@bticino.it>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25#ifndef _KS8851_MLL_H_
26#define _KS8851_MLL_H_
27
28#include <linux/types.h>
29
30#define KS_CCR 0x08
31#define CCR_EEPROM (1 << 9)
32#define CCR_SPI (1 << 8)
33#define CCR_8BIT (1 << 7)
34#define CCR_16BIT (1 << 6)
35#define CCR_32BIT (1 << 5)
36#define CCR_SHARED (1 << 4)
37#define CCR_32PIN (1 << 0)
38
39/* MAC address registers */
40#define KS_MARL 0x10
41#define KS_MARM 0x12
42#define KS_MARH 0x14
43
44#define KS_OBCR 0x20
45#define OBCR_ODS_16MA (1 << 6)
46
47#define KS_EEPCR 0x22
48#define EEPCR_EESA (1 << 4)
49#define EEPCR_EESB (1 << 3)
50#define EEPCR_EEDO (1 << 2)
51#define EEPCR_EESCK (1 << 1)
52#define EEPCR_EECS (1 << 0)
53
54#define KS_MBIR 0x24
55#define MBIR_TXMBF (1 << 12)
56#define MBIR_TXMBFA (1 << 11)
57#define MBIR_RXMBF (1 << 4)
58#define MBIR_RXMBFA (1 << 3)
59
60#define KS_GRR 0x26
61#define GRR_QMU (1 << 1)
62#define GRR_GSR (1 << 0)
63
64#define KS_WFCR 0x2A
65#define WFCR_MPRXE (1 << 7)
66#define WFCR_WF3E (1 << 3)
67#define WFCR_WF2E (1 << 2)
68#define WFCR_WF1E (1 << 1)
69#define WFCR_WF0E (1 << 0)
70
71#define KS_WF0CRC0 0x30
72#define KS_WF0CRC1 0x32
73#define KS_WF0BM0 0x34
74#define KS_WF0BM1 0x36
75#define KS_WF0BM2 0x38
76#define KS_WF0BM3 0x3A
77
78#define KS_WF1CRC0 0x40
79#define KS_WF1CRC1 0x42
80#define KS_WF1BM0 0x44
81#define KS_WF1BM1 0x46
82#define KS_WF1BM2 0x48
83#define KS_WF1BM3 0x4A
84
85#define KS_WF2CRC0 0x50
86#define KS_WF2CRC1 0x52
87#define KS_WF2BM0 0x54
88#define KS_WF2BM1 0x56
89#define KS_WF2BM2 0x58
90#define KS_WF2BM3 0x5A
91
92#define KS_WF3CRC0 0x60
93#define KS_WF3CRC1 0x62
94#define KS_WF3BM0 0x64
95#define KS_WF3BM1 0x66
96#define KS_WF3BM2 0x68
97#define KS_WF3BM3 0x6A
98
99#define KS_TXCR 0x70
100#define TXCR_TCGICMP (1 << 8)
101#define TXCR_TCGUDP (1 << 7)
102#define TXCR_TCGTCP (1 << 6)
103#define TXCR_TCGIP (1 << 5)
104#define TXCR_FTXQ (1 << 4)
105#define TXCR_TXFCE (1 << 3)
106#define TXCR_TXPE (1 << 2)
107#define TXCR_TXCRC (1 << 1)
108#define TXCR_TXE (1 << 0)
109
110#define KS_TXSR 0x72
111#define TXSR_TXLC (1 << 13)
112#define TXSR_TXMC (1 << 12)
113#define TXSR_TXFID_MASK (0x3f << 0)
114#define TXSR_TXFID_SHIFT (0)
115#define TXSR_TXFID_GET(_v) (((_v) >> 0) & 0x3f)
116
117
118#define KS_RXCR1 0x74
119#define RXCR1_FRXQ (1 << 15)
120#define RXCR1_RXUDPFCC (1 << 14)
121#define RXCR1_RXTCPFCC (1 << 13)
122#define RXCR1_RXIPFCC (1 << 12)
123#define RXCR1_RXPAFMA (1 << 11)
124#define RXCR1_RXFCE (1 << 10)
125#define RXCR1_RXEFE (1 << 9)
126#define RXCR1_RXMAFMA (1 << 8)
127#define RXCR1_RXBE (1 << 7)
128#define RXCR1_RXME (1 << 6)
129#define RXCR1_RXUE (1 << 5)
130#define RXCR1_RXAE (1 << 4)
131#define RXCR1_RXINVF (1 << 1)
132#define RXCR1_RXE (1 << 0)
133#define RXCR1_FILTER_MASK (RXCR1_RXINVF | RXCR1_RXAE | \
134 RXCR1_RXMAFMA | RXCR1_RXPAFMA)
135
136#define KS_RXCR2 0x76
137#define RXCR2_SRDBL_MASK (0x7 << 5)
138#define RXCR2_SRDBL_SHIFT (5)
139#define RXCR2_SRDBL_4B (0x0 << 5)
140#define RXCR2_SRDBL_8B (0x1 << 5)
141#define RXCR2_SRDBL_16B (0x2 << 5)
142#define RXCR2_SRDBL_32B (0x3 << 5)
143/* #define RXCR2_SRDBL_FRAME (0x4 << 5) */
144#define RXCR2_IUFFP (1 << 4)
145#define RXCR2_RXIUFCEZ (1 << 3)
146#define RXCR2_UDPLFE (1 << 2)
147#define RXCR2_RXICMPFCC (1 << 1)
148#define RXCR2_RXSAF (1 << 0)
149
150#define KS_TXMIR 0x78
151
152#define KS_RXFHSR 0x7C
153#define RXFSHR_RXFV (1 << 15)
154#define RXFSHR_RXICMPFCS (1 << 13)
155#define RXFSHR_RXIPFCS (1 << 12)
156#define RXFSHR_RXTCPFCS (1 << 11)
157#define RXFSHR_RXUDPFCS (1 << 10)
158#define RXFSHR_RXBF (1 << 7)
159#define RXFSHR_RXMF (1 << 6)
160#define RXFSHR_RXUF (1 << 5)
161#define RXFSHR_RXMR (1 << 4)
162#define RXFSHR_RXFT (1 << 3)
163#define RXFSHR_RXFTL (1 << 2)
164#define RXFSHR_RXRF (1 << 1)
165#define RXFSHR_RXCE (1 << 0)
166#define RXFSHR_ERR (RXFSHR_RXCE | RXFSHR_RXRF |\
167 RXFSHR_RXFTL | RXFSHR_RXMR |\
168 RXFSHR_RXICMPFCS | RXFSHR_RXIPFCS |\
169 RXFSHR_RXTCPFCS)
170#define KS_RXFHBCR 0x7E
171#define RXFHBCR_CNT_MASK 0x0FFF
172
173#define KS_TXQCR 0x80
174#define TXQCR_AETFE (1 << 2)
175#define TXQCR_TXQMAM (1 << 1)
176#define TXQCR_METFE (1 << 0)
177
178#define KS_RXQCR 0x82
179#define RXQCR_RXDTTS (1 << 12)
180#define RXQCR_RXDBCTS (1 << 11)
181#define RXQCR_RXFCTS (1 << 10)
182#define RXQCR_RXIPHTOE (1 << 9)
183#define RXQCR_RXDTTE (1 << 7)
184#define RXQCR_RXDBCTE (1 << 6)
185#define RXQCR_RXFCTE (1 << 5)
186#define RXQCR_ADRFE (1 << 4)
187#define RXQCR_SDA (1 << 3)
188#define RXQCR_RRXEF (1 << 0)
189#define RXQCR_CMD_CNTL (RXQCR_RXFCTE|RXQCR_ADRFE)
190
191#define KS_TXFDPR 0x84
192#define TXFDPR_TXFPAI (1 << 14)
193#define TXFDPR_TXFP_MASK (0x7ff << 0)
194#define TXFDPR_TXFP_SHIFT (0)
195
196#define KS_RXFDPR 0x86
197#define RXFDPR_RXFPAI (1 << 14)
198
199#define KS_RXDTTR 0x8C
200#define KS_RXDBCTR 0x8E
201
202#define KS_IER 0x90
203#define KS_ISR 0x92
204#define IRQ_LCI (1 << 15)
205#define IRQ_TXI (1 << 14)
206#define IRQ_RXI (1 << 13)
207#define IRQ_RXOI (1 << 11)
208#define IRQ_TXPSI (1 << 9)
209#define IRQ_RXPSI (1 << 8)
210#define IRQ_TXSAI (1 << 6)
211#define IRQ_RXWFDI (1 << 5)
212#define IRQ_RXMPDI (1 << 4)
213#define IRQ_LDI (1 << 3)
214#define IRQ_EDI (1 << 2)
215#define IRQ_SPIBEI (1 << 1)
216#define IRQ_DEDI (1 << 0)
217
218#define KS_RXFCTR 0x9C
219#define RXFCTR_THRESHOLD_MASK 0x00FF
220
221#define KS_RXFC 0x9D
222#define RXFCTR_RXFC_MASK (0xff << 8)
223#define RXFCTR_RXFC_SHIFT (8)
224#define RXFCTR_RXFC_GET(_v) (((_v) >> 8) & 0xff)
225#define RXFCTR_RXFCT_MASK (0xff << 0)
226#define RXFCTR_RXFCT_SHIFT (0)
227
228#define KS_TXNTFSR 0x9E
229
230#define KS_MAHTR0 0xA0
231#define KS_MAHTR1 0xA2
232#define KS_MAHTR2 0xA4
233#define KS_MAHTR3 0xA6
234
235#define KS_FCLWR 0xB0
236#define KS_FCHWR 0xB2
237#define KS_FCOWR 0xB4
238
239#define KS_CIDER 0xC0
240#define CIDER_ID 0x8870
241#define CIDER_REV_MASK (0x7 << 1)
242#define CIDER_REV_SHIFT (1)
243#define CIDER_REV_GET(_v) (((_v) >> 1) & 0x7)
244
245#define KS_CGCR 0xC6
246#define KS_IACR 0xC8
247#define IACR_RDEN (1 << 12)
248#define IACR_TSEL_MASK (0x3 << 10)
249#define IACR_TSEL_SHIFT (10)
250#define IACR_TSEL_MIB (0x3 << 10)
251#define IACR_ADDR_MASK (0x1f << 0)
252#define IACR_ADDR_SHIFT (0)
253
254#define KS_IADLR 0xD0
255#define KS_IAHDR 0xD2
256
257#define KS_PMECR 0xD4
258#define PMECR_PME_DELAY (1 << 14)
259#define PMECR_PME_POL (1 << 12)
260#define PMECR_WOL_WAKEUP (1 << 11)
261#define PMECR_WOL_MAGICPKT (1 << 10)
262#define PMECR_WOL_LINKUP (1 << 9)
263#define PMECR_WOL_ENERGY (1 << 8)
264#define PMECR_AUTO_WAKE_EN (1 << 7)
265#define PMECR_WAKEUP_NORMAL (1 << 6)
266#define PMECR_WKEVT_MASK (0xf << 2)
267#define PMECR_WKEVT_SHIFT (2)
268#define PMECR_WKEVT_GET(_v) (((_v) >> 2) & 0xf)
269#define PMECR_WKEVT_ENERGY (0x1 << 2)
270#define PMECR_WKEVT_LINK (0x2 << 2)
271#define PMECR_WKEVT_MAGICPKT (0x4 << 2)
272#define PMECR_WKEVT_FRAME (0x8 << 2)
273#define PMECR_PM_MASK (0x3 << 0)
274#define PMECR_PM_SHIFT (0)
275#define PMECR_PM_NORMAL (0x0 << 0)
276#define PMECR_PM_ENERGY (0x1 << 0)
277#define PMECR_PM_SOFTDOWN (0x2 << 0)
278#define PMECR_PM_POWERSAVE (0x3 << 0)
279
280/* Standard MII PHY data */
281#define KS_P1MBCR 0xE4
282#define P1MBCR_FORCE_FDX (1 << 8)
283
284#define KS_P1MBSR 0xE6
285#define P1MBSR_AN_COMPLETE (1 << 5)
286#define P1MBSR_AN_CAPABLE (1 << 3)
287#define P1MBSR_LINK_UP (1 << 2)
288
289#define KS_PHY1ILR 0xE8
290#define KS_PHY1IHR 0xEA
291#define KS_P1ANAR 0xEC
292#define KS_P1ANLPR 0xEE
293
294#define KS_P1SCLMD 0xF4
295#define P1SCLMD_LEDOFF (1 << 15)
296#define P1SCLMD_TXIDS (1 << 14)
297#define P1SCLMD_RESTARTAN (1 << 13)
298#define P1SCLMD_DISAUTOMDIX (1 << 10)
299#define P1SCLMD_FORCEMDIX (1 << 9)
300#define P1SCLMD_AUTONEGEN (1 << 7)
301#define P1SCLMD_FORCE100 (1 << 6)
302#define P1SCLMD_FORCEFDX (1 << 5)
303#define P1SCLMD_ADV_FLOW (1 << 4)
304#define P1SCLMD_ADV_100BT_FDX (1 << 3)
305#define P1SCLMD_ADV_100BT_HDX (1 << 2)
306#define P1SCLMD_ADV_10BT_FDX (1 << 1)
307#define P1SCLMD_ADV_10BT_HDX (1 << 0)
308
309#define KS_P1CR 0xF6
310#define P1CR_HP_MDIX (1 << 15)
311#define P1CR_REV_POL (1 << 13)
312#define P1CR_OP_100M (1 << 10)
313#define P1CR_OP_FDX (1 << 9)
314#define P1CR_OP_MDI (1 << 7)
315#define P1CR_AN_DONE (1 << 6)
316#define P1CR_LINK_GOOD (1 << 5)
317#define P1CR_PNTR_FLOW (1 << 4)
318#define P1CR_PNTR_100BT_FDX (1 << 3)
319#define P1CR_PNTR_100BT_HDX (1 << 2)
320#define P1CR_PNTR_10BT_FDX (1 << 1)
321#define P1CR_PNTR_10BT_HDX (1 << 0)
322
323/* TX Frame control */
324#define TXFR_TXIC (1 << 15)
325#define TXFR_TXFID_MASK (0x3f << 0)
326#define TXFR_TXFID_SHIFT (0)
327
328#define KS_P1SR 0xF8
329#define P1SR_HP_MDIX (1 << 15)
330#define P1SR_REV_POL (1 << 13)
331#define P1SR_OP_100M (1 << 10)
332#define P1SR_OP_FDX (1 << 9)
333#define P1SR_OP_MDI (1 << 7)
334#define P1SR_AN_DONE (1 << 6)
335#define P1SR_LINK_GOOD (1 << 5)
336#define P1SR_PNTR_FLOW (1 << 4)
337#define P1SR_PNTR_100BT_FDX (1 << 3)
338#define P1SR_PNTR_100BT_HDX (1 << 2)
339#define P1SR_PNTR_10BT_FDX (1 << 1)
340#define P1SR_PNTR_10BT_HDX (1 << 0)
341
342#define ENUM_BUS_NONE 0
343#define ENUM_BUS_8BIT 1
344#define ENUM_BUS_16BIT 2
345#define ENUM_BUS_32BIT 3
346
347#define MAX_MCAST_LST 32
348#define HW_MCAST_SIZE 8
349#define MAC_ADDR_LEN 6
350
351/* Chip ID values */
352struct chip_id {
353 u16 id;
354 char *name;
355};
356
357#endif