| Thomas Chou | 75219d5 | 2015-12-14 20:45:08 +0800 | [diff] [blame] | 1 | * UART (Universal Asynchronous Receiver/Transmitter) |
| 2 | |
| 3 | Required properties: |
| 4 | - compatible : one of: |
| 5 | - "ns8250" |
| 6 | - "ns16450" |
| 7 | - "ns16550a" |
| 8 | - "ns16550" |
| 9 | - "ns16750" |
| 10 | - "ns16850" |
| 11 | - For Tegra20, must contain "nvidia,tegra20-uart" |
| 12 | - For other Tegra, must contain '"nvidia,<chip>-uart", |
| 13 | "nvidia,tegra20-uart"' where <chip> is tegra30, tegra114, tegra124, |
| 14 | tegra132, or tegra210. |
| 15 | - "nxp,lpc3220-uart" |
| 16 | - "ralink,rt2880-uart" |
| 17 | - "ibm,qpace-nwp-serial" |
| 18 | - "altr,16550-FIFO32" |
| 19 | - "altr,16550-FIFO64" |
| 20 | - "altr,16550-FIFO128" |
| 21 | - "fsl,16550-FIFO64" |
| 22 | - "fsl,ns16550" |
| 23 | - "serial" if the port type is unknown. |
| 24 | - reg : offset and length of the register set for the device. |
| 25 | - interrupts : should contain uart interrupt. |
| 26 | - clock-frequency : the input clock frequency for the UART |
| 27 | or |
| 28 | clocks phandle to refer to the clk used as per Documentation/devicetree |
| 29 | /bindings/clock/clock-bindings.txt |
| 30 | |
| 31 | Optional properties: |
| 32 | - current-speed : the current active speed of the UART. |
| 33 | - reg-offset : offset to apply to the mapbase from the start of the registers. |
| 34 | - reg-shift : quantity to shift the register offsets by. |
| 35 | - reg-io-width : the size (in bytes) of the IO accesses that should be |
| 36 | performed on the device. There are some systems that require 32-bit |
| 37 | accesses to the UART (e.g. TI davinci). |
| 38 | - used-by-rtas : set to indicate that the port is in use by the OpenFirmware |
| 39 | RTAS and should not be registered. |
| 40 | - no-loopback-test: set to indicate that the port does not implements loopback |
| 41 | test mode |
| 42 | - fifo-size: the fifo size of the UART. |
| 43 | - auto-flow-control: one way to enable automatic flow control support. The |
| 44 | driver is allowed to detect support for the capability even without this |
| 45 | property. |
| 46 | |
| 47 | Note: |
| 48 | * fsl,ns16550: |
| 49 | ------------ |
| 50 | Freescale DUART is very similar to the PC16552D (and to a |
| 51 | pair of NS16550A), albeit with some nonstandard behavior such as |
| 52 | erratum A-004737 (relating to incorrect BRK handling). |
| 53 | |
| 54 | Represents a single port that is compatible with the DUART found |
| 55 | on many Freescale chips (examples include mpc8349, mpc8548, |
| York Sun | 3c1d218 | 2016-04-04 11:41:26 -0700 | [diff] [blame] | 56 | mpc8641d, p4080 and ls2080a). |
| Thomas Chou | 75219d5 | 2015-12-14 20:45:08 +0800 | [diff] [blame] | 57 | |
| 58 | Example: |
| 59 | |
| 60 | uart@80230000 { |
| 61 | compatible = "ns8250"; |
| 62 | reg = <0x80230000 0x100>; |
| 63 | clock-frequency = <3686400>; |
| 64 | interrupts = <10>; |
| 65 | reg-shift = <2>; |
| 66 | }; |