blob: 41e2a62d12d3d587b9d42e5e0f9c761e0df341b9 [file] [log] [blame]
Wolfgang Denk6cb142f2006-03-12 02:12:27 +01001/*
2 * U-boot - cache.c
3 *
Mike Frysingerb86b3412008-02-19 00:50:58 -05004 * Copyright (c) 2005-2008 Analog Devices Inc.
Wolfgang Denk6cb142f2006-03-12 02:12:27 +01005 *
6 * (C) Copyright 2000-2004
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 *
Mike Frysingerb86b3412008-02-19 00:50:58 -05009 * Licensed under the GPL-2 or later.
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010010 */
11
Aubrey.Li3f0606a2007-03-09 13:38:44 +080012#include <common.h>
13#include <asm/blackfin.h>
Mike Frysinger50f0d212008-08-07 15:21:47 -040014#include <asm/mach-common/bits/mpu.h>
Aubrey.Li3f0606a2007-03-09 13:38:44 +080015
Mike Frysingerb86b3412008-02-19 00:50:58 -050016void flush_cache(unsigned long addr, unsigned long size)
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010017{
Mike Frysingerb86b3412008-02-19 00:50:58 -050018 /* no need to flush stuff in on chip memory (L1/L2/etc...) */
19 if (addr >= 0xE0000000)
Aubrey.Li3f0606a2007-03-09 13:38:44 +080020 return;
21
22 if (icache_status())
Mike Frysingerb86b3412008-02-19 00:50:58 -050023 blackfin_icache_flush_range((void *)addr, (void *)(addr + size));
Aubrey.Li3f0606a2007-03-09 13:38:44 +080024
Mike Frysingerb86b3412008-02-19 00:50:58 -050025 if (dcache_status())
26 blackfin_dcache_flush_range((void *)addr, (void *)(addr + size));
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010027}
Mike Frysinger50f0d212008-08-07 15:21:47 -040028
29void icache_enable(void)
30{
31 bfin_write_IMEM_CONTROL(IMC | ENICPLB);
32 SSYNC();
33}
34
35void icache_disable(void)
36{
37 bfin_write_IMEM_CONTROL(0);
38 SSYNC();
39}
40
41int icache_status(void)
42{
43 return bfin_read_IMEM_CONTROL() & ENICPLB;
44}
45
46void dcache_enable(void)
47{
48 bfin_write_DMEM_CONTROL(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
49 SSYNC();
50}
51
52void dcache_disable(void)
53{
54 bfin_write_DMEM_CONTROL(0);
55 SSYNC();
56}
57
58int dcache_status(void)
59{
60 return bfin_read_DMEM_CONTROL() & ENDCPLB;
61}