Wolfgang Denk | 6cb142f | 2006-03-12 02:12:27 +0100 | [diff] [blame] | 1 | /* |
| 2 | * U-boot - cache.c |
| 3 | * |
Mike Frysinger | b86b341 | 2008-02-19 00:50:58 -0500 | [diff] [blame] | 4 | * Copyright (c) 2005-2008 Analog Devices Inc. |
Wolfgang Denk | 6cb142f | 2006-03-12 02:12:27 +0100 | [diff] [blame] | 5 | * |
| 6 | * (C) Copyright 2000-2004 |
| 7 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 8 | * |
Mike Frysinger | b86b341 | 2008-02-19 00:50:58 -0500 | [diff] [blame] | 9 | * Licensed under the GPL-2 or later. |
Wolfgang Denk | 6cb142f | 2006-03-12 02:12:27 +0100 | [diff] [blame] | 10 | */ |
| 11 | |
Aubrey.Li | 3f0606a | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 12 | #include <common.h> |
| 13 | #include <asm/blackfin.h> |
Mike Frysinger | 50f0d21 | 2008-08-07 15:21:47 -0400 | [diff] [blame^] | 14 | #include <asm/mach-common/bits/mpu.h> |
Aubrey.Li | 3f0606a | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 15 | |
Mike Frysinger | b86b341 | 2008-02-19 00:50:58 -0500 | [diff] [blame] | 16 | void flush_cache(unsigned long addr, unsigned long size) |
Wolfgang Denk | 6cb142f | 2006-03-12 02:12:27 +0100 | [diff] [blame] | 17 | { |
Mike Frysinger | b86b341 | 2008-02-19 00:50:58 -0500 | [diff] [blame] | 18 | /* no need to flush stuff in on chip memory (L1/L2/etc...) */ |
| 19 | if (addr >= 0xE0000000) |
Aubrey.Li | 3f0606a | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 20 | return; |
| 21 | |
| 22 | if (icache_status()) |
Mike Frysinger | b86b341 | 2008-02-19 00:50:58 -0500 | [diff] [blame] | 23 | blackfin_icache_flush_range((void *)addr, (void *)(addr + size)); |
Aubrey.Li | 3f0606a | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 24 | |
Mike Frysinger | b86b341 | 2008-02-19 00:50:58 -0500 | [diff] [blame] | 25 | if (dcache_status()) |
| 26 | blackfin_dcache_flush_range((void *)addr, (void *)(addr + size)); |
Wolfgang Denk | 6cb142f | 2006-03-12 02:12:27 +0100 | [diff] [blame] | 27 | } |
Mike Frysinger | 50f0d21 | 2008-08-07 15:21:47 -0400 | [diff] [blame^] | 28 | |
| 29 | void icache_enable(void) |
| 30 | { |
| 31 | bfin_write_IMEM_CONTROL(IMC | ENICPLB); |
| 32 | SSYNC(); |
| 33 | } |
| 34 | |
| 35 | void icache_disable(void) |
| 36 | { |
| 37 | bfin_write_IMEM_CONTROL(0); |
| 38 | SSYNC(); |
| 39 | } |
| 40 | |
| 41 | int icache_status(void) |
| 42 | { |
| 43 | return bfin_read_IMEM_CONTROL() & ENICPLB; |
| 44 | } |
| 45 | |
| 46 | void dcache_enable(void) |
| 47 | { |
| 48 | bfin_write_DMEM_CONTROL(ACACHE_BCACHE | ENDCPLB | PORT_PREF0); |
| 49 | SSYNC(); |
| 50 | } |
| 51 | |
| 52 | void dcache_disable(void) |
| 53 | { |
| 54 | bfin_write_DMEM_CONTROL(0); |
| 55 | SSYNC(); |
| 56 | } |
| 57 | |
| 58 | int dcache_status(void) |
| 59 | { |
| 60 | return bfin_read_DMEM_CONTROL() & ENDCPLB; |
| 61 | } |