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Sonic Zhang8a6b2722008-11-26 22:16:45 -05001/*
2 * Driver for Blackfin on-chip ATAPI controller.
3 *
4 * Enter bugs at http://blackfin.uclinux.org/
5 *
6 * Copyright (c) 2008 Analog Devices Inc.
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11#include <common.h>
12#include <command.h>
13#include <config.h>
14#include <asm/byteorder.h>
15#include <asm/io.h>
16#include <asm/errno.h>
Mike Frysingerc5dc4822010-06-02 06:00:04 -040017#include <asm/portmux.h>
Sonic Zhang8a6b2722008-11-26 22:16:45 -050018#include <asm/mach-common/bits/pata.h>
19#include <ata.h>
20#include <libata.h>
21#include "pata_bfin.h"
22
23static struct ata_port port[CONFIG_SYS_SATA_MAX_DEVICE];
24
25/**
26 * PIO Mode - Frequency compatibility
27 */
28/* mode: 0 1 2 3 4 */
29static const u32 pio_fsclk[] =
30{ 33333333, 33333333, 33333333, 33333333, 33333333 };
31
32/**
33 * MDMA Mode - Frequency compatibility
34 */
35/* mode: 0 1 2 */
36static const u32 mdma_fsclk[] = { 33333333, 33333333, 33333333 };
37
38/**
39 * UDMA Mode - Frequency compatibility
40 *
41 * UDMA5 - 100 MB/s - SCLK = 133 MHz
42 * UDMA4 - 66 MB/s - SCLK >= 80 MHz
43 * UDMA3 - 44.4 MB/s - SCLK >= 50 MHz
44 * UDMA2 - 33 MB/s - SCLK >= 40 MHz
45 */
46/* mode: 0 1 2 3 4 5 */
47static const u32 udma_fsclk[] =
48{ 33333333, 33333333, 40000000, 50000000, 80000000, 133333333 };
49
50/**
51 * Register transfer timing table
52 */
53/* mode: 0 1 2 3 4 */
54/* Cycle Time */
55static const u32 reg_t0min[] = { 600, 383, 330, 180, 120 };
56/* DIOR/DIOW to end cycle */
57static const u32 reg_t2min[] = { 290, 290, 290, 70, 25 };
58/* DIOR/DIOW asserted pulse width */
59static const u32 reg_teocmin[] = { 290, 290, 290, 80, 70 };
60
61/**
62 * PIO timing table
63 */
64/* mode: 0 1 2 3 4 */
65/* Cycle Time */
66static const u32 pio_t0min[] = { 600, 383, 240, 180, 120 };
67/* Address valid to DIOR/DIORW */
68static const u32 pio_t1min[] = { 70, 50, 30, 30, 25 };
69/* DIOR/DIOW to end cycle */
70static const u32 pio_t2min[] = { 165, 125, 100, 80, 70 };
71/* DIOR/DIOW asserted pulse width */
72static const u32 pio_teocmin[] = { 165, 125, 100, 70, 25 };
73/* DIOW data hold */
74static const u32 pio_t4min[] = { 30, 20, 15, 10, 10 };
75
76/* ******************************************************************
77 * Multiword DMA timing table
78 * ******************************************************************
79 */
80/* mode: 0 1 2 */
81/* Cycle Time */
82static const u32 mdma_t0min[] = { 480, 150, 120 };
83/* DIOR/DIOW asserted pulse width */
84static const u32 mdma_tdmin[] = { 215, 80, 70 };
85/* DMACK to read data released */
86static const u32 mdma_thmin[] = { 20, 15, 10 };
87/* DIOR/DIOW to DMACK hold */
88static const u32 mdma_tjmin[] = { 20, 5, 5 };
89/* DIOR negated pulse width */
90static const u32 mdma_tkrmin[] = { 50, 50, 25 };
91/* DIOR negated pulse width */
92static const u32 mdma_tkwmin[] = { 215, 50, 25 };
93/* CS[1:0] valid to DIOR/DIOW */
94static const u32 mdma_tmmin[] = { 50, 30, 25 };
95/* DMACK to read data released */
96static const u32 mdma_tzmax[] = { 20, 25, 25 };
97
98/**
99 * Ultra DMA timing table
100 */
101/* mode: 0 1 2 3 4 5 */
102static const u32 udma_tcycmin[] = { 112, 73, 54, 39, 25, 17 };
103static const u32 udma_tdvsmin[] = { 70, 48, 31, 20, 7, 5 };
104static const u32 udma_tenvmax[] = { 70, 70, 70, 55, 55, 50 };
105static const u32 udma_trpmin[] = { 160, 125, 100, 100, 100, 85 };
106static const u32 udma_tmin[] = { 5, 5, 5, 5, 3, 3 };
107
108
109static const u32 udma_tmlimin = 20;
110static const u32 udma_tzahmin = 20;
111static const u32 udma_tenvmin = 20;
112static const u32 udma_tackmin = 20;
113static const u32 udma_tssmin = 50;
114
115static void msleep(int count)
116{
117 int i;
118
119 for (i = 0; i < count; i++)
120 udelay(1000);
121}
122
123/**
124 *
125 * Function: num_clocks_min
126 *
127 * Description:
128 * calculate number of SCLK cycles to meet minimum timing
129 */
130static unsigned short num_clocks_min(unsigned long tmin,
131 unsigned long fsclk)
132{
133 unsigned long tmp ;
134 unsigned short result;
135
136 tmp = tmin * (fsclk/1000/1000) / 1000;
137 result = (unsigned short)tmp;
138 if ((tmp*1000*1000) < (tmin*(fsclk/1000)))
139 result++;
140
141 return result;
142}
143
144/**
145 * bfin_set_piomode - Initialize host controller PATA PIO timings
146 * @ap: Port whose timings we are configuring
147 * @pio_mode: mode
148 *
149 * Set PIO mode for device.
150 *
151 * LOCKING:
152 * None (inherited from caller).
153 */
154
155static void bfin_set_piomode(struct ata_port *ap, int pio_mode)
156{
157 int mode = pio_mode - XFER_PIO_0;
158 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
159 unsigned int fsclk = get_sclk();
160 unsigned short teoc_reg, t2_reg, teoc_pio;
161 unsigned short t4_reg, t2_pio, t1_reg;
162 unsigned short n0, n6, t6min = 5;
163
164 /* the most restrictive timing value is t6 and tc, the DIOW - data hold
165 * If one SCLK pulse is longer than this minimum value then register
166 * transfers cannot be supported at this frequency.
167 */
168 n6 = num_clocks_min(t6min, fsclk);
169 if (mode >= 0 && mode <= 4 && n6 >= 1) {
170 debug("set piomode: mode=%d, fsclk=%ud\n", mode, fsclk);
171 /* calculate the timing values for register transfers. */
172 while (mode > 0 && pio_fsclk[mode] > fsclk)
173 mode--;
174
175 /* DIOR/DIOW to end cycle time */
176 t2_reg = num_clocks_min(reg_t2min[mode], fsclk);
177 /* DIOR/DIOW asserted pulse width */
178 teoc_reg = num_clocks_min(reg_teocmin[mode], fsclk);
179 /* Cycle Time */
180 n0 = num_clocks_min(reg_t0min[mode], fsclk);
181
182 /* increase t2 until we meed the minimum cycle length */
183 if (t2_reg + teoc_reg < n0)
184 t2_reg = n0 - teoc_reg;
185
186 /* calculate the timing values for pio transfers. */
187
188 /* DIOR/DIOW to end cycle time */
189 t2_pio = num_clocks_min(pio_t2min[mode], fsclk);
190 /* DIOR/DIOW asserted pulse width */
191 teoc_pio = num_clocks_min(pio_teocmin[mode], fsclk);
192 /* Cycle Time */
193 n0 = num_clocks_min(pio_t0min[mode], fsclk);
194
195 /* increase t2 until we meed the minimum cycle length */
196 if (t2_pio + teoc_pio < n0)
197 t2_pio = n0 - teoc_pio;
198
199 /* Address valid to DIOR/DIORW */
200 t1_reg = num_clocks_min(pio_t1min[mode], fsclk);
201
202 /* DIOW data hold */
203 t4_reg = num_clocks_min(pio_t4min[mode], fsclk);
204
205 ATAPI_SET_REG_TIM_0(base, (teoc_reg<<8 | t2_reg));
206 ATAPI_SET_PIO_TIM_0(base, (t4_reg<<12 | t2_pio<<4 | t1_reg));
207 ATAPI_SET_PIO_TIM_1(base, teoc_pio);
208 if (mode > 2) {
209 ATAPI_SET_CONTROL(base,
210 ATAPI_GET_CONTROL(base) | IORDY_EN);
211 } else {
212 ATAPI_SET_CONTROL(base,
213 ATAPI_GET_CONTROL(base) & ~IORDY_EN);
214 }
215
216 /* Disable host ATAPI PIO interrupts */
217 ATAPI_SET_INT_MASK(base, ATAPI_GET_INT_MASK(base)
218 & ~(PIO_DONE_MASK | HOST_TERM_XFER_MASK));
219 SSYNC();
220 }
221}
222
223/**
224 *
225 * Function: wait_complete
226 *
227 * Description: Waits the interrupt from device
228 *
229 */
230static inline void wait_complete(void __iomem *base, unsigned short mask)
231{
232 unsigned short status;
233 unsigned int i = 0;
234
235 for (i = 0; i < PATA_BFIN_WAIT_TIMEOUT; i++) {
236 status = ATAPI_GET_INT_STATUS(base) & mask;
237 if (status)
238 break;
239 }
240
241 ATAPI_SET_INT_STATUS(base, mask);
242}
243
244/**
245 *
246 * Function: write_atapi_register
247 *
248 * Description: Writes to ATA Device Resgister
249 *
250 */
251
252static void write_atapi_register(void __iomem *base,
253 unsigned long ata_reg, unsigned short value)
254{
255 /* Program the ATA_DEV_TXBUF register with write data (to be
256 * written into the device).
257 */
258 ATAPI_SET_DEV_TXBUF(base, value);
259
260 /* Program the ATA_DEV_ADDR register with address of the
261 * device register (0x01 to 0x0F).
262 */
263 ATAPI_SET_DEV_ADDR(base, ata_reg);
264
265 /* Program the ATA_CTRL register with dir set to write (1)
266 */
267 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | XFER_DIR));
268
269 /* ensure PIO DMA is not set */
270 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
271
272 /* and start the transfer */
273 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
274
275 /* Wait for the interrupt to indicate the end of the transfer.
276 * (We need to wait on and clear rhe ATA_DEV_INT interrupt status)
277 */
278 wait_complete(base, PIO_DONE_INT);
279}
280
281/**
282 *
283 * Function: read_atapi_register
284 *
285 *Description: Reads from ATA Device Resgister
286 *
287 */
288
289static unsigned short read_atapi_register(void __iomem *base,
290 unsigned long ata_reg)
291{
292 /* Program the ATA_DEV_ADDR register with address of the
293 * device register (0x01 to 0x0F).
294 */
295 ATAPI_SET_DEV_ADDR(base, ata_reg);
296
297 /* Program the ATA_CTRL register with dir set to read (0) and
298 */
299 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~XFER_DIR));
300
301 /* ensure PIO DMA is not set */
302 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
303
304 /* and start the transfer */
305 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
306
307 /* Wait for the interrupt to indicate the end of the transfer.
308 * (PIO_DONE interrupt is set and it doesn't seem to matter
309 * that we don't clear it)
310 */
311 wait_complete(base, PIO_DONE_INT);
312
313 /* Read the ATA_DEV_RXBUF register with write data (to be
314 * written into the device).
315 */
316 return ATAPI_GET_DEV_RXBUF(base);
317}
318
319/**
320 *
321 * Function: write_atapi_register_data
322 *
323 * Description: Writes to ATA Device Resgister
324 *
325 */
326
327static void write_atapi_data(void __iomem *base,
328 int len, unsigned short *buf)
329{
330 int i;
331
332 /* Set transfer length to 1 */
333 ATAPI_SET_XFER_LEN(base, 1);
334
335 /* Program the ATA_DEV_ADDR register with address of the
336 * ATA_REG_DATA
337 */
338 ATAPI_SET_DEV_ADDR(base, ATA_REG_DATA);
339
340 /* Program the ATA_CTRL register with dir set to write (1)
341 */
342 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | XFER_DIR));
343
344 /* ensure PIO DMA is not set */
345 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
346
347 for (i = 0; i < len; i++) {
348 /* Program the ATA_DEV_TXBUF register with write data (to be
349 * written into the device).
350 */
351 ATAPI_SET_DEV_TXBUF(base, buf[i]);
352
353 /* and start the transfer */
354 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
355
356 /* Wait for the interrupt to indicate the end of the transfer.
357 * (We need to wait on and clear rhe ATA_DEV_INT
358 * interrupt status)
359 */
360 wait_complete(base, PIO_DONE_INT);
361 }
362}
363
364/**
365 *
366 * Function: read_atapi_register_data
367 *
368 * Description: Reads from ATA Device Resgister
369 *
370 */
371
372static void read_atapi_data(void __iomem *base,
373 int len, unsigned short *buf)
374{
375 int i;
376
377 /* Set transfer length to 1 */
378 ATAPI_SET_XFER_LEN(base, 1);
379
380 /* Program the ATA_DEV_ADDR register with address of the
381 * ATA_REG_DATA
382 */
383 ATAPI_SET_DEV_ADDR(base, ATA_REG_DATA);
384
385 /* Program the ATA_CTRL register with dir set to read (0) and
386 */
387 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~XFER_DIR));
388
389 /* ensure PIO DMA is not set */
390 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
391
392 for (i = 0; i < len; i++) {
393 /* and start the transfer */
394 ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
395
396 /* Wait for the interrupt to indicate the end of the transfer.
397 * (PIO_DONE interrupt is set and it doesn't seem to matter
398 * that we don't clear it)
399 */
400 wait_complete(base, PIO_DONE_INT);
401
402 /* Read the ATA_DEV_RXBUF register with write data (to be
403 * written into the device).
404 */
405 buf[i] = ATAPI_GET_DEV_RXBUF(base);
406 }
407}
408
409/**
410 * bfin_check_status - Read device status reg & clear interrupt
411 * @ap: port where the device is
412 *
413 * Note: Original code is ata_check_status().
414 */
415
416static u8 bfin_check_status(struct ata_port *ap)
417{
418 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
419 return read_atapi_register(base, ATA_REG_STATUS);
420}
421
422/**
423 * bfin_check_altstatus - Read device alternate status reg
424 * @ap: port where the device is
425 */
426
427static u8 bfin_check_altstatus(struct ata_port *ap)
428{
429 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
430 return read_atapi_register(base, ATA_REG_ALTSTATUS);
431}
432
433/**
434 * bfin_ata_busy_wait - Wait for a port status register
435 * @ap: Port to wait for.
436 * @bits: bits that must be clear
437 * @max: number of 10uS waits to perform
438 *
439 * Waits up to max*10 microseconds for the selected bits in the port's
440 * status register to be cleared.
441 * Returns final value of status register.
442 *
443 * LOCKING:
444 * Inherited from caller.
445 */
446static inline u8 bfin_ata_busy_wait(struct ata_port *ap, unsigned int bits,
447 unsigned int max, u8 usealtstatus)
448{
449 u8 status;
450
451 do {
452 udelay(10);
453 if (usealtstatus)
454 status = bfin_check_altstatus(ap);
455 else
456 status = bfin_check_status(ap);
457 max--;
458 } while (status != 0xff && (status & bits) && (max > 0));
459
460 return status;
461}
462
463/**
464 * bfin_ata_busy_sleep - sleep until BSY clears, or timeout
465 * @ap: port containing status register to be polled
466 * @tmout_pat: impatience timeout in msecs
467 * @tmout: overall timeout in msecs
468 *
469 * Sleep until ATA Status register bit BSY clears,
470 * or a timeout occurs.
471 *
472 * RETURNS:
473 * 0 on success, -errno otherwise.
474 */
475static int bfin_ata_busy_sleep(struct ata_port *ap,
476 long tmout_pat, unsigned long tmout)
477{
478 u8 status;
479
480 status = bfin_ata_busy_wait(ap, ATA_BUSY, 300, 0);
481 while (status != 0xff && (status & ATA_BUSY) && tmout_pat > 0) {
482 msleep(50);
483 tmout_pat -= 50;
484 status = bfin_ata_busy_wait(ap, ATA_BUSY, 3, 0);
485 }
486
487 if (status != 0xff && (status & ATA_BUSY))
488 printf("port is slow to respond, please be patient "
489 "(Status 0x%x)\n", status);
490
491 while (status != 0xff && (status & ATA_BUSY) && tmout_pat > 0) {
492 msleep(50);
493 tmout_pat -= 50;
494 status = bfin_check_status(ap);
495 }
496
497 if (status == 0xff)
498 return -ENODEV;
499
500 if (status & ATA_BUSY) {
501 printf("port failed to respond "
502 "(%lu secs, Status 0x%x)\n",
503 DIV_ROUND_UP(tmout, 1000), status);
504 return -EBUSY;
505 }
506
507 return 0;
508}
509
510/**
511 * bfin_dev_select - Select device 0/1 on ATA bus
512 * @ap: ATA channel to manipulate
513 * @device: ATA device (numbered from zero) to select
514 *
515 * Note: Original code is ata_sff_dev_select().
516 */
517
518static void bfin_dev_select(struct ata_port *ap, unsigned int device)
519{
520 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
521 u8 tmp;
522
523
524 if (device == 0)
525 tmp = ATA_DEVICE_OBS;
526 else
527 tmp = ATA_DEVICE_OBS | ATA_DEV1;
528
529 write_atapi_register(base, ATA_REG_DEVICE, tmp);
530 udelay(1);
531}
532
533/**
534 * bfin_devchk - PATA device presence detection
535 * @ap: ATA channel to examine
536 * @device: Device to examine (starting at zero)
537 *
538 * Note: Original code is ata_devchk().
539 */
540
541static unsigned int bfin_devchk(struct ata_port *ap,
542 unsigned int device)
543{
544 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
545 u8 nsect, lbal;
546
547 bfin_dev_select(ap, device);
548
549 write_atapi_register(base, ATA_REG_NSECT, 0x55);
550 write_atapi_register(base, ATA_REG_LBAL, 0xaa);
551
552 write_atapi_register(base, ATA_REG_NSECT, 0xaa);
553 write_atapi_register(base, ATA_REG_LBAL, 0x55);
554
555 write_atapi_register(base, ATA_REG_NSECT, 0x55);
556 write_atapi_register(base, ATA_REG_LBAL, 0xaa);
557
558 nsect = read_atapi_register(base, ATA_REG_NSECT);
559 lbal = read_atapi_register(base, ATA_REG_LBAL);
560
561 if ((nsect == 0x55) && (lbal == 0xaa))
562 return 1; /* we found a device */
563
564 return 0; /* nothing found */
565}
566
567/**
568 * bfin_bus_post_reset - PATA device post reset
569 *
570 * Note: Original code is ata_bus_post_reset().
571 */
572
573static void bfin_bus_post_reset(struct ata_port *ap, unsigned int devmask)
574{
575 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
576 unsigned int dev0 = devmask & (1 << 0);
577 unsigned int dev1 = devmask & (1 << 1);
578 long deadline;
579
580 /* if device 0 was found in ata_devchk, wait for its
581 * BSY bit to clear
582 */
583 if (dev0)
584 bfin_ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
585
586 /* if device 1 was found in ata_devchk, wait for
587 * register access, then wait for BSY to clear
588 */
589 deadline = ATA_TMOUT_BOOT;
590 while (dev1) {
591 u8 nsect, lbal;
592
593 bfin_dev_select(ap, 1);
594 nsect = read_atapi_register(base, ATA_REG_NSECT);
595 lbal = read_atapi_register(base, ATA_REG_LBAL);
596 if ((nsect == 1) && (lbal == 1))
597 break;
598 if (deadline <= 0) {
599 dev1 = 0;
600 break;
601 }
602 msleep(50); /* give drive a breather */
603 deadline -= 50;
604 }
605 if (dev1)
606 bfin_ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
607
608 /* is all this really necessary? */
609 bfin_dev_select(ap, 0);
610 if (dev1)
611 bfin_dev_select(ap, 1);
612 if (dev0)
613 bfin_dev_select(ap, 0);
614}
615
616/**
617 * bfin_bus_softreset - PATA device software reset
618 *
619 * Note: Original code is ata_bus_softreset().
620 */
621
622static unsigned int bfin_bus_softreset(struct ata_port *ap,
623 unsigned int devmask)
624{
625 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
626
627 /* software reset. causes dev0 to be selected */
628 write_atapi_register(base, ATA_REG_CTRL, ap->ctl_reg);
629 udelay(20);
630 write_atapi_register(base, ATA_REG_CTRL, ap->ctl_reg | ATA_SRST);
631 udelay(20);
632 write_atapi_register(base, ATA_REG_CTRL, ap->ctl_reg);
633
634 /* spec mandates ">= 2ms" before checking status.
635 * We wait 150ms, because that was the magic delay used for
636 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
637 * between when the ATA command register is written, and then
638 * status is checked. Because waiting for "a while" before
639 * checking status is fine, post SRST, we perform this magic
640 * delay here as well.
641 *
642 * Old drivers/ide uses the 2mS rule and then waits for ready
643 */
644 msleep(150);
645
646 /* Before we perform post reset processing we want to see if
647 * the bus shows 0xFF because the odd clown forgets the D7
648 * pulldown resistor.
649 */
650 if (bfin_check_status(ap) == 0xFF)
651 return 0;
652
653 bfin_bus_post_reset(ap, devmask);
654
655 return 0;
656}
657
658/**
659 * bfin_softreset - reset host port via ATA SRST
660 * @ap: port to reset
661 *
662 * Note: Original code is ata_sff_softreset().
663 */
664
665static int bfin_softreset(struct ata_port *ap)
666{
667 unsigned int err_mask;
668
669 ap->dev_mask = 0;
670
671 /* determine if device 0/1 are present.
672 * only one device is supported on one port by now.
673 */
674 if (bfin_devchk(ap, 0))
675 ap->dev_mask |= (1 << 0);
676 else if (bfin_devchk(ap, 1))
677 ap->dev_mask |= (1 << 1);
678 else
679 return -ENODEV;
680
681 /* select device 0 again */
682 bfin_dev_select(ap, 0);
683
684 /* issue bus reset */
685 err_mask = bfin_bus_softreset(ap, ap->dev_mask);
686 if (err_mask) {
687 printf("SRST failed (err_mask=0x%x)\n",
688 err_mask);
689 ap->dev_mask = 0;
690 return -EIO;
691 }
692
693 return 0;
694}
695
696/**
697 * bfin_irq_clear - Clear ATAPI interrupt.
698 * @ap: Port associated with this ATA transaction.
699 *
700 * Note: Original code is ata_sff_irq_clear().
701 */
702
703static void bfin_irq_clear(struct ata_port *ap)
704{
705 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
706
707 ATAPI_SET_INT_STATUS(base, ATAPI_GET_INT_STATUS(base)|ATAPI_DEV_INT
708 | MULTI_DONE_INT | UDMAIN_DONE_INT | UDMAOUT_DONE_INT
709 | MULTI_TERM_INT | UDMAIN_TERM_INT | UDMAOUT_TERM_INT);
710}
711
712static u8 bfin_wait_for_irq(struct ata_port *ap, unsigned int max)
713{
714 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
715
716 do {
717 if (ATAPI_GET_INT_STATUS(base) & (ATAPI_DEV_INT
718 | MULTI_DONE_INT | UDMAIN_DONE_INT | UDMAOUT_DONE_INT
719 | MULTI_TERM_INT | UDMAIN_TERM_INT | UDMAOUT_TERM_INT)) {
720 break;
721 }
722 udelay(1000);
723 max--;
724 } while ((max > 0));
725
726 return max == 0;
727}
728
729/**
730 * bfin_ata_reset_port - initialize BFIN ATAPI port.
731 */
732
733static int bfin_ata_reset_port(struct ata_port *ap)
734{
735 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
736 int count;
737 unsigned short status;
738
739 /* Disable all ATAPI interrupts */
740 ATAPI_SET_INT_MASK(base, 0);
741 SSYNC();
742
743 /* Assert the RESET signal 25us*/
744 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | DEV_RST);
745 udelay(30);
746
747 /* Negate the RESET signal for 2ms*/
748 ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) & ~DEV_RST);
749 msleep(2);
750
751 /* Wait on Busy flag to clear */
752 count = 10000000;
753 do {
754 status = read_atapi_register(base, ATA_REG_STATUS);
755 } while (--count && (status & ATA_BUSY));
756
757 /* Enable only ATAPI Device interrupt */
758 ATAPI_SET_INT_MASK(base, 1);
759 SSYNC();
760
761 return !count;
762}
763
764/**
765 *
766 * Function: bfin_config_atapi_gpio
767 *
768 * Description: Configures the ATAPI pins for use
769 *
770 */
771static int bfin_config_atapi_gpio(struct ata_port *ap)
772{
Mike Frysingerc5dc4822010-06-02 06:00:04 -0400773 const unsigned short pins[] = {
774 P_ATAPI_RESET, P_ATAPI_DIOR, P_ATAPI_DIOW, P_ATAPI_CS0,
775 P_ATAPI_CS1, P_ATAPI_DMACK, P_ATAPI_DMARQ, P_ATAPI_INTRQ,
776 P_ATAPI_IORDY, P_ATAPI_D0A, P_ATAPI_D1A, P_ATAPI_D2A,
777 P_ATAPI_D3A, P_ATAPI_D4A, P_ATAPI_D5A, P_ATAPI_D6A,
778 P_ATAPI_D7A, P_ATAPI_D8A, P_ATAPI_D9A, P_ATAPI_D10A,
779 P_ATAPI_D11A, P_ATAPI_D12A, P_ATAPI_D13A, P_ATAPI_D14A,
780 P_ATAPI_D15A, P_ATAPI_A0A, P_ATAPI_A1A, P_ATAPI_A2A, 0,
781 };
Sonic Zhang8a6b2722008-11-26 22:16:45 -0500782
Mike Frysingerc5dc4822010-06-02 06:00:04 -0400783 peripheral_request_list(pins, "pata_bfin");
Sonic Zhang8a6b2722008-11-26 22:16:45 -0500784
785 return 0;
786}
787
788/**
789 * bfin_atapi_probe - attach a bfin atapi interface
790 * @pdev: platform device
791 *
792 * Register a bfin atapi interface.
793 *
794 *
795 * Platform devices are expected to contain 2 resources per port:
796 *
797 * - I/O Base (IORESOURCE_IO)
798 * - IRQ (IORESOURCE_IRQ)
799 *
800 */
801static int bfin_ata_probe_port(struct ata_port *ap)
802{
803 if (bfin_config_atapi_gpio(ap)) {
804 printf("Requesting Peripherals faild\n");
805 return -EFAULT;
806 }
807
808 if (bfin_ata_reset_port(ap)) {
809 printf("Fail to reset ATAPI device\n");
810 return -EFAULT;
811 }
812
813 if (ap->ata_mode >= XFER_PIO_0 && ap->ata_mode <= XFER_PIO_4)
814 bfin_set_piomode(ap, ap->ata_mode);
815 else {
816 printf("Given ATA data transfer mode is not supported.\n");
817 return -EFAULT;
818 }
819
820 return 0;
821}
822
823#define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
824
825static void bfin_ata_identify(struct ata_port *ap, int dev)
826{
827 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
828 u8 status = 0;
829 static u16 iobuf[ATA_SECTOR_WORDS];
830 u64 n_sectors = 0;
831 hd_driveid_t *iop = (hd_driveid_t *)iobuf;
832
833 memset(iobuf, 0, sizeof(iobuf));
834
835 if (!(ap->dev_mask & (1 << dev)))
836 return;
837
838 debug("port=%d dev=%d\n", ap->port_no, dev);
839
840 bfin_dev_select(ap, dev);
841
842 status = 0;
843 /* Device Identify Command */
844 write_atapi_register(base, ATA_REG_CMD, ATA_CMD_ID_ATA);
845 bfin_check_altstatus(ap);
846 udelay(10);
847
848 status = bfin_ata_busy_wait(ap, ATA_BUSY, 1000, 0);
849 if (status & ATA_ERR) {
850 printf("\ndevice not responding\n");
851 ap->dev_mask &= ~(1 << dev);
852 return;
853 }
854
855 read_atapi_data(base, ATA_SECTOR_WORDS, iobuf);
856
857 ata_swap_buf_le16(iobuf, ATA_SECTOR_WORDS);
858
859 /* we require LBA and DMA support (bits 8 & 9 of word 49) */
860 if (!ata_id_has_dma(iobuf) || !ata_id_has_lba(iobuf))
861 printf("ata%u: no dma/lba\n", ap->port_no);
862
863#ifdef DEBUG
864 ata_dump_id(iobuf);
865#endif
866
867 n_sectors = ata_id_n_sectors(iobuf);
868
869 if (n_sectors == 0) {
870 ap->dev_mask &= ~(1 << dev);
871 return;
872 }
873
874 ata_id_c_string(iobuf, (unsigned char *)sata_dev_desc[ap->port_no].revision,
875 ATA_ID_FW_REV, sizeof(sata_dev_desc[ap->port_no].revision));
876 ata_id_c_string(iobuf, (unsigned char *)sata_dev_desc[ap->port_no].vendor,
877 ATA_ID_PROD, sizeof(sata_dev_desc[ap->port_no].vendor));
878 ata_id_c_string(iobuf, (unsigned char *)sata_dev_desc[ap->port_no].product,
879 ATA_ID_SERNO, sizeof(sata_dev_desc[ap->port_no].product));
880
881 if ((iop->config & 0x0080) == 0x0080)
882 sata_dev_desc[ap->port_no].removable = 1;
883 else
884 sata_dev_desc[ap->port_no].removable = 0;
885
886 sata_dev_desc[ap->port_no].lba = (u32) n_sectors;
Mike Frysinger44f67f72012-02-03 08:04:22 -0500887 debug("lba=0x%lx\n", sata_dev_desc[ap->port_no].lba);
Sonic Zhang8a6b2722008-11-26 22:16:45 -0500888
889#ifdef CONFIG_LBA48
890 if (iop->command_set_2 & 0x0400)
891 sata_dev_desc[ap->port_no].lba48 = 1;
892 else
893 sata_dev_desc[ap->port_no].lba48 = 0;
894#endif
895
896 /* assuming HD */
897 sata_dev_desc[ap->port_no].type = DEV_TYPE_HARDDISK;
898 sata_dev_desc[ap->port_no].blksz = ATA_SECT_SIZE;
899 sata_dev_desc[ap->port_no].lun = 0; /* just to fill something in... */
900
901 printf("PATA device#%d %s is found on ata port#%d.\n",
902 ap->port_no%PATA_DEV_NUM_PER_PORT,
903 sata_dev_desc[ap->port_no].vendor,
904 ap->port_no/PATA_DEV_NUM_PER_PORT);
905}
906
907static void bfin_ata_set_Feature_cmd(struct ata_port *ap, int dev)
908{
909 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
910 u8 status = 0;
911
912 if (!(ap->dev_mask & (1 << dev)))
913 return;
914
915 bfin_dev_select(ap, dev);
916
917 write_atapi_register(base, ATA_REG_FEATURE, SETFEATURES_XFER);
918 write_atapi_register(base, ATA_REG_NSECT, ap->ata_mode);
919 write_atapi_register(base, ATA_REG_LBAL, 0);
920 write_atapi_register(base, ATA_REG_LBAM, 0);
921 write_atapi_register(base, ATA_REG_LBAH, 0);
922
923 write_atapi_register(base, ATA_REG_DEVICE, ATA_DEVICE_OBS);
924 write_atapi_register(base, ATA_REG_CMD, ATA_CMD_SET_FEATURES);
925
926 udelay(50);
927 msleep(150);
928
929 status = bfin_ata_busy_wait(ap, ATA_BUSY, 5000, 0);
930 if ((status & (ATA_BUSY | ATA_ERR))) {
931 printf("Error : status 0x%02x\n", status);
932 ap->dev_mask &= ~(1 << dev);
933 }
934}
935
936int scan_sata(int dev)
937{
938 /* dev is the index of each ata device in the system. one PATA port
939 * contains 2 devices. one element in scan_done array indicates one
940 * PATA port. device connected to one PATA port is selected by
941 * bfin_dev_select() before access.
942 */
943 struct ata_port *ap = &port[dev];
944 static int scan_done[(CONFIG_SYS_SATA_MAX_DEVICE+1)/PATA_DEV_NUM_PER_PORT];
945
946 if (scan_done[dev/PATA_DEV_NUM_PER_PORT])
947 return 0;
948
949 /* Check for attached device */
950 if (!bfin_ata_probe_port(ap)) {
951 if (bfin_softreset(ap)) {
952 /* soft reset failed, try a hard one */
953 bfin_ata_reset_port(ap);
954 if (bfin_softreset(ap))
955 scan_done[dev/PATA_DEV_NUM_PER_PORT] = 1;
956 } else {
957 scan_done[dev/PATA_DEV_NUM_PER_PORT] = 1;
958 }
959 }
960 if (scan_done[dev/PATA_DEV_NUM_PER_PORT]) {
961 /* Probe device and set xfer mode */
962 bfin_ata_identify(ap, dev%PATA_DEV_NUM_PER_PORT);
963 bfin_ata_set_Feature_cmd(ap, dev%PATA_DEV_NUM_PER_PORT);
964 init_part(&sata_dev_desc[dev]);
965 return 0;
966 }
967
968 printf("PATA device#%d is not present on ATA port#%d.\n",
969 ap->port_no%PATA_DEV_NUM_PER_PORT,
970 ap->port_no/PATA_DEV_NUM_PER_PORT);
971
972 return -1;
973}
974
975int init_sata(int dev)
976{
977 struct ata_port *ap = &port[dev];
978 static u8 init_done;
979 int res = 1;
980
981 if (init_done)
982 return res;
983
984 init_done = 1;
985
986 switch (dev/PATA_DEV_NUM_PER_PORT) {
987 case 0:
988 ap->ioaddr.ctl_addr = ATAPI_CONTROL;
989 ap->ata_mode = CONFIG_BFIN_ATA_MODE;
990 break;
991 default:
992 printf("Tried to scan unknown port %d.\n", dev);
993 return res;
994 }
995
996 if (ap->ata_mode < XFER_PIO_0 || ap->ata_mode > XFER_PIO_4) {
997 ap->ata_mode = XFER_PIO_4;
998 printf("DMA mode is not supported. Set to PIO mode 4.\n");
999 }
1000
1001 ap->port_no = dev;
1002 ap->ctl_reg = 0x8; /*Default value of control reg */
1003
1004 res = 0;
1005 return res;
1006}
1007
1008/* Read up to 255 sectors
1009 *
1010 * Returns sectors read
1011*/
1012static u8 do_one_read(struct ata_port *ap, u64 blknr, u8 blkcnt, u16 *buffer,
1013 uchar lba48)
1014{
1015 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1016 u8 sr = 0;
1017 u8 status;
1018 u16 err = 0;
1019
1020 if (!(bfin_check_status(ap) & ATA_DRDY)) {
1021 printf("Device ata%d not ready\n", ap->port_no);
1022 return 0;
1023 }
1024
1025 /* Set up transfer */
1026#ifdef CONFIG_LBA48
1027 if (lba48) {
1028 /* write high bits */
1029 write_atapi_register(base, ATA_REG_NSECT, 0);
1030 write_atapi_register(base, ATA_REG_LBAL, (blknr >> 24) & 0xFF);
1031 write_atapi_register(base, ATA_REG_LBAM, (blknr >> 32) & 0xFF);
1032 write_atapi_register(base, ATA_REG_LBAH, (blknr >> 40) & 0xFF);
1033 }
1034#endif
1035 write_atapi_register(base, ATA_REG_NSECT, blkcnt);
1036 write_atapi_register(base, ATA_REG_LBAL, (blknr >> 0) & 0xFF);
1037 write_atapi_register(base, ATA_REG_LBAM, (blknr >> 8) & 0xFF);
1038 write_atapi_register(base, ATA_REG_LBAH, (blknr >> 16) & 0xFF);
1039
1040#ifdef CONFIG_LBA48
1041 if (lba48) {
1042 write_atapi_register(base, ATA_REG_DEVICE, ATA_LBA);
1043 write_atapi_register(base, ATA_REG_CMD, ATA_CMD_PIO_READ_EXT);
1044 } else
1045#endif
1046 {
1047 write_atapi_register(base, ATA_REG_DEVICE, ATA_LBA | ((blknr >> 24) & 0xF));
1048 write_atapi_register(base, ATA_REG_CMD, ATA_CMD_PIO_READ);
1049 }
1050 status = bfin_ata_busy_wait(ap, ATA_BUSY, 500000, 1);
1051
1052 if (status & (ATA_BUSY | ATA_ERR)) {
1053 printf("Device %d not responding status 0x%x.\n", ap->port_no, status);
1054 err = read_atapi_register(base, ATA_REG_ERR);
1055 printf("Error reg = 0x%x\n", err);
1056 return sr;
1057 }
1058
1059 while (blkcnt--) {
1060 if (bfin_wait_for_irq(ap, 500)) {
1061 printf("ata%u irq failed\n", ap->port_no);
1062 return sr;
1063 }
1064
1065 status = bfin_check_status(ap);
1066 if (status & ATA_ERR) {
1067 err = read_atapi_register(base, ATA_REG_ERR);
1068 printf("ata%u error %d\n", ap->port_no, err);
1069 return sr;
1070 }
1071 bfin_irq_clear(ap);
1072
1073 /* Read one sector */
1074 read_atapi_data(base, ATA_SECTOR_WORDS, buffer);
1075 buffer += ATA_SECTOR_WORDS;
1076 sr++;
1077 }
1078
1079 return sr;
1080}
1081
1082ulong sata_read(int dev, ulong block, ulong blkcnt, void *buff)
1083{
1084 struct ata_port *ap = &port[dev];
1085 ulong n = 0, sread;
1086 u16 *buffer = (u16 *) buff;
1087 u8 status = 0;
1088 u64 blknr = (u64) block;
1089 unsigned char lba48 = 0;
1090
1091#ifdef CONFIG_LBA48
1092 if (blknr > 0xfffffff) {
1093 if (!sata_dev_desc[dev].lba48) {
1094 printf("Drive doesn't support 48-bit addressing\n");
1095 return 0;
1096 }
1097 /* more than 28 bits used, use 48bit mode */
1098 lba48 = 1;
1099 }
1100#endif
1101 bfin_dev_select(ap, dev%PATA_DEV_NUM_PER_PORT);
1102
1103 while (blkcnt > 0) {
1104
1105 if (blkcnt > 255)
1106 sread = 255;
1107 else
1108 sread = blkcnt;
1109
1110 status = do_one_read(ap, blknr, sread, buffer, lba48);
1111 if (status != sread) {
1112 printf("Read failed\n");
1113 return n;
1114 }
1115
1116 blkcnt -= sread;
1117 blknr += sread;
1118 n += sread;
1119 buffer += sread * ATA_SECTOR_WORDS;
1120 }
1121 return n;
1122}
1123
1124ulong sata_write(int dev, ulong block, ulong blkcnt, const void *buff)
1125{
1126 struct ata_port *ap = &port[dev];
1127 void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
1128 ulong n = 0;
1129 u16 *buffer = (u16 *) buff;
1130 unsigned char status = 0;
1131 u64 blknr = (u64) block;
1132#ifdef CONFIG_LBA48
1133 unsigned char lba48 = 0;
1134
1135 if (blknr > 0xfffffff) {
1136 if (!sata_dev_desc[dev].lba48) {
1137 printf("Drive doesn't support 48-bit addressing\n");
1138 return 0;
1139 }
1140 /* more than 28 bits used, use 48bit mode */
1141 lba48 = 1;
1142 }
1143#endif
1144
1145 bfin_dev_select(ap, dev%PATA_DEV_NUM_PER_PORT);
1146
1147 while (blkcnt-- > 0) {
1148 status = bfin_ata_busy_wait(ap, ATA_BUSY, 50000, 0);
1149 if (status & ATA_BUSY) {
1150 printf("ata%u failed to respond\n", ap->port_no);
1151 return n;
1152 }
1153#ifdef CONFIG_LBA48
1154 if (lba48) {
1155 /* write high bits */
1156 write_atapi_register(base, ATA_REG_NSECT, 0);
1157 write_atapi_register(base, ATA_REG_LBAL,
1158 (blknr >> 24) & 0xFF);
1159 write_atapi_register(base, ATA_REG_LBAM,
1160 (blknr >> 32) & 0xFF);
1161 write_atapi_register(base, ATA_REG_LBAH,
1162 (blknr >> 40) & 0xFF);
1163 }
1164#endif
1165 write_atapi_register(base, ATA_REG_NSECT, 1);
1166 write_atapi_register(base, ATA_REG_LBAL, (blknr >> 0) & 0xFF);
1167 write_atapi_register(base, ATA_REG_LBAM, (blknr >> 8) & 0xFF);
1168 write_atapi_register(base, ATA_REG_LBAH, (blknr >> 16) & 0xFF);
1169#ifdef CONFIG_LBA48
1170 if (lba48) {
1171 write_atapi_register(base, ATA_REG_DEVICE, ATA_LBA);
1172 write_atapi_register(base, ATA_REG_CMD,
1173 ATA_CMD_PIO_WRITE_EXT);
1174 } else
1175#endif
1176 {
1177 write_atapi_register(base, ATA_REG_DEVICE,
1178 ATA_LBA | ((blknr >> 24) & 0xF));
1179 write_atapi_register(base, ATA_REG_CMD,
1180 ATA_CMD_PIO_WRITE);
1181 }
1182
1183 /*may take up to 5 sec */
1184 status = bfin_ata_busy_wait(ap, ATA_BUSY, 50000, 0);
1185 if ((status & (ATA_DRQ | ATA_BUSY | ATA_ERR)) != ATA_DRQ) {
1186 printf("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
1187 ap->port_no, (ulong) blknr, status);
1188 return n;
1189 }
1190
1191 write_atapi_data(base, ATA_SECTOR_WORDS, buffer);
1192 bfin_check_altstatus(ap);
1193 udelay(1);
1194
1195 ++n;
1196 ++blknr;
1197 buffer += ATA_SECTOR_WORDS;
1198 }
1199 return n;
1200}