blob: 9864fd7b5c81e435955483dab1b37671bcb27fdb [file] [log] [blame]
wdenka8bd82d2004-04-18 22:03:42 +00001/*
2 * rtl8169.c : U-Boot driver for the RealTek RTL8169
3 *
4 * Masami Komiya (mkomiya@sonare.it)
5 *
6 * Most part is taken from r8169.c of etherboot
7 *
8 */
9
10/**************************************************************************
11* r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit
12* Written 2003 by Timothy Legge <tlegge@rogers.com>
13*
14* This program is free software; you can redistribute it and/or modify
15* it under the terms of the GNU General Public License as published by
16* the Free Software Foundation; either version 2 of the License, or
17* (at your option) any later version.
18*
19* This program is distributed in the hope that it will be useful,
20* but WITHOUT ANY WARRANTY; without even the implied warranty of
21* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22* GNU General Public License for more details.
23*
24* You should have received a copy of the GNU General Public License
25* along with this program; if not, write to the Free Software
26* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27*
28* Portions of this code based on:
29* r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver
30* for Linux kernel 2.4.x.
31*
32* Written 2002 ShuChen <shuchen@realtek.com.tw>
33* See Linux Driver for full information
34*
35* Linux Driver Version 1.27a, 10.02.2002
36*
37* Thanks to:
38* Jean Chen of RealTek Semiconductor Corp. for
39* providing the evaluation NIC used to develop
40* this driver. RealTek's support for Etherboot
41* is appreciated.
42*
43* REVISION HISTORY:
44* ================
45*
46* v1.0 11-26-2003 timlegge Initial port of Linux driver
47* v1.5 01-17-2004 timlegge Initial driver output cleanup
48*
49* Indent Options: indent -kr -i8
50***************************************************************************/
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +010051/*
52 * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk>
53 * Modified to use le32_to_cpu and cpu_to_le32 properly
54 */
wdenka8bd82d2004-04-18 22:03:42 +000055#include <common.h>
56#include <malloc.h>
57#include <net.h>
Ben Warren02d69892008-08-31 09:49:42 -070058#include <netdev.h>
wdenka8bd82d2004-04-18 22:03:42 +000059#include <asm/io.h>
60#include <pci.h>
61
wdenka8bd82d2004-04-18 22:03:42 +000062#undef DEBUG_RTL8169
63#undef DEBUG_RTL8169_TX
64#undef DEBUG_RTL8169_RX
65
66#define drv_version "v1.5"
67#define drv_date "01-17-2004"
68
69static u32 ioaddr;
70
71/* Condensed operations for readability. */
wdenka8bd82d2004-04-18 22:03:42 +000072#define currticks() get_timer(0)
wdenka8bd82d2004-04-18 22:03:42 +000073
74/* media options */
75#define MAX_UNITS 8
76static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
77
78/* MAC address length*/
79#define MAC_ADDR_LEN 6
80
81/* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/
82#define MAX_ETH_FRAME_SIZE 1536
83
84#define TX_FIFO_THRESH 256 /* In bytes */
85
86#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
87#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
88#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
89#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
90#define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */
91#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
92
93#define NUM_TX_DESC 1 /* Number of Tx descriptor registers */
94#define NUM_RX_DESC 4 /* Number of Rx descriptor registers */
95#define RX_BUF_SIZE 1536 /* Rx Buffer size */
96#define RX_BUF_LEN 8192
97
98#define RTL_MIN_IO_SIZE 0x80
99#define TX_TIMEOUT (6*HZ)
100
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +0100101/* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */
wdenka8bd82d2004-04-18 22:03:42 +0000102#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
103#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
104#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
105#define RTL_R8(reg) readb (ioaddr + (reg))
106#define RTL_R16(reg) readw (ioaddr + (reg))
107#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
108
109#define ETH_FRAME_LEN MAX_ETH_FRAME_SIZE
110#define ETH_ALEN MAC_ADDR_LEN
111#define ETH_ZLEN 60
112
Yoshihiro Shimodad65e34d2009-02-25 14:27:29 +0900113#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, (pci_addr_t)a)
114#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, (phys_addr_t)a)
115
wdenka8bd82d2004-04-18 22:03:42 +0000116enum RTL8169_registers {
117 MAC0 = 0, /* Ethernet hardware address. */
118 MAR0 = 8, /* Multicast filter. */
Yoshihiro Shimodadb70b842008-07-09 21:07:34 +0900119 TxDescStartAddrLow = 0x20,
120 TxDescStartAddrHigh = 0x24,
121 TxHDescStartAddrLow = 0x28,
122 TxHDescStartAddrHigh = 0x2c,
wdenka8bd82d2004-04-18 22:03:42 +0000123 FLASH = 0x30,
124 ERSR = 0x36,
125 ChipCmd = 0x37,
126 TxPoll = 0x38,
127 IntrMask = 0x3C,
128 IntrStatus = 0x3E,
129 TxConfig = 0x40,
130 RxConfig = 0x44,
131 RxMissed = 0x4C,
132 Cfg9346 = 0x50,
133 Config0 = 0x51,
134 Config1 = 0x52,
135 Config2 = 0x53,
136 Config3 = 0x54,
137 Config4 = 0x55,
138 Config5 = 0x56,
139 MultiIntr = 0x5C,
140 PHYAR = 0x60,
141 TBICSR = 0x64,
142 TBI_ANAR = 0x68,
143 TBI_LPAR = 0x6A,
144 PHYstatus = 0x6C,
145 RxMaxSize = 0xDA,
146 CPlusCmd = 0xE0,
Yoshihiro Shimodadb70b842008-07-09 21:07:34 +0900147 RxDescStartAddrLow = 0xE4,
148 RxDescStartAddrHigh = 0xE8,
wdenka8bd82d2004-04-18 22:03:42 +0000149 EarlyTxThres = 0xEC,
150 FuncEvent = 0xF0,
151 FuncEventMask = 0xF4,
152 FuncPresetState = 0xF8,
153 FuncForceEvent = 0xFC,
154};
155
156enum RTL8169_register_content {
157 /*InterruptStatusBits */
158 SYSErr = 0x8000,
159 PCSTimeout = 0x4000,
160 SWInt = 0x0100,
161 TxDescUnavail = 0x80,
162 RxFIFOOver = 0x40,
163 RxUnderrun = 0x20,
164 RxOverflow = 0x10,
165 TxErr = 0x08,
166 TxOK = 0x04,
167 RxErr = 0x02,
168 RxOK = 0x01,
169
170 /*RxStatusDesc */
171 RxRES = 0x00200000,
172 RxCRC = 0x00080000,
173 RxRUNT = 0x00100000,
174 RxRWT = 0x00400000,
175
176 /*ChipCmdBits */
177 CmdReset = 0x10,
178 CmdRxEnb = 0x08,
179 CmdTxEnb = 0x04,
180 RxBufEmpty = 0x01,
181
182 /*Cfg9346Bits */
183 Cfg9346_Lock = 0x00,
184 Cfg9346_Unlock = 0xC0,
185
186 /*rx_mode_bits */
187 AcceptErr = 0x20,
188 AcceptRunt = 0x10,
189 AcceptBroadcast = 0x08,
190 AcceptMulticast = 0x04,
191 AcceptMyPhys = 0x02,
192 AcceptAllPhys = 0x01,
193
194 /*RxConfigBits */
195 RxCfgFIFOShift = 13,
196 RxCfgDMAShift = 8,
197
198 /*TxConfigBits */
199 TxInterFrameGapShift = 24,
200 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
201
202 /*rtl8169_PHYstatus */
203 TBI_Enable = 0x80,
204 TxFlowCtrl = 0x40,
205 RxFlowCtrl = 0x20,
206 _1000bpsF = 0x10,
207 _100bps = 0x08,
208 _10bps = 0x04,
209 LinkStatus = 0x02,
210 FullDup = 0x01,
211
212 /*GIGABIT_PHY_registers */
213 PHY_CTRL_REG = 0,
214 PHY_STAT_REG = 1,
215 PHY_AUTO_NEGO_REG = 4,
216 PHY_1000_CTRL_REG = 9,
217
218 /*GIGABIT_PHY_REG_BIT */
219 PHY_Restart_Auto_Nego = 0x0200,
220 PHY_Enable_Auto_Nego = 0x1000,
221
222 /* PHY_STAT_REG = 1; */
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +0100223 PHY_Auto_Nego_Comp = 0x0020,
wdenka8bd82d2004-04-18 22:03:42 +0000224
225 /* PHY_AUTO_NEGO_REG = 4; */
226 PHY_Cap_10_Half = 0x0020,
227 PHY_Cap_10_Full = 0x0040,
228 PHY_Cap_100_Half = 0x0080,
229 PHY_Cap_100_Full = 0x0100,
230
231 /* PHY_1000_CTRL_REG = 9; */
232 PHY_Cap_1000_Full = 0x0200,
233
234 PHY_Cap_Null = 0x0,
235
236 /*_MediaType*/
237 _10_Half = 0x01,
238 _10_Full = 0x02,
239 _100_Half = 0x04,
240 _100_Full = 0x08,
241 _1000_Full = 0x10,
242
243 /*_TBICSRBit*/
244 TBILinkOK = 0x02000000,
245};
246
247static struct {
248 const char *name;
249 u8 version; /* depend on RTL8169 docs */
250 u32 RxConfigMask; /* should clear the bits supported by this chip */
251} rtl_chip_info[] = {
252 {"RTL-8169", 0x00, 0xff7e1880,},
253 {"RTL-8169", 0x04, 0xff7e1880,},
Nobuhiro Iwamatsud75469d2008-03-08 09:25:49 +0900254 {"RTL-8169", 0x00, 0xff7e1880,},
255 {"RTL-8169s/8110s", 0x02, 0xff7e1880,},
256 {"RTL-8169s/8110s", 0x04, 0xff7e1880,},
257 {"RTL-8169sb/8110sb", 0x10, 0xff7e1880,},
258 {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,},
259 {"RTL-8168b/8111sb", 0x30, 0xff7e1880,},
260 {"RTL-8168b/8111sb", 0x38, 0xff7e1880,},
261 {"RTL-8101e", 0x34, 0xff7e1880,},
262 {"RTL-8100e", 0x32, 0xff7e1880,},
wdenka8bd82d2004-04-18 22:03:42 +0000263};
264
265enum _DescStatusBit {
266 OWNbit = 0x80000000,
267 EORbit = 0x40000000,
268 FSbit = 0x20000000,
269 LSbit = 0x10000000,
270};
271
272struct TxDesc {
273 u32 status;
274 u32 vlan_tag;
275 u32 buf_addr;
276 u32 buf_Haddr;
277};
278
279struct RxDesc {
280 u32 status;
281 u32 vlan_tag;
282 u32 buf_addr;
283 u32 buf_Haddr;
284};
285
286/* Define the TX Descriptor */
287static u8 tx_ring[NUM_TX_DESC * sizeof(struct TxDesc) + 256];
288/* __attribute__ ((aligned(256))); */
289
290/* Create a static buffer of size RX_BUF_SZ for each
291TX Descriptor. All descriptors point to a
292part of this buffer */
293static unsigned char txb[NUM_TX_DESC * RX_BUF_SIZE];
294
295/* Define the RX Descriptor */
296static u8 rx_ring[NUM_RX_DESC * sizeof(struct TxDesc) + 256];
297 /* __attribute__ ((aligned(256))); */
298
299/* Create a static buffer of size RX_BUF_SZ for each
300RX Descriptor All descriptors point to a
301part of this buffer */
302static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE];
303
304struct rtl8169_private {
305 void *mmio_addr; /* memory map physical address */
306 int chipset;
307 unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
308 unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
309 unsigned long dirty_tx;
310 unsigned char *TxDescArrays; /* Index of Tx Descriptor buffer */
311 unsigned char *RxDescArrays; /* Index of Rx Descriptor buffer */
312 struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */
313 struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */
314 unsigned char *RxBufferRings; /* Index of Rx Buffer */
315 unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */
316 unsigned char *Tx_skbuff[NUM_TX_DESC];
317} tpx;
318
319static struct rtl8169_private *tpc;
320
321static const u16 rtl8169_intr_mask =
322 SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr |
323 TxOK | RxErr | RxOK;
324static const unsigned int rtl8169_rx_config =
325 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
326
327static struct pci_device_id supported[] = {
Nobuhiro Iwamatsud75469d2008-03-08 09:25:49 +0900328 {PCI_VENDOR_ID_REALTEK, 0x8167},
wdenka8bd82d2004-04-18 22:03:42 +0000329 {PCI_VENDOR_ID_REALTEK, 0x8169},
330 {}
331};
332
333void mdio_write(int RegAddr, int value)
334{
335 int i;
336
337 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
338 udelay(1000);
339
340 for (i = 2000; i > 0; i--) {
341 /* Check if the RTL8169 has completed writing to the specified MII register */
342 if (!(RTL_R32(PHYAR) & 0x80000000)) {
343 break;
344 } else {
345 udelay(100);
346 }
347 }
348}
349
350int mdio_read(int RegAddr)
351{
352 int i, value = -1;
353
354 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
355 udelay(1000);
356
357 for (i = 2000; i > 0; i--) {
358 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
359 if (RTL_R32(PHYAR) & 0x80000000) {
360 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
361 break;
362 } else {
363 udelay(100);
364 }
365 }
366 return value;
367}
368
wdenka8bd82d2004-04-18 22:03:42 +0000369static int rtl8169_init_board(struct eth_device *dev)
370{
371 int i;
372 u32 tmp;
373
374#ifdef DEBUG_RTL8169
375 printf ("%s\n", __FUNCTION__);
376#endif
377 ioaddr = dev->iobase;
378
379 /* Soft reset the chip. */
380 RTL_W8(ChipCmd, CmdReset);
381
382 /* Check that the chip has finished the reset. */
383 for (i = 1000; i > 0; i--)
384 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
385 break;
386 else
387 udelay(10);
388
389 /* identify chip attached to board */
390 tmp = RTL_R32(TxConfig);
391 tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24;
392
393 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){
394 if (tmp == rtl_chip_info[i].version) {
395 tpc->chipset = i;
396 goto match;
397 }
398 }
399
400 /* if unknown chip, assume array element #0, original RTL-8169 in this case */
401 printf("PCI device %s: unknown chip version, assuming RTL-8169\n", dev->name);
Wolfgang Denk06c53be2008-07-10 13:16:09 +0200402 printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig));
wdenka8bd82d2004-04-18 22:03:42 +0000403 tpc->chipset = 0;
404
405match:
406 return 0;
407}
408
409/**************************************************************************
410RECV - Receive a frame
411***************************************************************************/
412static int rtl_recv(struct eth_device *dev)
413{
414 /* return true if there's an ethernet packet ready to read */
415 /* nic->packet should contain data on return */
416 /* nic->packetlen should contain length of data */
417 int cur_rx;
418 int length = 0;
419
420#ifdef DEBUG_RTL8169_RX
421 printf ("%s\n", __FUNCTION__);
422#endif
423 ioaddr = dev->iobase;
424
425 cur_rx = tpc->cur_rx;
Yoshihiro Shimodad4c02e62009-02-25 14:27:24 +0900426 flush_cache((unsigned long)&tpc->RxDescArray[cur_rx],
427 sizeof(struct RxDesc));
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +0100428 if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) {
429 if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) {
wdenka8bd82d2004-04-18 22:03:42 +0000430 unsigned char rxdata[RX_BUF_LEN];
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +0100431 length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx].
432 status) & 0x00001FFF) - 4;
wdenka8bd82d2004-04-18 22:03:42 +0000433
434 memcpy(rxdata, tpc->RxBufferRing[cur_rx], length);
435 NetReceive(rxdata, length);
436
437 if (cur_rx == NUM_RX_DESC - 1)
438 tpc->RxDescArray[cur_rx].status =
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +0100439 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
wdenka8bd82d2004-04-18 22:03:42 +0000440 else
441 tpc->RxDescArray[cur_rx].status =
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +0100442 cpu_to_le32(OWNbit + RX_BUF_SIZE);
wdenka8bd82d2004-04-18 22:03:42 +0000443 tpc->RxDescArray[cur_rx].buf_addr =
Yoshihiro Shimodad65e34d2009-02-25 14:27:29 +0900444 cpu_to_le32(bus_to_phys(tpc->RxBufferRing[cur_rx]));
Yoshihiro Shimodad4c02e62009-02-25 14:27:24 +0900445 flush_cache((unsigned long)tpc->RxBufferRing[cur_rx],
446 RX_BUF_SIZE);
wdenka8bd82d2004-04-18 22:03:42 +0000447 } else {
448 puts("Error Rx");
449 }
450 cur_rx = (cur_rx + 1) % NUM_RX_DESC;
451 tpc->cur_rx = cur_rx;
452 return 1;
453
Nobuhiro Iwamatsud75469d2008-03-08 09:25:49 +0900454 } else {
455 ushort sts = RTL_R8(IntrStatus);
456 RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr));
457 udelay(100); /* wait */
wdenka8bd82d2004-04-18 22:03:42 +0000458 }
459 tpc->cur_rx = cur_rx;
460 return (0); /* initially as this is called to flush the input */
461}
462
463#define HZ 1000
464/**************************************************************************
465SEND - Transmit a frame
466***************************************************************************/
Joe Hershbergerd1527b52012-05-22 18:09:57 +0000467static int rtl_send(struct eth_device *dev, void *packet, int length)
wdenka8bd82d2004-04-18 22:03:42 +0000468{
469 /* send the packet to destination */
470
471 u32 to;
472 u8 *ptxb;
473 int entry = tpc->cur_tx % NUM_TX_DESC;
474 u32 len = length;
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +0100475 int ret;
wdenka8bd82d2004-04-18 22:03:42 +0000476
477#ifdef DEBUG_RTL8169_TX
478 int stime = currticks();
479 printf ("%s\n", __FUNCTION__);
480 printf("sending %d bytes\n", len);
481#endif
482
483 ioaddr = dev->iobase;
484
485 /* point to the current txb incase multiple tx_rings are used */
486 ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE];
487 memcpy(ptxb, (char *)packet, (int)length);
Yoshihiro Shimodad4c02e62009-02-25 14:27:24 +0900488 flush_cache((unsigned long)ptxb, length);
wdenka8bd82d2004-04-18 22:03:42 +0000489
490 while (len < ETH_ZLEN)
491 ptxb[len++] = '\0';
492
Yoshihiro Shimodadb70b842008-07-09 21:07:34 +0900493 tpc->TxDescArray[entry].buf_Haddr = 0;
Yoshihiro Shimodad65e34d2009-02-25 14:27:29 +0900494 tpc->TxDescArray[entry].buf_addr = cpu_to_le32(bus_to_phys(ptxb));
wdenka8bd82d2004-04-18 22:03:42 +0000495 if (entry != (NUM_TX_DESC - 1)) {
496 tpc->TxDescArray[entry].status =
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +0100497 cpu_to_le32((OWNbit | FSbit | LSbit) |
498 ((len > ETH_ZLEN) ? len : ETH_ZLEN));
wdenka8bd82d2004-04-18 22:03:42 +0000499 } else {
500 tpc->TxDescArray[entry].status =
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +0100501 cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) |
502 ((len > ETH_ZLEN) ? len : ETH_ZLEN));
wdenka8bd82d2004-04-18 22:03:42 +0000503 }
504 RTL_W8(TxPoll, 0x40); /* set polling bit */
505
506 tpc->cur_tx++;
507 to = currticks() + TX_TIMEOUT;
Yoshihiro Shimodad4c02e62009-02-25 14:27:24 +0900508 do {
509 flush_cache((unsigned long)&tpc->TxDescArray[entry],
510 sizeof(struct TxDesc));
511 } while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit)
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +0100512 && (currticks() < to)); /* wait */
wdenka8bd82d2004-04-18 22:03:42 +0000513
514 if (currticks() >= to) {
515#ifdef DEBUG_RTL8169_TX
516 puts ("tx timeout/error\n");
517 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime);
518#endif
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +0100519 ret = 0;
wdenka8bd82d2004-04-18 22:03:42 +0000520 } else {
521#ifdef DEBUG_RTL8169_TX
522 puts("tx done\n");
523#endif
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +0100524 ret = length;
wdenka8bd82d2004-04-18 22:03:42 +0000525 }
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +0100526 /* Delay to make net console (nc) work properly */
527 udelay(20);
528 return ret;
wdenka8bd82d2004-04-18 22:03:42 +0000529}
530
531static void rtl8169_set_rx_mode(struct eth_device *dev)
532{
533 u32 mc_filter[2]; /* Multicast hash filter */
534 int rx_mode;
535 u32 tmp = 0;
536
537#ifdef DEBUG_RTL8169
538 printf ("%s\n", __FUNCTION__);
539#endif
540
541 /* IFF_ALLMULTI */
542 /* Too many to filter perfectly -- accept all multicasts. */
543 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
544 mc_filter[1] = mc_filter[0] = 0xffffffff;
545
546 tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) &
547 rtl_chip_info[tpc->chipset].RxConfigMask);
548
549 RTL_W32(RxConfig, tmp);
550 RTL_W32(MAR0 + 0, mc_filter[0]);
551 RTL_W32(MAR0 + 4, mc_filter[1]);
552}
553
554static void rtl8169_hw_start(struct eth_device *dev)
555{
556 u32 i;
557
558#ifdef DEBUG_RTL8169
559 int stime = currticks();
560 printf ("%s\n", __FUNCTION__);
561#endif
562
563#if 0
564 /* Soft reset the chip. */
565 RTL_W8(ChipCmd, CmdReset);
566
567 /* Check that the chip has finished the reset. */
568 for (i = 1000; i > 0; i--) {
569 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
570 break;
571 else
572 udelay(10);
573 }
574#endif
575
576 RTL_W8(Cfg9346, Cfg9346_Unlock);
Yoshihiro Shimodadb70b842008-07-09 21:07:34 +0900577
578 /* RTL-8169sb/8110sb or previous version */
579 if (tpc->chipset <= 5)
580 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
581
wdenka8bd82d2004-04-18 22:03:42 +0000582 RTL_W8(EarlyTxThres, EarlyTxThld);
583
584 /* For gigabit rtl8169 */
585 RTL_W16(RxMaxSize, RxPacketMaxSize);
586
587 /* Set Rx Config register */
588 i = rtl8169_rx_config | (RTL_R32(RxConfig) &
589 rtl_chip_info[tpc->chipset].RxConfigMask);
590 RTL_W32(RxConfig, i);
591
592 /* Set DMA burst size and Interframe Gap Time */
593 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
594 (InterFrameGap << TxInterFrameGapShift));
595
596
597 tpc->cur_rx = 0;
598
Yoshihiro Shimodad65e34d2009-02-25 14:27:29 +0900599 RTL_W32(TxDescStartAddrLow, bus_to_phys(tpc->TxDescArray));
Yoshihiro Shimodadb70b842008-07-09 21:07:34 +0900600 RTL_W32(TxDescStartAddrHigh, (unsigned long)0);
Yoshihiro Shimodad65e34d2009-02-25 14:27:29 +0900601 RTL_W32(RxDescStartAddrLow, bus_to_phys(tpc->RxDescArray));
Yoshihiro Shimodadb70b842008-07-09 21:07:34 +0900602 RTL_W32(RxDescStartAddrHigh, (unsigned long)0);
603
604 /* RTL-8169sc/8110sc or later version */
605 if (tpc->chipset > 5)
606 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
607
wdenka8bd82d2004-04-18 22:03:42 +0000608 RTL_W8(Cfg9346, Cfg9346_Lock);
609 udelay(10);
610
611 RTL_W32(RxMissed, 0);
612
613 rtl8169_set_rx_mode(dev);
614
615 /* no early-rx interrupts */
616 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
617
618#ifdef DEBUG_RTL8169
619 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime);
620#endif
621}
622
623static void rtl8169_init_ring(struct eth_device *dev)
624{
625 int i;
626
627#ifdef DEBUG_RTL8169
628 int stime = currticks();
629 printf ("%s\n", __FUNCTION__);
630#endif
631
632 tpc->cur_rx = 0;
633 tpc->cur_tx = 0;
634 tpc->dirty_tx = 0;
635 memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc));
636 memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc));
637
638 for (i = 0; i < NUM_TX_DESC; i++) {
639 tpc->Tx_skbuff[i] = &txb[i];
640 }
641
642 for (i = 0; i < NUM_RX_DESC; i++) {
643 if (i == (NUM_RX_DESC - 1))
644 tpc->RxDescArray[i].status =
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +0100645 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
wdenka8bd82d2004-04-18 22:03:42 +0000646 else
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +0100647 tpc->RxDescArray[i].status =
648 cpu_to_le32(OWNbit + RX_BUF_SIZE);
wdenka8bd82d2004-04-18 22:03:42 +0000649
650 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
651 tpc->RxDescArray[i].buf_addr =
Yoshihiro Shimodad65e34d2009-02-25 14:27:29 +0900652 cpu_to_le32(bus_to_phys(tpc->RxBufferRing[i]));
Yoshihiro Shimodad4c02e62009-02-25 14:27:24 +0900653 flush_cache((unsigned long)tpc->RxBufferRing[i], RX_BUF_SIZE);
wdenka8bd82d2004-04-18 22:03:42 +0000654 }
655
656#ifdef DEBUG_RTL8169
657 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime);
658#endif
659}
660
661/**************************************************************************
662RESET - Finish setting up the ethernet interface
663***************************************************************************/
Ben Warren422b1a02008-01-09 18:15:53 -0500664static int rtl_reset(struct eth_device *dev, bd_t *bis)
wdenka8bd82d2004-04-18 22:03:42 +0000665{
666 int i;
wdenka8bd82d2004-04-18 22:03:42 +0000667
668#ifdef DEBUG_RTL8169
669 int stime = currticks();
670 printf ("%s\n", __FUNCTION__);
671#endif
672
673 tpc->TxDescArrays = tx_ring;
wdenka8bd82d2004-04-18 22:03:42 +0000674 /* Tx Desscriptor needs 256 bytes alignment; */
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +0100675 tpc->TxDescArray = (struct TxDesc *) ((unsigned long)(tpc->TxDescArrays +
676 255) & ~255);
wdenka8bd82d2004-04-18 22:03:42 +0000677
678 tpc->RxDescArrays = rx_ring;
679 /* Rx Desscriptor needs 256 bytes alignment; */
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +0100680 tpc->RxDescArray = (struct RxDesc *) ((unsigned long)(tpc->RxDescArrays +
681 255) & ~255);
wdenka8bd82d2004-04-18 22:03:42 +0000682
683 rtl8169_init_ring(dev);
684 rtl8169_hw_start(dev);
685 /* Construct a perfect filter frame with the mac address as first match
686 * and broadcast for all others */
687 for (i = 0; i < 192; i++)
688 txb[i] = 0xFF;
689
690 txb[0] = dev->enetaddr[0];
691 txb[1] = dev->enetaddr[1];
692 txb[2] = dev->enetaddr[2];
693 txb[3] = dev->enetaddr[3];
694 txb[4] = dev->enetaddr[4];
695 txb[5] = dev->enetaddr[5];
696
697#ifdef DEBUG_RTL8169
698 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime);
699#endif
Ben Warren422b1a02008-01-09 18:15:53 -0500700 return 0;
wdenka8bd82d2004-04-18 22:03:42 +0000701}
702
703/**************************************************************************
704HALT - Turn off ethernet interface
705***************************************************************************/
706static void rtl_halt(struct eth_device *dev)
707{
708 int i;
709
710#ifdef DEBUG_RTL8169
711 printf ("%s\n", __FUNCTION__);
712#endif
713
714 ioaddr = dev->iobase;
715
716 /* Stop the chip's Tx and Rx DMA processes. */
717 RTL_W8(ChipCmd, 0x00);
718
719 /* Disable interrupts by clearing the interrupt mask. */
720 RTL_W16(IntrMask, 0x0000);
721
722 RTL_W32(RxMissed, 0);
723
724 tpc->TxDescArrays = NULL;
725 tpc->RxDescArrays = NULL;
726 tpc->TxDescArray = NULL;
727 tpc->RxDescArray = NULL;
728 for (i = 0; i < NUM_RX_DESC; i++) {
729 tpc->RxBufferRing[i] = NULL;
730 }
731}
732
733/**************************************************************************
734INIT - Look for an adapter, this routine's visible to the outside
735***************************************************************************/
736
737#define board_found 1
738#define valid_link 0
739static int rtl_init(struct eth_device *dev, bd_t *bis)
740{
741 static int board_idx = -1;
wdenka8bd82d2004-04-18 22:03:42 +0000742 int i, rc;
743 int option = -1, Cap10_100 = 0, Cap1000 = 0;
744
745#ifdef DEBUG_RTL8169
746 printf ("%s\n", __FUNCTION__);
747#endif
748
749 ioaddr = dev->iobase;
750
751 board_idx++;
752
wdenka8bd82d2004-04-18 22:03:42 +0000753 /* point to private storage */
754 tpc = &tpx;
755
756 rc = rtl8169_init_board(dev);
757 if (rc)
758 return rc;
759
760 /* Get MAC address. FIXME: read EEPROM */
761 for (i = 0; i < MAC_ADDR_LEN; i++)
Mike Frysingerd3f87142009-02-11 19:01:26 -0500762 dev->enetaddr[i] = RTL_R8(MAC0 + i);
wdenka8bd82d2004-04-18 22:03:42 +0000763
764#ifdef DEBUG_RTL8169
Yoshihiro Shimodadb70b842008-07-09 21:07:34 +0900765 printf("chipset = %d\n", tpc->chipset);
wdenka8bd82d2004-04-18 22:03:42 +0000766 printf("MAC Address");
767 for (i = 0; i < MAC_ADDR_LEN; i++)
768 printf(":%02x", dev->enetaddr[i]);
769 putc('\n');
770#endif
771
772#ifdef DEBUG_RTL8169
773 /* Print out some hardware info */
774 printf("%s: at ioaddr 0x%x\n", dev->name, ioaddr);
775#endif
776
777 /* if TBI is not endbled */
778 if (!(RTL_R8(PHYstatus) & TBI_Enable)) {
779 int val = mdio_read(PHY_AUTO_NEGO_REG);
780
781 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
782 /* Force RTL8169 in 10/100/1000 Full/Half mode. */
783 if (option > 0) {
784#ifdef DEBUG_RTL8169
785 printf("%s: Force-mode Enabled.\n", dev->name);
786#endif
787 Cap10_100 = 0, Cap1000 = 0;
788 switch (option) {
789 case _10_Half:
790 Cap10_100 = PHY_Cap_10_Half;
791 Cap1000 = PHY_Cap_Null;
792 break;
793 case _10_Full:
794 Cap10_100 = PHY_Cap_10_Full;
795 Cap1000 = PHY_Cap_Null;
796 break;
797 case _100_Half:
798 Cap10_100 = PHY_Cap_100_Half;
799 Cap1000 = PHY_Cap_Null;
800 break;
801 case _100_Full:
802 Cap10_100 = PHY_Cap_100_Full;
803 Cap1000 = PHY_Cap_Null;
804 break;
805 case _1000_Full:
806 Cap10_100 = PHY_Cap_Null;
807 Cap1000 = PHY_Cap_1000_Full;
808 break;
809 default:
810 break;
811 }
812 mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
813 mdio_write(PHY_1000_CTRL_REG, Cap1000);
814 } else {
815#ifdef DEBUG_RTL8169
816 printf("%s: Auto-negotiation Enabled.\n",
817 dev->name);
818#endif
819 /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
820 mdio_write(PHY_AUTO_NEGO_REG,
821 PHY_Cap_10_Half | PHY_Cap_10_Full |
822 PHY_Cap_100_Half | PHY_Cap_100_Full |
823 (val & 0x1F));
824
825 /* enable 1000 Full Mode */
826 mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full);
827
828 }
829
830 /* Enable auto-negotiation and restart auto-nigotiation */
831 mdio_write(PHY_CTRL_REG,
832 PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego);
833 udelay(100);
834
835 /* wait for auto-negotiation process */
836 for (i = 10000; i > 0; i--) {
837 /* check if auto-negotiation complete */
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +0100838 if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) {
wdenka8bd82d2004-04-18 22:03:42 +0000839 udelay(100);
840 option = RTL_R8(PHYstatus);
841 if (option & _1000bpsF) {
842#ifdef DEBUG_RTL8169
843 printf("%s: 1000Mbps Full-duplex operation.\n",
844 dev->name);
845#endif
846 } else {
847#ifdef DEBUG_RTL8169
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +0100848 printf("%s: %sMbps %s-duplex operation.\n",
849 dev->name,
850 (option & _100bps) ? "100" :
851 "10",
852 (option & FullDup) ? "Full" :
853 "Half");
wdenka8bd82d2004-04-18 22:03:42 +0000854#endif
855 }
856 break;
857 } else {
858 udelay(100);
859 }
860 } /* end for-loop to wait for auto-negotiation process */
861
862 } else {
863 udelay(100);
864#ifdef DEBUG_RTL8169
865 printf
866 ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n",
867 dev->name,
868 (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed");
869#endif
870 }
871
872 return 1;
873}
874
875int rtl8169_initialize(bd_t *bis)
876{
877 pci_dev_t devno;
878 int card_number = 0;
879 struct eth_device *dev;
880 u32 iobase;
881 int idx=0;
882
883 while(1){
884 /* Find RTL8169 */
885 if ((devno = pci_find_devices(supported, idx++)) < 0)
886 break;
887
888 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
889 iobase &= ~0xf;
890
891 debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
892
893 dev = (struct eth_device *)malloc(sizeof *dev);
Nobuhiro Iwamatsuf4eaef72010-10-19 14:03:38 +0900894 if (!dev) {
895 printf("Can not allocate memory of rtl8169\n");
896 break;
897 }
wdenka8bd82d2004-04-18 22:03:42 +0000898
Nobuhiro Iwamatsuf4eaef72010-10-19 14:03:38 +0900899 memset(dev, 0, sizeof(*dev));
wdenka8bd82d2004-04-18 22:03:42 +0000900 sprintf (dev->name, "RTL8169#%d", card_number);
901
902 dev->priv = (void *) devno;
Guennadi Liakhovetski6a5e1d72007-11-20 13:14:20 +0100903 dev->iobase = (int)pci_mem_to_phys(devno, iobase);
wdenka8bd82d2004-04-18 22:03:42 +0000904
905 dev->init = rtl_reset;
906 dev->halt = rtl_halt;
907 dev->send = rtl_send;
908 dev->recv = rtl_recv;
909
910 eth_register (dev);
911
912 rtl_init(dev, bis);
913
914 card_number++;
915 }
916 return card_number;
917}