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Ilya Yanokeb819552012-11-06 13:48:21 +00001/*
2 * MUSB OTG driver DMA controller abstraction
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
Tom Rini5b8031c2016-01-14 22:05:13 -05008 * SPDX-License-Identifier: GPL-2.0
Ilya Yanokeb819552012-11-06 13:48:21 +00009 */
10
11#ifndef __MUSB_DMA_H__
12#define __MUSB_DMA_H__
13
14struct musb_hw_ep;
15
16/*
17 * DMA Controller Abstraction
18 *
19 * DMA Controllers are abstracted to allow use of a variety of different
20 * implementations of DMA, as allowed by the Inventra USB cores. On the
21 * host side, usbcore sets up the DMA mappings and flushes caches; on the
22 * peripheral side, the gadget controller driver does. Responsibilities
23 * of a DMA controller driver include:
24 *
25 * - Handling the details of moving multiple USB packets
26 * in cooperation with the Inventra USB core, including especially
27 * the correct RX side treatment of short packets and buffer-full
28 * states (both of which terminate transfers).
29 *
30 * - Knowing the correlation between dma channels and the
31 * Inventra core's local endpoint resources and data direction.
32 *
33 * - Maintaining a list of allocated/available channels.
34 *
35 * - Updating channel status on interrupts,
36 * whether shared with the Inventra core or separate.
37 */
38
39#define DMA_ADDR_INVALID (~(dma_addr_t)0)
40
Paul Kocialkowski95de1e22015-08-04 17:04:06 +020041#ifndef CONFIG_USB_MUSB_PIO_ONLY
Ilya Yanokeb819552012-11-06 13:48:21 +000042#define is_dma_capable() (1)
43#else
44#define is_dma_capable() (0)
45#endif
46
47#ifdef CONFIG_USB_TI_CPPI_DMA
48#define is_cppi_enabled() 1
49#else
50#define is_cppi_enabled() 0
51#endif
52
53#ifdef CONFIG_USB_TUSB_OMAP_DMA
54#define tusb_dma_omap() 1
55#else
56#define tusb_dma_omap() 0
57#endif
58
59/* Anomaly 05000456 - USB Receive Interrupt Is Not Generated in DMA Mode 1
60 * Only allow DMA mode 1 to be used when the USB will actually generate the
61 * interrupts we expect.
62 */
63#ifdef CONFIG_BLACKFIN
64# undef USE_MODE1
65# if !ANOMALY_05000456
66# define USE_MODE1
67# endif
68#endif
69
70/*
71 * DMA channel status ... updated by the dma controller driver whenever that
72 * status changes, and protected by the overall controller spinlock.
73 */
74enum dma_channel_status {
75 /* unallocated */
76 MUSB_DMA_STATUS_UNKNOWN,
77 /* allocated ... but not busy, no errors */
78 MUSB_DMA_STATUS_FREE,
79 /* busy ... transactions are active */
80 MUSB_DMA_STATUS_BUSY,
81 /* transaction(s) aborted due to ... dma or memory bus error */
82 MUSB_DMA_STATUS_BUS_ABORT,
83 /* transaction(s) aborted due to ... core error or USB fault */
84 MUSB_DMA_STATUS_CORE_ABORT
85};
86
87struct dma_controller;
88
89/**
90 * struct dma_channel - A DMA channel.
91 * @private_data: channel-private data
92 * @max_len: the maximum number of bytes the channel can move in one
93 * transaction (typically representing many USB maximum-sized packets)
94 * @actual_len: how many bytes have been transferred
95 * @status: current channel status (updated e.g. on interrupt)
96 * @desired_mode: true if mode 1 is desired; false if mode 0 is desired
97 *
98 * channels are associated with an endpoint for the duration of at least
99 * one usb transfer.
100 */
101struct dma_channel {
102 void *private_data;
103 /* FIXME not void* private_data, but a dma_controller * */
104 size_t max_len;
105 size_t actual_len;
106 enum dma_channel_status status;
107 bool desired_mode;
108};
109
110/*
111 * dma_channel_status - return status of dma channel
112 * @c: the channel
113 *
114 * Returns the software's view of the channel status. If that status is BUSY
115 * then it's possible that the hardware has completed (or aborted) a transfer,
116 * so the driver needs to update that status.
117 */
118static inline enum dma_channel_status
119dma_channel_status(struct dma_channel *c)
120{
121 return (is_dma_capable() && c) ? c->status : MUSB_DMA_STATUS_UNKNOWN;
122}
123
124/**
125 * struct dma_controller - A DMA Controller.
126 * @start: call this to start a DMA controller;
127 * return 0 on success, else negative errno
128 * @stop: call this to stop a DMA controller
129 * return 0 on success, else negative errno
130 * @channel_alloc: call this to allocate a DMA channel
131 * @channel_release: call this to release a DMA channel
132 * @channel_abort: call this to abort a pending DMA transaction,
133 * returning it to FREE (but allocated) state
134 *
135 * Controllers manage dma channels.
136 */
137struct dma_controller {
138 int (*start)(struct dma_controller *);
139 int (*stop)(struct dma_controller *);
140 struct dma_channel *(*channel_alloc)(struct dma_controller *,
141 struct musb_hw_ep *, u8 is_tx);
142 void (*channel_release)(struct dma_channel *);
143 int (*channel_program)(struct dma_channel *channel,
144 u16 maxpacket, u8 mode,
145 dma_addr_t dma_addr,
146 u32 length);
147 int (*channel_abort)(struct dma_channel *);
148 int (*is_compatible)(struct dma_channel *channel,
149 u16 maxpacket,
150 void *buf, u32 length);
151};
152
153/* called after channel_program(), may indicate a fault */
154extern void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit);
155
156
157extern struct dma_controller *__init
158dma_controller_create(struct musb *, void __iomem *);
159
160extern void dma_controller_destroy(struct dma_controller *);
161
162#endif /* __MUSB_DMA_H__ */