blob: 28698e0fc0a29ed9b86218119d3449d2744507e7 [file] [log] [blame]
Tom Warren21ef6a12011-05-31 10:30:37 +00001/*
2 * (C) Copyright 2009 SAMSUNG Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
4 * Portions Copyright (C) 2011 NVIDIA Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
22#ifndef __TEGRA2_MMC_H_
23#define __TEGRA2_MMC_H_
24
25#define TEGRA2_SDMMC1_BASE 0xC8000000
26#define TEGRA2_SDMMC2_BASE 0xC8000200
27#define TEGRA2_SDMMC3_BASE 0xC8000400
28#define TEGRA2_SDMMC4_BASE 0xC8000600
29
30#ifndef __ASSEMBLY__
31struct tegra2_mmc {
32 unsigned int sysad; /* _SYSTEM_ADDRESS_0 */
33 unsigned short blksize; /* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */
34 unsigned short blkcnt; /* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */
35 unsigned int argument; /* _ARGUMENT_0 */
36 unsigned short trnmod; /* _CMD_XFER_MODE_0 15:00 xfer mode */
37 unsigned short cmdreg; /* _CMD_XFER_MODE_0 31:16 cmd reg */
38 unsigned int rspreg0; /* _RESPONSE_R0_R1_0 CMD RESP 31:00 */
39 unsigned int rspreg1; /* _RESPONSE_R2_R3_0 CMD RESP 63:32 */
40 unsigned int rspreg2; /* _RESPONSE_R4_R5_0 CMD RESP 95:64 */
41 unsigned int rspreg3; /* _RESPONSE_R6_R7_0 CMD RESP 127:96 */
42 unsigned int bdata; /* _BUFFER_DATA_PORT_0 */
43 unsigned int prnsts; /* _PRESENT_STATE_0 */
44 unsigned char hostctl; /* _POWER_CONTROL_HOST_0 7:00 */
45 unsigned char pwrcon; /* _POWER_CONTROL_HOST_0 15:8 */
46 unsigned char blkgap; /* _POWER_CONTROL_HOST_9 23:16 */
47 unsigned char wakcon; /* _POWER_CONTROL_HOST_0 31:24 */
48 unsigned short clkcon; /* _CLOCK_CONTROL_0 15:00 */
49 unsigned char timeoutcon; /* _TIMEOUT_CTRL 23:16 */
50 unsigned char swrst; /* _SW_RESET_ 31:24 */
51 unsigned int norintsts; /* _INTERRUPT_STATUS_0 */
52 unsigned int norintstsen; /* _INTERRUPT_STATUS_ENABLE_0 */
53 unsigned int norintsigen; /* _INTERRUPT_SIGNAL_ENABLE_0 */
54 unsigned short acmd12errsts; /* _AUTO_CMD12_ERR_STATUS_0 15:00 */
55 unsigned char res1[2]; /* _RESERVED 31:16 */
56 unsigned int capareg; /* _CAPABILITIES_0 */
57 unsigned char res2[4]; /* RESERVED, offset 44h-47h */
58 unsigned int maxcurr; /* _MAXIMUM_CURRENT_0 */
59 unsigned char res3[4]; /* RESERVED, offset 4Ch-4Fh */
60 unsigned short setacmd12err; /* offset 50h */
61 unsigned short setinterr; /* offset 52h */
62 unsigned char admaerr; /* offset 54h */
63 unsigned char res4[3]; /* RESERVED, offset 55h-57h */
64 unsigned long admaaddr; /* offset 58h-5Fh */
65 unsigned char res5[0x9c]; /* RESERVED, offset 60h-FBh */
66 unsigned short slotintstatus; /* offset FCh */
67 unsigned short hcver; /* HOST Version */
68 unsigned char res6[0x100]; /* RESERVED, offset 100h-1FFh */
69};
70
71struct mmc_host {
72 struct tegra2_mmc *reg;
73 unsigned int version; /* SDHCI spec. version */
74 unsigned int clock; /* Current clock (MHz) */
75 unsigned int base; /* Base address, SDMMC1/2/3/4 */
Simon Glass4ed59e72011-09-21 12:40:04 +000076 enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */
Tom Warren21ef6a12011-05-31 10:30:37 +000077};
78
79int tegra2_mmc_init(int dev_index, int bus_width);
80
81#endif /* __ASSEMBLY__ */
82#endif /* __TEGRA2_MMC_H_ */