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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 51b67d06faa670c65de6f29ec5b5aace74b2a047 / . / board / sbc8641d / init.S
blob: c151d7eff879411215098404803bdbc19022376d [file] [log] [blame]
Joe Hamman8ac27322007-08-09 15:10:53 -0500[diff] [blame]1/*
2 * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
3 * Copyright 2007 Embedded Specialties, Inc.
4 * Joe Hamman joe.hamman@embeddedspecialties.com
5 *
6 * Copyright 2004 Freescale Semiconductor.
7 * Jeff Brown
8 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#include <ppc_asm.tmpl>
30#include <ppc_defs.h>
31#include <asm/cache.h>
32#include <asm/mmu.h>
33#include <config.h>
34#include <mpc86xx.h>
35
36/*
37 * LAW(Local Access Window) configuration:
38 *
39 * 0x0000_0000 0x0fff_ffff DDR1 256M
40 * 0x1000_0000 0x1fff_ffff DDR2 256M
41 * 0xe000_0000 0xffff_ffff LBC 512M
42 *
43 * Notes:
44 * CCSRBAR doesn't need a configured Local Access Window.
45 * If flash is 8M at default position (last 8M), no LAW needed.
46 */
47
48# DDR Bank 1
49# #define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
50# #define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
51
52# DDR Bank 2
53# #define LAWBAR2 ((CFG_DDR_SDRAM_BASE2>>12) & 0xffffff)
54# #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
55
56# LBC
57# #define LAWBAR3 ((0xe0000000>>12) & 0xffffff)
58# #define LAWAR3 (LAWAR_EN & (LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_512M)))
59
60/*
61 * LAW (Local Access Window) configuration:
62 *
63 * 0x0000_0000 DDR 256M
64 * 0x1000_0000 DDR2 256M
65 * 0x8000_0000 PCI1 MEM 512M
66 * 0xa000_0000 PCI2 MEM 512M
67 * 0xc000_0000 RapidIO 512M
68 * 0xe200_0000 PCI1 IO 16M
69 * 0xe300_0000 PCI2 IO 16M
70 * 0xf800_0000 CCSRBAR 2M
71 * 0xfe00_0000 FLASH (boot bank) 32M
72 *
73 */
74
75#define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
76#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
77
78#define LAWBAR2 ((CFG_PCI1_MEM_BASE>>12) & 0xffffff)
79#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
80
81#define LAWBAR3 ((CFG_PCI2_MEM_BASE>>12) & 0xffffff)
82#define LAWAR3 (~LAWAR_EN & (LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)))
83
84#define LAWBAR4 ((0xf8000000>>12) & 0xffffff)
85#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M))
86
87#define LAWBAR5 ((CFG_PCI1_IO_BASE>>12) & 0xffffff)
88#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
89
90#define LAWBAR6 ((CFG_PCI2_IO_BASE>>12) & 0xffffff)
91#define LAWAR6 (~LAWAR_EN &( LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)))
92
93#define LAWBAR7 ((0xfe000000 >>12) & 0xffffff)
94#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M))
95
96#define LAWBAR8 ((CFG_DDR_SDRAM_BASE2>>12) & 0xffffff)
97#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
98
99#define LAWBAR9 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
100#define LAWAR9 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
101
102 .section .bootpg, "ax"
103 .globl law_entry
104law_entry:
105 lis r7,CFG_CCSRBAR@h
106 ori r7,r7,CFG_CCSRBAR@l
107
108 addi r4,r7,0
109 addi r5,r7,0
110
111 /* Skip LAWAR0, start at LAWAR1 */
112 lis r6,LAWBAR1@h
113 ori r6,r6,LAWBAR1@l
114 stwu r6, 0xc28(r4)
115
116 lis r6,LAWAR1@h
117 ori r6,r6,LAWAR1@l
118 stwu r6, 0xc30(r5)
119
120 /* LAWBAR2, LAWAR2 */
121 lis r6,LAWBAR2@h
122 ori r6,r6,LAWBAR2@l
123 stwu r6, 0x20(r4)
124
125 lis r6,LAWAR2@h
126 ori r6,r6,LAWAR2@l
127 stwu r6, 0x20(r5)
128
129 /* LAWBAR3, LAWAR3 */
130 lis r6,LAWBAR3@h
131 ori r6,r6,LAWBAR3@l
132 stwu r6, 0x20(r4)
133
134 lis r6,LAWAR3@h
135 ori r6,r6,LAWAR3@l
136 stwu r6, 0x20(r5)
137
138 /* LAWBAR4, LAWAR4 */
139 lis r6,LAWBAR4@h
140 ori r6,r6,LAWBAR4@l
141 stwu r6, 0x20(r4)
142
143 lis r6,LAWAR4@h
144 ori r6,r6,LAWAR4@l
145 stwu r6, 0x20(r5)
146
147 /* LAWBAR5, LAWAR5 */
148 lis r6,LAWBAR5@h
149 ori r6,r6,LAWBAR5@l
150 stwu r6, 0x20(r4)
151
152 lis r6,LAWAR5@h
153 ori r6,r6,LAWAR5@l
154 stwu r6, 0x20(r5)
155
156 /* LAWBAR6, LAWAR6 */
157 lis r6,LAWBAR6@h
158 ori r6,r6,LAWBAR6@l
159 stwu r6, 0x20(r4)
160
161 lis r6,LAWAR6@h
162 ori r6,r6,LAWAR6@l
163 stwu r6, 0x20(r5)
164
165 /* LAWBAR7, LAWAR7 */
166 lis r6,LAWBAR7@h
167 ori r6,r6,LAWBAR7@l
168 stwu r6, 0x20(r4)
169
170 lis r6,LAWAR7@h
171 ori r6,r6,LAWAR7@l
172 stwu r6, 0x20(r5)
173
174 /* LAWBAR8, LAWAR8 */
175 lis r6,LAWBAR8@h
176 ori r6,r6,LAWBAR8@l
177 stwu r6, 0x20(r4)
178
179 lis r6,LAWAR8@h
180 ori r6,r6,LAWAR8@l
181 stwu r6, 0x20(r5)
182
183 /* LAWBAR9, LAWAR9 */
184 lis r6,LAWBAR9@h
185 ori r6,r6,LAWBAR9@l
186 stwu r6, 0x20(r4)
187
188 lis r6,LAWAR9@h
189 ori r6,r6,LAWAR9@l
190 stwu r6, 0x20(r5)
191
192 blr