Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Thierry Reding | 6173c45 | 2014-12-09 22:25:05 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2014 NVIDIA Corporation |
Thierry Reding | 6173c45 | 2014-12-09 22:25:05 -0700 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #define pr_fmt(fmt) "as3722: " fmt |
| 7 | |
| 8 | #include <common.h> |
| 9 | #include <dm.h> |
| 10 | #include <errno.h> |
| 11 | #include <fdtdec.h> |
| 12 | #include <i2c.h> |
Simon Glass | f7ae49f | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 13 | #include <log.h> |
Simon Glass | e3f44f5 | 2017-07-25 08:30:12 -0600 | [diff] [blame] | 14 | #include <dm/lists.h> |
Thierry Reding | 6173c45 | 2014-12-09 22:25:05 -0700 | [diff] [blame] | 15 | #include <power/as3722.h> |
Simon Glass | e3f44f5 | 2017-07-25 08:30:12 -0600 | [diff] [blame] | 16 | #include <power/pmic.h> |
Thierry Reding | 6173c45 | 2014-12-09 22:25:05 -0700 | [diff] [blame] | 17 | |
Simon Glass | e3f44f5 | 2017-07-25 08:30:12 -0600 | [diff] [blame] | 18 | #define AS3722_NUM_OF_REGS 0x92 |
Thierry Reding | 6173c45 | 2014-12-09 22:25:05 -0700 | [diff] [blame] | 19 | |
Simon Glass | e3f44f5 | 2017-07-25 08:30:12 -0600 | [diff] [blame] | 20 | static int as3722_read(struct udevice *dev, uint reg, uint8_t *buff, int len) |
Thierry Reding | 6173c45 | 2014-12-09 22:25:05 -0700 | [diff] [blame] | 21 | { |
Simon Glass | e3f44f5 | 2017-07-25 08:30:12 -0600 | [diff] [blame] | 22 | int ret; |
Thierry Reding | 6173c45 | 2014-12-09 22:25:05 -0700 | [diff] [blame] | 23 | |
Simon Glass | e3f44f5 | 2017-07-25 08:30:12 -0600 | [diff] [blame] | 24 | ret = dm_i2c_read(dev, reg, buff, len); |
| 25 | if (ret < 0) |
| 26 | return ret; |
Thierry Reding | 6173c45 | 2014-12-09 22:25:05 -0700 | [diff] [blame] | 27 | |
| 28 | return 0; |
| 29 | } |
| 30 | |
Simon Glass | e3f44f5 | 2017-07-25 08:30:12 -0600 | [diff] [blame] | 31 | static int as3722_write(struct udevice *dev, uint reg, const uint8_t *buff, |
| 32 | int len) |
Thierry Reding | 6173c45 | 2014-12-09 22:25:05 -0700 | [diff] [blame] | 33 | { |
Simon Glass | e3f44f5 | 2017-07-25 08:30:12 -0600 | [diff] [blame] | 34 | int ret; |
Thierry Reding | 6173c45 | 2014-12-09 22:25:05 -0700 | [diff] [blame] | 35 | |
Simon Glass | e3f44f5 | 2017-07-25 08:30:12 -0600 | [diff] [blame] | 36 | ret = dm_i2c_write(dev, reg, buff, len); |
| 37 | if (ret < 0) |
| 38 | return ret; |
Thierry Reding | 6173c45 | 2014-12-09 22:25:05 -0700 | [diff] [blame] | 39 | |
| 40 | return 0; |
| 41 | } |
| 42 | |
Simon Glass | e3f44f5 | 2017-07-25 08:30:12 -0600 | [diff] [blame] | 43 | static int as3722_read_id(struct udevice *dev, uint *idp, uint *revisionp) |
Thierry Reding | 6173c45 | 2014-12-09 22:25:05 -0700 | [diff] [blame] | 44 | { |
Simon Glass | e3f44f5 | 2017-07-25 08:30:12 -0600 | [diff] [blame] | 45 | int ret; |
Thierry Reding | 6173c45 | 2014-12-09 22:25:05 -0700 | [diff] [blame] | 46 | |
Simon Glass | e3f44f5 | 2017-07-25 08:30:12 -0600 | [diff] [blame] | 47 | ret = pmic_reg_read(dev, AS3722_ASIC_ID1); |
| 48 | if (ret < 0) { |
Simon Glass | c83c436 | 2018-11-18 08:14:28 -0700 | [diff] [blame] | 49 | pr_err("failed to read ID1 register: %d\n", ret); |
Simon Glass | e3f44f5 | 2017-07-25 08:30:12 -0600 | [diff] [blame] | 50 | return ret; |
Thierry Reding | 6173c45 | 2014-12-09 22:25:05 -0700 | [diff] [blame] | 51 | } |
Simon Glass | e3f44f5 | 2017-07-25 08:30:12 -0600 | [diff] [blame] | 52 | *idp = ret; |
Thierry Reding | 6173c45 | 2014-12-09 22:25:05 -0700 | [diff] [blame] | 53 | |
Simon Glass | e3f44f5 | 2017-07-25 08:30:12 -0600 | [diff] [blame] | 54 | ret = pmic_reg_read(dev, AS3722_ASIC_ID2); |
| 55 | if (ret < 0) { |
Simon Glass | c83c436 | 2018-11-18 08:14:28 -0700 | [diff] [blame] | 56 | pr_err("failed to read ID2 register: %d\n", ret); |
Simon Glass | e3f44f5 | 2017-07-25 08:30:12 -0600 | [diff] [blame] | 57 | return ret; |
Thierry Reding | 6173c45 | 2014-12-09 22:25:05 -0700 | [diff] [blame] | 58 | } |
Simon Glass | e3f44f5 | 2017-07-25 08:30:12 -0600 | [diff] [blame] | 59 | *revisionp = ret; |
Thierry Reding | 6173c45 | 2014-12-09 22:25:05 -0700 | [diff] [blame] | 60 | |
| 61 | return 0; |
| 62 | } |
| 63 | |
Simon Glass | e3f44f5 | 2017-07-25 08:30:12 -0600 | [diff] [blame] | 64 | /* TODO(treding@nvidia.com): Add proper regulator support to avoid this */ |
| 65 | int as3722_sd_set_voltage(struct udevice *dev, unsigned int sd, u8 value) |
Thierry Reding | 6173c45 | 2014-12-09 22:25:05 -0700 | [diff] [blame] | 66 | { |
Simon Glass | e3f44f5 | 2017-07-25 08:30:12 -0600 | [diff] [blame] | 67 | int ret; |
Thierry Reding | 6173c45 | 2014-12-09 22:25:05 -0700 | [diff] [blame] | 68 | |
| 69 | if (sd > 6) |
| 70 | return -EINVAL; |
| 71 | |
Simon Glass | e3f44f5 | 2017-07-25 08:30:12 -0600 | [diff] [blame] | 72 | ret = pmic_reg_write(dev, AS3722_SD_VOLTAGE(sd), value); |
| 73 | if (ret < 0) { |
Simon Glass | c83c436 | 2018-11-18 08:14:28 -0700 | [diff] [blame] | 74 | pr_err("failed to write SD%u voltage register: %d\n", sd, ret); |
Simon Glass | e3f44f5 | 2017-07-25 08:30:12 -0600 | [diff] [blame] | 75 | return ret; |
Thierry Reding | 6173c45 | 2014-12-09 22:25:05 -0700 | [diff] [blame] | 76 | } |
| 77 | |
| 78 | return 0; |
| 79 | } |
| 80 | |
Simon Glass | e3f44f5 | 2017-07-25 08:30:12 -0600 | [diff] [blame] | 81 | int as3722_ldo_set_voltage(struct udevice *dev, unsigned int ldo, u8 value) |
Thierry Reding | 6173c45 | 2014-12-09 22:25:05 -0700 | [diff] [blame] | 82 | { |
Simon Glass | e3f44f5 | 2017-07-25 08:30:12 -0600 | [diff] [blame] | 83 | int ret; |
Thierry Reding | 6173c45 | 2014-12-09 22:25:05 -0700 | [diff] [blame] | 84 | |
| 85 | if (ldo > 11) |
| 86 | return -EINVAL; |
| 87 | |
Simon Glass | e3f44f5 | 2017-07-25 08:30:12 -0600 | [diff] [blame] | 88 | ret = pmic_reg_write(dev, AS3722_LDO_VOLTAGE(ldo), value); |
| 89 | if (ret < 0) { |
Simon Glass | c83c436 | 2018-11-18 08:14:28 -0700 | [diff] [blame] | 90 | pr_err("failed to write LDO%u voltage register: %d\n", ldo, |
| 91 | ret); |
Simon Glass | e3f44f5 | 2017-07-25 08:30:12 -0600 | [diff] [blame] | 92 | return ret; |
Thierry Reding | 6173c45 | 2014-12-09 22:25:05 -0700 | [diff] [blame] | 93 | } |
| 94 | |
| 95 | return 0; |
| 96 | } |
| 97 | |
Simon Glass | e3f44f5 | 2017-07-25 08:30:12 -0600 | [diff] [blame] | 98 | static int as3722_probe(struct udevice *dev) |
Thierry Reding | 6173c45 | 2014-12-09 22:25:05 -0700 | [diff] [blame] | 99 | { |
Simon Glass | e3f44f5 | 2017-07-25 08:30:12 -0600 | [diff] [blame] | 100 | uint id, revision; |
| 101 | int ret; |
Thierry Reding | 6173c45 | 2014-12-09 22:25:05 -0700 | [diff] [blame] | 102 | |
Simon Glass | e3f44f5 | 2017-07-25 08:30:12 -0600 | [diff] [blame] | 103 | ret = as3722_read_id(dev, &id, &revision); |
| 104 | if (ret < 0) { |
Simon Glass | c83c436 | 2018-11-18 08:14:28 -0700 | [diff] [blame] | 105 | pr_err("failed to read ID: %d\n", ret); |
Simon Glass | e3f44f5 | 2017-07-25 08:30:12 -0600 | [diff] [blame] | 106 | return ret; |
Thierry Reding | 6173c45 | 2014-12-09 22:25:05 -0700 | [diff] [blame] | 107 | } |
| 108 | |
| 109 | if (id != AS3722_DEVICE_ID) { |
Simon Glass | c83c436 | 2018-11-18 08:14:28 -0700 | [diff] [blame] | 110 | pr_err("unknown device\n"); |
Thierry Reding | 6173c45 | 2014-12-09 22:25:05 -0700 | [diff] [blame] | 111 | return -ENOENT; |
| 112 | } |
| 113 | |
Simon Glass | e3f44f5 | 2017-07-25 08:30:12 -0600 | [diff] [blame] | 114 | debug("AS3722 revision %#x found on I2C bus %s\n", revision, dev->name); |
Thierry Reding | 6173c45 | 2014-12-09 22:25:05 -0700 | [diff] [blame] | 115 | |
| 116 | return 0; |
| 117 | } |
Simon Glass | e3f44f5 | 2017-07-25 08:30:12 -0600 | [diff] [blame] | 118 | |
| 119 | #if CONFIG_IS_ENABLED(PMIC_CHILDREN) |
| 120 | static const struct pmic_child_info pmic_children_info[] = { |
| 121 | { .prefix = "sd", .driver = "as3722_stepdown"}, |
| 122 | { .prefix = "ldo", .driver = "as3722_ldo"}, |
| 123 | { }, |
| 124 | }; |
| 125 | |
| 126 | static int as3722_bind(struct udevice *dev) |
| 127 | { |
| 128 | struct udevice *gpio_dev; |
| 129 | ofnode regulators_node; |
| 130 | int children; |
| 131 | int ret; |
| 132 | |
| 133 | regulators_node = dev_read_subnode(dev, "regulators"); |
| 134 | if (!ofnode_valid(regulators_node)) { |
| 135 | debug("%s: %s regulators subnode not found\n", __func__, |
| 136 | dev->name); |
| 137 | return -ENXIO; |
| 138 | } |
| 139 | |
| 140 | children = pmic_bind_children(dev, regulators_node, pmic_children_info); |
| 141 | if (!children) |
| 142 | debug("%s: %s - no child found\n", __func__, dev->name); |
| 143 | ret = device_bind_driver(dev, "gpio_as3722", "gpio_as3722", &gpio_dev); |
| 144 | if (ret) { |
| 145 | debug("%s: Cannot bind GPIOs (ret=%d)\n", __func__, ret); |
| 146 | return ret; |
| 147 | } |
| 148 | |
| 149 | return 0; |
| 150 | } |
| 151 | #endif |
| 152 | |
| 153 | static int as3722_reg_count(struct udevice *dev) |
| 154 | { |
| 155 | return AS3722_NUM_OF_REGS; |
| 156 | } |
| 157 | |
| 158 | static struct dm_pmic_ops as3722_ops = { |
| 159 | .reg_count = as3722_reg_count, |
| 160 | .read = as3722_read, |
| 161 | .write = as3722_write, |
| 162 | }; |
| 163 | |
| 164 | static const struct udevice_id as3722_ids[] = { |
| 165 | { .compatible = "ams,as3722" }, |
| 166 | { } |
| 167 | }; |
| 168 | |
| 169 | U_BOOT_DRIVER(pmic_as3722) = { |
| 170 | .name = "as3722_pmic", |
| 171 | .id = UCLASS_PMIC, |
| 172 | .of_match = as3722_ids, |
| 173 | #if CONFIG_IS_ENABLED(PMIC_CHILDREN) |
| 174 | .bind = as3722_bind, |
| 175 | #endif |
| 176 | .probe = as3722_probe, |
| 177 | .ops = &as3722_ops, |
| 178 | }; |