blob: 328b16c277f32540a65b73e22ee730e68153cc99 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
rick7155cd22017-08-28 15:08:01 +08002/*
Rick Chen6720e4a2017-11-23 14:17:35 +08003 * Andestech ATCSPI200 SPI controller driver.
rick7155cd22017-08-28 15:08:01 +08004 *
5 * Copyright 2017 Andes Technology, Inc.
6 * Author: Rick Chen (rick@andestech.com)
rick7155cd22017-08-28 15:08:01 +08007 */
8
rick7155cd22017-08-28 15:08:01 +08009#include <common.h>
Jagan Teki0cbee852019-05-08 19:42:16 +053010#include <clk.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060011#include <log.h>
rick7155cd22017-08-28 15:08:01 +080012#include <malloc.h>
13#include <spi.h>
14#include <asm/io.h>
15#include <dm.h>
16
17DECLARE_GLOBAL_DATA_PTR;
18
19#define MAX_TRANSFER_LEN 512
20#define CHUNK_SIZE 1
21#define SPI_TIMEOUT 0x100000
22#define SPI0_BUS 0
23#define SPI1_BUS 1
24#define SPI0_BASE 0xf0b00000
25#define SPI1_BASE 0xf0f00000
26#define NSPI_MAX_CS_NUM 1
27
Rick Chen6720e4a2017-11-23 14:17:35 +080028struct atcspi200_spi_regs {
rick7155cd22017-08-28 15:08:01 +080029 u32 rev;
30 u32 reserve1[3];
31 u32 format; /* 0x10 */
32#define DATA_LENGTH(x) ((x-1)<<8)
33 u32 pio;
34 u32 reserve2[2];
35 u32 tctrl; /* 0x20 */
36#define TRAMODE_OFFSET 24
37#define TRAMODE_MASK (0x0F<<TRAMODE_OFFSET)
38#define TRAMODE_WR_SYNC (0<<TRAMODE_OFFSET)
39#define TRAMODE_WO (1<<TRAMODE_OFFSET)
40#define TRAMODE_RO (2<<TRAMODE_OFFSET)
41#define TRAMODE_WR (3<<TRAMODE_OFFSET)
42#define TRAMODE_RW (4<<TRAMODE_OFFSET)
43#define TRAMODE_WDR (5<<TRAMODE_OFFSET)
44#define TRAMODE_RDW (6<<TRAMODE_OFFSET)
45#define TRAMODE_NONE (7<<TRAMODE_OFFSET)
46#define TRAMODE_DW (8<<TRAMODE_OFFSET)
47#define TRAMODE_DR (9<<TRAMODE_OFFSET)
48#define WCNT_OFFSET 12
49#define WCNT_MASK (0x1FF<<WCNT_OFFSET)
50#define RCNT_OFFSET 0
51#define RCNT_MASK (0x1FF<<RCNT_OFFSET)
52 u32 cmd;
53 u32 addr;
54 u32 data;
55 u32 ctrl; /* 0x30 */
56#define TXFTH_OFFSET 16
57#define RXFTH_OFFSET 8
58#define TXDMAEN (1<<4)
59#define RXDMAEN (1<<3)
60#define TXFRST (1<<2)
61#define RXFRST (1<<1)
62#define SPIRST (1<<0)
63 u32 status;
64#define TXFFL (1<<23)
65#define TXEPTY (1<<22)
66#define TXFVE_MASK (0x1F<<16)
67#define RXFEM (1<<14)
68#define RXFVE_OFFSET (8)
69#define RXFVE_MASK (0x1F<<RXFVE_OFFSET)
70#define SPIBSY (1<<0)
71 u32 inten;
72 u32 intsta;
73 u32 timing; /* 0x40 */
74#define SCLK_DIV_MASK 0xFF
75};
76
77struct nds_spi_slave {
Rick Chen6720e4a2017-11-23 14:17:35 +080078 volatile struct atcspi200_spi_regs *regs;
rick7155cd22017-08-28 15:08:01 +080079 int to;
80 unsigned int freq;
81 ulong clock;
82 unsigned int mode;
83 u8 num_cs;
84 unsigned int mtiming;
85 size_t cmd_len;
86 u8 cmd_buf[16];
87 size_t data_len;
88 size_t tran_len;
89 u8 *din;
90 u8 *dout;
91 unsigned int max_transfer_length;
92};
93
Rick Chen6720e4a2017-11-23 14:17:35 +080094static int __atcspi200_spi_set_speed(struct nds_spi_slave *ns)
rick7155cd22017-08-28 15:08:01 +080095{
96 u32 tm;
97 u8 div;
98 tm = ns->regs->timing;
99 tm &= ~SCLK_DIV_MASK;
100
101 if(ns->freq >= ns->clock)
102 div =0xff;
103 else{
104 for (div = 0; div < 0xff; div++) {
105 if (ns->freq >= ns->clock / (2 * (div + 1)))
106 break;
107 }
108 }
109
110 tm |= div;
111 ns->regs->timing = tm;
112
113 return 0;
114
115}
116
Rick Chen6720e4a2017-11-23 14:17:35 +0800117static int __atcspi200_spi_claim_bus(struct nds_spi_slave *ns)
rick7155cd22017-08-28 15:08:01 +0800118{
119 unsigned int format=0;
120 ns->regs->ctrl |= (TXFRST|RXFRST|SPIRST);
121 while((ns->regs->ctrl &(TXFRST|RXFRST|SPIRST))&&(ns->to--))
122 if(!ns->to)
123 return -EINVAL;
124
125 ns->cmd_len = 0;
126 format = ns->mode|DATA_LENGTH(8);
127 ns->regs->format = format;
Rick Chen6720e4a2017-11-23 14:17:35 +0800128 __atcspi200_spi_set_speed(ns);
rick7155cd22017-08-28 15:08:01 +0800129
130 return 0;
131}
132
Rick Chen6720e4a2017-11-23 14:17:35 +0800133static int __atcspi200_spi_release_bus(struct nds_spi_slave *ns)
rick7155cd22017-08-28 15:08:01 +0800134{
135 /* do nothing */
136 return 0;
137}
138
Rick Chen6720e4a2017-11-23 14:17:35 +0800139static int __atcspi200_spi_start(struct nds_spi_slave *ns)
rick7155cd22017-08-28 15:08:01 +0800140{
141 int i,olen=0;
142 int tc = ns->regs->tctrl;
143
144 tc &= ~(WCNT_MASK|RCNT_MASK|TRAMODE_MASK);
145 if ((ns->din)&&(ns->cmd_len))
146 tc |= TRAMODE_WR;
147 else if (ns->din)
148 tc |= TRAMODE_RO;
149 else
150 tc |= TRAMODE_WO;
151
152 if(ns->dout)
153 olen = ns->tran_len;
154 tc |= (ns->cmd_len+olen-1) << WCNT_OFFSET;
155
156 if(ns->din)
157 tc |= (ns->tran_len-1) << RCNT_OFFSET;
158
159 ns->regs->tctrl = tc;
160 ns->regs->cmd = 1;
161
162 for (i=0;i<ns->cmd_len;i++)
163 ns->regs->data = ns->cmd_buf[i];
164
165 return 0;
166}
167
Rick Chen6720e4a2017-11-23 14:17:35 +0800168static int __atcspi200_spi_stop(struct nds_spi_slave *ns)
rick7155cd22017-08-28 15:08:01 +0800169{
170 ns->regs->timing = ns->mtiming;
171 while ((ns->regs->status & SPIBSY)&&(ns->to--))
172 if (!ns->to)
173 return -EINVAL;
174
175 return 0;
176}
177
178static void __nspi_espi_tx(struct nds_spi_slave *ns, const void *dout)
179{
180 ns->regs->data = *(u8 *)dout;
181}
182
183static int __nspi_espi_rx(struct nds_spi_slave *ns, void *din, unsigned int bytes)
184{
185 *(u8 *)din = ns->regs->data;
186 return bytes;
187}
188
189
Rick Chen6720e4a2017-11-23 14:17:35 +0800190static int __atcspi200_spi_xfer(struct nds_spi_slave *ns,
rick7155cd22017-08-28 15:08:01 +0800191 unsigned int bitlen, const void *data_out, void *data_in,
192 unsigned long flags)
193{
194 unsigned int event, rx_bytes;
195 const void *dout = NULL;
196 void *din = NULL;
197 int num_blks, num_chunks, max_tran_len, tran_len;
198 int num_bytes;
199 u8 *cmd_buf = ns->cmd_buf;
200 size_t cmd_len = ns->cmd_len;
Rick Chen6083cf32018-05-29 10:40:03 +0800201 unsigned long data_len = bitlen / 8;
rick7155cd22017-08-28 15:08:01 +0800202 int rf_cnt;
203 int ret = 0;
204
205 max_tran_len = ns->max_transfer_length;
206 switch (flags) {
207 case SPI_XFER_BEGIN:
208 cmd_len = ns->cmd_len = data_len;
209 memcpy(cmd_buf, data_out, cmd_len);
210 return 0;
211
212 case 0:
213 case SPI_XFER_END:
214 if (bitlen == 0) {
215 return 0;
216 }
217 ns->data_len = data_len;
218 ns->din = (u8 *)data_in;
219 ns->dout = (u8 *)data_out;
220 break;
221
222 case SPI_XFER_BEGIN | SPI_XFER_END:
223 ns->data_len = 0;
224 ns->din = 0;
225 ns->dout = 0;
226 cmd_len = ns->cmd_len = data_len;
227 memcpy(cmd_buf, data_out, cmd_len);
228 data_out = 0;
229 data_len = 0;
Rick Chen6720e4a2017-11-23 14:17:35 +0800230 __atcspi200_spi_start(ns);
rick7155cd22017-08-28 15:08:01 +0800231 break;
232 }
Heinrich Schuchardt8fad5e02018-03-18 12:41:43 +0100233 if (data_out)
Tom Rini8ada17d2018-05-30 14:51:37 -0400234 debug("spi_xfer: data_out %08X(%p) data_in %08X(%p) data_len %lu\n",
Heinrich Schuchardt8fad5e02018-03-18 12:41:43 +0100235 *(uint *)data_out, data_out, *(uint *)data_in,
236 data_in, data_len);
rick7155cd22017-08-28 15:08:01 +0800237 num_chunks = DIV_ROUND_UP(data_len, max_tran_len);
238 din = data_in;
239 dout = data_out;
240 while (num_chunks--) {
Rick Chen6083cf32018-05-29 10:40:03 +0800241 tran_len = min((size_t)data_len, (size_t)max_tran_len);
rick7155cd22017-08-28 15:08:01 +0800242 ns->tran_len = tran_len;
243 num_blks = DIV_ROUND_UP(tran_len , CHUNK_SIZE);
244 num_bytes = (tran_len) % CHUNK_SIZE;
245 if(num_bytes == 0)
246 num_bytes = CHUNK_SIZE;
Rick Chen6720e4a2017-11-23 14:17:35 +0800247 __atcspi200_spi_start(ns);
rick7155cd22017-08-28 15:08:01 +0800248
249 while (num_blks) {
250 event = in_le32(&ns->regs->status);
251 if ((event & TXEPTY) && (data_out)) {
252 __nspi_espi_tx(ns, dout);
253 num_blks -= CHUNK_SIZE;
254 dout += CHUNK_SIZE;
255 }
256
257 if ((event & RXFVE_MASK) && (data_in)) {
258 rf_cnt = ((event & RXFVE_MASK)>> RXFVE_OFFSET);
259 if (rf_cnt >= CHUNK_SIZE)
260 rx_bytes = CHUNK_SIZE;
261 else if (num_blks == 1 && rf_cnt == num_bytes)
262 rx_bytes = num_bytes;
263 else
264 continue;
265
266 if (__nspi_espi_rx(ns, din, rx_bytes) == rx_bytes) {
267 num_blks -= CHUNK_SIZE;
268 din = (unsigned char *)din + rx_bytes;
269 }
270 }
271 }
272
273 data_len -= tran_len;
274 if(data_len)
275 {
276 ns->cmd_buf[1] += ((tran_len>>16)&0xff);
277 ns->cmd_buf[2] += ((tran_len>>8)&0xff);
278 ns->cmd_buf[3] += ((tran_len)&0xff);
279 ns->data_len = data_len;
280 }
Rick Chen6720e4a2017-11-23 14:17:35 +0800281 ret = __atcspi200_spi_stop(ns);
rick7155cd22017-08-28 15:08:01 +0800282 }
Rick Chen6720e4a2017-11-23 14:17:35 +0800283 ret = __atcspi200_spi_stop(ns);
rick7155cd22017-08-28 15:08:01 +0800284
285 return ret;
286}
287
Rick Chen6720e4a2017-11-23 14:17:35 +0800288static int atcspi200_spi_set_speed(struct udevice *bus, uint max_hz)
rick7155cd22017-08-28 15:08:01 +0800289{
290 struct nds_spi_slave *ns = dev_get_priv(bus);
291
292 debug("%s speed %u\n", __func__, max_hz);
293
294 ns->freq = max_hz;
Rick Chen6720e4a2017-11-23 14:17:35 +0800295 __atcspi200_spi_set_speed(ns);
rick7155cd22017-08-28 15:08:01 +0800296
297 return 0;
298}
299
Rick Chen6720e4a2017-11-23 14:17:35 +0800300static int atcspi200_spi_set_mode(struct udevice *bus, uint mode)
rick7155cd22017-08-28 15:08:01 +0800301{
302 struct nds_spi_slave *ns = dev_get_priv(bus);
303
304 debug("%s mode %u\n", __func__, mode);
305 ns->mode = mode;
306
307 return 0;
308}
309
Rick Chen6720e4a2017-11-23 14:17:35 +0800310static int atcspi200_spi_claim_bus(struct udevice *dev)
rick7155cd22017-08-28 15:08:01 +0800311{
312 struct dm_spi_slave_platdata *slave_plat =
313 dev_get_parent_platdata(dev);
314 struct udevice *bus = dev->parent;
315 struct nds_spi_slave *ns = dev_get_priv(bus);
316
317 if (slave_plat->cs >= ns->num_cs) {
318 printf("Invalid SPI chipselect\n");
319 return -EINVAL;
320 }
321
Rick Chen6720e4a2017-11-23 14:17:35 +0800322 return __atcspi200_spi_claim_bus(ns);
rick7155cd22017-08-28 15:08:01 +0800323}
324
Rick Chen6720e4a2017-11-23 14:17:35 +0800325static int atcspi200_spi_release_bus(struct udevice *dev)
rick7155cd22017-08-28 15:08:01 +0800326{
327 struct nds_spi_slave *ns = dev_get_priv(dev->parent);
328
Rick Chen6720e4a2017-11-23 14:17:35 +0800329 return __atcspi200_spi_release_bus(ns);
rick7155cd22017-08-28 15:08:01 +0800330}
331
Rick Chen6720e4a2017-11-23 14:17:35 +0800332static int atcspi200_spi_xfer(struct udevice *dev, unsigned int bitlen,
rick7155cd22017-08-28 15:08:01 +0800333 const void *dout, void *din,
334 unsigned long flags)
335{
336 struct udevice *bus = dev->parent;
337 struct nds_spi_slave *ns = dev_get_priv(bus);
338
Rick Chen6720e4a2017-11-23 14:17:35 +0800339 return __atcspi200_spi_xfer(ns, bitlen, dout, din, flags);
rick7155cd22017-08-28 15:08:01 +0800340}
341
Rick Chen6720e4a2017-11-23 14:17:35 +0800342static int atcspi200_spi_get_clk(struct udevice *bus)
rick7155cd22017-08-28 15:08:01 +0800343{
344 struct nds_spi_slave *ns = dev_get_priv(bus);
345 struct clk clk;
346 ulong clk_rate;
347 int ret;
348
349 ret = clk_get_by_index(bus, 0, &clk);
350 if (ret)
351 return -EINVAL;
352
353 clk_rate = clk_get_rate(&clk);
354 if (!clk_rate)
355 return -EINVAL;
356
357 ns->clock = clk_rate;
358 clk_free(&clk);
359
360 return 0;
361}
362
Rick Chen6720e4a2017-11-23 14:17:35 +0800363static int atcspi200_spi_probe(struct udevice *bus)
rick7155cd22017-08-28 15:08:01 +0800364{
365 struct nds_spi_slave *ns = dev_get_priv(bus);
366
367 ns->to = SPI_TIMEOUT;
368 ns->max_transfer_length = MAX_TRANSFER_LEN;
369 ns->mtiming = ns->regs->timing;
Rick Chen6720e4a2017-11-23 14:17:35 +0800370 atcspi200_spi_get_clk(bus);
rick7155cd22017-08-28 15:08:01 +0800371
372 return 0;
373}
374
Rick Chen6720e4a2017-11-23 14:17:35 +0800375static int atcspi200_ofdata_to_platadata(struct udevice *bus)
rick7155cd22017-08-28 15:08:01 +0800376{
377 struct nds_spi_slave *ns = dev_get_priv(bus);
378 const void *blob = gd->fdt_blob;
379 int node = dev_of_offset(bus);
380
381 ns->regs = map_physmem(devfdt_get_addr(bus),
Rick Chen6720e4a2017-11-23 14:17:35 +0800382 sizeof(struct atcspi200_spi_regs),
rick7155cd22017-08-28 15:08:01 +0800383 MAP_NOCACHE);
384 if (!ns->regs) {
385 printf("%s: could not map device address\n", __func__);
386 return -EINVAL;
387 }
388 ns->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
389
390 return 0;
391}
392
Rick Chen6720e4a2017-11-23 14:17:35 +0800393static const struct dm_spi_ops atcspi200_spi_ops = {
394 .claim_bus = atcspi200_spi_claim_bus,
395 .release_bus = atcspi200_spi_release_bus,
396 .xfer = atcspi200_spi_xfer,
397 .set_speed = atcspi200_spi_set_speed,
398 .set_mode = atcspi200_spi_set_mode,
rick7155cd22017-08-28 15:08:01 +0800399};
400
Rick Chen6720e4a2017-11-23 14:17:35 +0800401static const struct udevice_id atcspi200_spi_ids[] = {
rick7155cd22017-08-28 15:08:01 +0800402 { .compatible = "andestech,atcspi200" },
403 { }
404};
405
Rick Chen6720e4a2017-11-23 14:17:35 +0800406U_BOOT_DRIVER(atcspi200_spi) = {
407 .name = "atcspi200_spi",
rick7155cd22017-08-28 15:08:01 +0800408 .id = UCLASS_SPI,
Rick Chen6720e4a2017-11-23 14:17:35 +0800409 .of_match = atcspi200_spi_ids,
410 .ops = &atcspi200_spi_ops,
411 .ofdata_to_platdata = atcspi200_ofdata_to_platadata,
rick7155cd22017-08-28 15:08:01 +0800412 .priv_auto_alloc_size = sizeof(struct nds_spi_slave),
Rick Chen6720e4a2017-11-23 14:17:35 +0800413 .probe = atcspi200_spi_probe,
rick7155cd22017-08-28 15:08:01 +0800414};