| Nobuhiro Iwamatsu | e92c9518 | 2008-03-12 12:15:29 +0900 | [diff] [blame] | 1 | #ifndef __ASM_SH_CACHE_H |
| 2 | #define __ASM_SH_CACHE_H |
| 3 | |
| Masahiro Yamada | 7d23666 | 2014-11-06 15:55:21 +0900 | [diff] [blame] | 4 | #if defined(CONFIG_CPU_SH4) |
| Nobuhiro Iwamatsu | e92c9518 | 2008-03-12 12:15:29 +0900 | [diff] [blame] | 5 | |
| Nobuhiro Iwamatsu | b5d10a1 | 2008-09-18 19:34:36 +0900 | [diff] [blame] | 6 | int cache_control(unsigned int cmd); |
| 7 | |
| Nobuhiro Iwamatsu | e92c9518 | 2008-03-12 12:15:29 +0900 | [diff] [blame] | 8 | #define L1_CACHE_BYTES 32 |
| Anton Staaf | 2482e3c | 2011-10-17 16:46:07 -0700 | [diff] [blame] | 9 | |
| Nobuhiro Iwamatsu | e92c9518 | 2008-03-12 12:15:29 +0900 | [diff] [blame] | 10 | struct __large_struct { unsigned long buf[100]; }; |
| 11 | #define __m(x) (*(struct __large_struct *)(x)) |
| 12 | |
| Anton Staaf | 2482e3c | 2011-10-17 16:46:07 -0700 | [diff] [blame] | 13 | #else |
| 14 | |
| 15 | /* |
| 16 | * 32-bytes is the largest L1 data cache line size for SH the architecture. So |
| 17 | * it is a safe default for DMA alignment. |
| 18 | */ |
| 19 | #define ARCH_DMA_MINALIGN 32 |
| 20 | |
| Masahiro Yamada | 7d23666 | 2014-11-06 15:55:21 +0900 | [diff] [blame] | 21 | #endif /* CONFIG_CPU_SH4 */ |
| Nobuhiro Iwamatsu | e92c9518 | 2008-03-12 12:15:29 +0900 | [diff] [blame] | 22 | |
| Anton Staaf | 2482e3c | 2011-10-17 16:46:07 -0700 | [diff] [blame] | 23 | /* |
| 24 | * Use the L1 data cache line size value for the minimum DMA buffer alignment |
| 25 | * on SH. |
| 26 | */ |
| 27 | #ifndef ARCH_DMA_MINALIGN |
| 28 | #define ARCH_DMA_MINALIGN L1_CACHE_BYTES |
| 29 | #endif |
| 30 | |
| Nobuhiro Iwamatsu | e92c9518 | 2008-03-12 12:15:29 +0900 | [diff] [blame] | 31 | #endif /* __ASM_SH_CACHE_H */ |