Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Enric Balletbò i Serra | 9d1b298 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 2 | /* |
| 3 | * am335x_sl50.h |
| 4 | * |
| 5 | * Copyright (C) 2015 Toby Churchill Ltd - http://www.toby-churchill.com/ |
Enric Balletbò i Serra | 9d1b298 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __CONFIG_AM335X_EVM_H |
| 9 | #define __CONFIG_AM335X_EVM_H |
| 10 | |
| 11 | #include <configs/ti_am335x_common.h> |
Enric Balletbò i Serra | 9d1b298 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 12 | |
| 13 | #ifndef CONFIG_SPL_BUILD |
Enric Balletbò i Serra | 9d1b298 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 14 | # define CONFIG_TIMESTAMP |
Enric Balletbò i Serra | 9d1b298 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 15 | #endif |
| 16 | |
| 17 | #define CONFIG_SYS_BOOTM_LEN (16 << 20) |
| 18 | |
| 19 | /*#define CONFIG_MACH_TYPE 3589 Until the next sync */ |
Enric Balletbò i Serra | 9d1b298 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 20 | |
| 21 | /* Clock Defines */ |
| 22 | #define V_OSCK 24000000 /* Clock output from T2 */ |
| 23 | #define V_SCLK (V_OSCK) |
| 24 | |
Enric Balletbò i Serra | 9d1b298 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 25 | #ifndef CONFIG_SPL_BUILD |
| 26 | |
Enric Balletbò i Serra | 9d1b298 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 27 | #define MEM_LAYOUT_ENV_SETTINGS \ |
| 28 | "scriptaddr=0x80000000\0" \ |
| 29 | "pxefile_addr_r=0x80100000\0" \ |
| 30 | "kernel_addr_r=0x82000000\0" \ |
| 31 | "fdt_addr_r=0x88000000\0" \ |
| 32 | "ramdisk_addr_r=0x88080000\0" \ |
| 33 | |
| 34 | #define BOOT_TARGET_DEVICES(func) \ |
| 35 | func(MMC, mmc, 0) \ |
| 36 | func(MMC, mmc, 1) |
| 37 | |
| 38 | #define AM335XX_BOARD_FDTFILE \ |
| 39 | "fdtfile=am335x-sl50.dtb\0" \ |
| 40 | |
| 41 | #include <config_distro_bootcmd.h> |
| 42 | |
| 43 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 44 | AM335XX_BOARD_FDTFILE \ |
| 45 | MEM_LAYOUT_ENV_SETTINGS \ |
| 46 | BOOTENV |
| 47 | |
| 48 | #endif |
| 49 | |
| 50 | /* NS16550 Configuration */ |
| 51 | #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ |
| 52 | #define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ |
| 53 | #define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ |
| 54 | #define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ |
| 55 | #define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ |
| 56 | #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ |
Enric Balletbò i Serra | 9d1b298 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 57 | |
Enric Balletbò i Serra | 9d1b298 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 58 | #define CONFIG_ENV_EEPROM_IS_ON_I2C |
| 59 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ |
| 60 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 |
Enric Balletbò i Serra | 9d1b298 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 61 | |
| 62 | /* PMIC support */ |
| 63 | #define CONFIG_POWER_TPS65217 |
| 64 | #define CONFIG_POWER_TPS65910 |
| 65 | |
| 66 | /* SPL */ |
Enric Balletbò i Serra | 9d1b298 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 67 | |
| 68 | /* Bootcount using the RTC block */ |
Enric Balletbò i Serra | 9d1b298 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 69 | #define CONFIG_SYS_BOOTCOUNT_BE |
| 70 | |
Faiz Abbas | b432b1e | 2018-02-16 21:17:44 +0530 | [diff] [blame] | 71 | #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USB_ETHER) |
Enric Balletbò i Serra | 9d1b298 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 72 | /* Remove other SPL modes. */ |
Enric Balletbò i Serra | 9d1b298 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 73 | /* disable host part of MUSB in SPL */ |
| 74 | #undef CONFIG_MUSB_HOST |
| 75 | /* disable EFI partitions and partition UUID support */ |
Enric Balletbò i Serra | 9d1b298 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 76 | #endif |
| 77 | |
| 78 | #if defined(CONFIG_EMMC_BOOT) |
Enric Balletbò i Serra | 9d1b298 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 79 | #define CONFIG_SYS_MMC_ENV_DEV 1 |
| 80 | #define CONFIG_SYS_MMC_ENV_PART 2 |
Enric Balletbò i Serra | 9d1b298 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 81 | #endif |
| 82 | |
| 83 | /* Network. */ |
Enric Balletbò i Serra | 9d1b298 | 2015-09-07 07:43:20 +0200 | [diff] [blame] | 84 | #define CONFIG_PHY_SMSC |
| 85 | |
| 86 | #endif /* ! __CONFIG_AM335X_SL50_H */ |