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Peter Tyser017f11f2009-06-30 17:15:40 -05001/*
2 * Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
3 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
5 *
6 * (C) Copyright 2000
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02009 * SPDX-License-Identifier: GPL-2.0+
Peter Tyser017f11f2009-06-30 17:15:40 -050010 */
11
12#include <config.h>
13#include <common.h>
Peter Tysera7303932009-06-30 17:15:42 -050014#include <asm/io.h>
Peter Tyser017f11f2009-06-30 17:15:40 -050015#include <asm/fsl_dma.h>
16
Peter Tyser51402ac2009-06-30 17:15:43 -050017/* Controller can only transfer 2^26 - 1 bytes at a time */
18#define FSL_DMA_MAX_SIZE (0x3ffffff)
19
Peter Tysere94e4602009-06-30 17:15:51 -050020#if defined(CONFIG_MPC83xx)
21#define FSL_DMA_MR_DEFAULT (FSL_DMA_MR_CTM_DIRECT | FSL_DMA_MR_DMSEN)
22#else
23#define FSL_DMA_MR_DEFAULT (FSL_DMA_MR_BWC_DIS | FSL_DMA_MR_CTM_DIRECT)
24#endif
25
26
27#if defined(CONFIG_MPC83xx)
28dma83xx_t *dma_base = (void *)(CONFIG_SYS_MPC83xx_DMA_ADDR);
29#elif defined(CONFIG_MPC85xx)
Peter Tysera7303932009-06-30 17:15:42 -050030ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
Peter Tyser017f11f2009-06-30 17:15:40 -050031#elif defined(CONFIG_MPC86xx)
Peter Tysera7303932009-06-30 17:15:42 -050032ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
Peter Tyser017f11f2009-06-30 17:15:40 -050033#else
34#error "Freescale DMA engine not supported on your processor"
35#endif
36
37static void dma_sync(void)
38{
39#if defined(CONFIG_MPC85xx)
40 asm("sync; isync; msync");
41#elif defined(CONFIG_MPC86xx)
42 asm("sync; isync");
43#endif
44}
45
Peter Tysere94e4602009-06-30 17:15:51 -050046static void out_dma32(volatile unsigned *addr, int val)
47{
48#if defined(CONFIG_MPC83xx)
49 out_le32(addr, val);
50#else
51 out_be32(addr, val);
52#endif
53}
54
55static uint in_dma32(volatile unsigned *addr)
56{
57#if defined(CONFIG_MPC83xx)
58 return in_le32(addr);
59#else
60 return in_be32(addr);
61#endif
62}
63
Peter Tyser017f11f2009-06-30 17:15:40 -050064static uint dma_check(void) {
65 volatile fsl_dma_t *dma = &dma_base->dma[0];
Peter Tysera7303932009-06-30 17:15:42 -050066 uint status;
Peter Tyser017f11f2009-06-30 17:15:40 -050067
68 /* While the channel is busy, spin */
Peter Tysera7303932009-06-30 17:15:42 -050069 do {
Peter Tysere94e4602009-06-30 17:15:51 -050070 status = in_dma32(&dma->sr);
Peter Tysera7303932009-06-30 17:15:42 -050071 } while (status & FSL_DMA_SR_CB);
Peter Tyser017f11f2009-06-30 17:15:40 -050072
73 /* clear MR[CS] channel start bit */
Peter Tysere94e4602009-06-30 17:15:51 -050074 out_dma32(&dma->mr, in_dma32(&dma->mr) & ~FSL_DMA_MR_CS);
Peter Tyser017f11f2009-06-30 17:15:40 -050075 dma_sync();
76
77 if (status != 0)
78 printf ("DMA Error: status = %x\n", status);
79
80 return status;
81}
82
Peter Tysere94e4602009-06-30 17:15:51 -050083#if !defined(CONFIG_MPC83xx)
Peter Tyser017f11f2009-06-30 17:15:40 -050084void dma_init(void) {
85 volatile fsl_dma_t *dma = &dma_base->dma[0];
86
Peter Tysere94e4602009-06-30 17:15:51 -050087 out_dma32(&dma->satr, FSL_DMA_SATR_SREAD_SNOOP);
88 out_dma32(&dma->datr, FSL_DMA_DATR_DWRITE_SNOOP);
89 out_dma32(&dma->sr, 0xffffffff); /* clear any errors */
Peter Tyser017f11f2009-06-30 17:15:40 -050090 dma_sync();
91}
Peter Tysere94e4602009-06-30 17:15:51 -050092#endif
Peter Tyser017f11f2009-06-30 17:15:40 -050093
Peter Tyser7892f612009-06-30 17:15:45 -050094int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t count) {
Peter Tyser017f11f2009-06-30 17:15:40 -050095 volatile fsl_dma_t *dma = &dma_base->dma[0];
Peter Tyser51402ac2009-06-30 17:15:43 -050096 uint xfer_size;
Peter Tyser017f11f2009-06-30 17:15:40 -050097
Peter Tyser51402ac2009-06-30 17:15:43 -050098 while (count) {
Masahiro Yamadac79cba32014-09-18 13:28:06 +090099 xfer_size = min(FSL_DMA_MAX_SIZE, count);
Peter Tyser017f11f2009-06-30 17:15:40 -0500100
York Sun359ec492010-08-27 16:25:50 -0500101 out_dma32(&dma->dar, (u32) (dest & 0xFFFFFFFF));
102 out_dma32(&dma->sar, (u32) (src & 0xFFFFFFFF));
Ira W. Snyder9a865ff2011-03-01 14:40:55 -0800103#if !defined(CONFIG_MPC83xx)
York Sun359ec492010-08-27 16:25:50 -0500104 out_dma32(&dma->satr,
105 in_dma32(&dma->satr) | (u32)((u64)src >> 32));
106 out_dma32(&dma->datr,
107 in_dma32(&dma->datr) | (u32)((u64)dest >> 32));
Ira W. Snyder9a865ff2011-03-01 14:40:55 -0800108#endif
Peter Tysere94e4602009-06-30 17:15:51 -0500109 out_dma32(&dma->bcr, xfer_size);
110 dma_sync();
Peter Tyser017f11f2009-06-30 17:15:40 -0500111
Peter Tysere94e4602009-06-30 17:15:51 -0500112 /* Prepare mode register */
113 out_dma32(&dma->mr, FSL_DMA_MR_DEFAULT);
Peter Tyser51402ac2009-06-30 17:15:43 -0500114 dma_sync();
Peter Tyser017f11f2009-06-30 17:15:40 -0500115
Peter Tyser51402ac2009-06-30 17:15:43 -0500116 /* Start the transfer */
Peter Tysere94e4602009-06-30 17:15:51 -0500117 out_dma32(&dma->mr, FSL_DMA_MR_DEFAULT | FSL_DMA_MR_CS);
Peter Tyser51402ac2009-06-30 17:15:43 -0500118
119 count -= xfer_size;
120 src += xfer_size;
121 dest += xfer_size;
122
123 dma_sync();
124
125 if (dma_check())
126 return -1;
127 }
128
129 return 0;
Peter Tyser017f11f2009-06-30 17:15:40 -0500130}
Peter Tyser0d595f72009-06-30 17:15:48 -0500131
Peter Tysere94e4602009-06-30 17:15:51 -0500132/*
133 * 85xx/86xx use dma to initialize SDRAM when !CONFIG_ECC_INIT_VIA_DDRCONTROLLER
134 * while 83xx uses dma to initialize SDRAM when CONFIG_DDR_ECC_INIT_VIA_DMA
135 */
136#if ((!defined CONFIG_MPC83xx && defined(CONFIG_DDR_ECC) && \
137 !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) || \
138 (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)))
Peter Tyser0d595f72009-06-30 17:15:48 -0500139void dma_meminit(uint val, uint size)
140{
141 uint *p = 0;
142 uint i = 0;
143
144 for (*p = 0; p < (uint *)(8 * 1024); p++) {
145 if (((uint)p & 0x1f) == 0)
146 ppcDcbz((ulong)p);
147
148 *p = (uint)CONFIG_MEM_INIT_VALUE;
149
150 if (((uint)p & 0x1c) == 0x1c)
151 ppcDcbf((ulong)p);
152 }
153
154 dmacpy(0x002000, 0, 0x002000); /* 8K */
155 dmacpy(0x004000, 0, 0x004000); /* 16K */
156 dmacpy(0x008000, 0, 0x008000); /* 32K */
157 dmacpy(0x010000, 0, 0x010000); /* 64K */
158 dmacpy(0x020000, 0, 0x020000); /* 128K */
159 dmacpy(0x040000, 0, 0x040000); /* 256K */
160 dmacpy(0x080000, 0, 0x080000); /* 512K */
161 dmacpy(0x100000, 0, 0x100000); /* 1M */
162 dmacpy(0x200000, 0, 0x200000); /* 2M */
163 dmacpy(0x400000, 0, 0x400000); /* 4M */
164
165 for (i = 1; i < size / 0x800000; i++)
166 dmacpy((0x800000 * i), 0, 0x800000);
167}
168#endif