blob: 430e22821c7d5c21371b2e59a22c6a6d010ee10e [file] [log] [blame]
Michal Simek185f7d92012-09-13 20:23:34 +00001/*
2 * (C) Copyright 2011 Michal Simek
3 *
4 * Michal SIMEK <monstr@monstr.eu>
5 *
6 * Based on Xilinx gmac driver:
7 * (C) Copyright 2011 Xilinx
8 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02009 * SPDX-License-Identifier: GPL-2.0+
Michal Simek185f7d92012-09-13 20:23:34 +000010 */
11
12#include <common.h>
13#include <net.h>
Michal Simek2fd24892014-04-25 14:17:38 +020014#include <netdev.h>
Michal Simek185f7d92012-09-13 20:23:34 +000015#include <config.h>
Michal Simekf88a6862014-02-24 11:16:30 +010016#include <fdtdec.h>
17#include <libfdt.h>
Michal Simek185f7d92012-09-13 20:23:34 +000018#include <malloc.h>
19#include <asm/io.h>
20#include <phy.h>
21#include <miiphy.h>
22#include <watchdog.h>
David Andrey01fbf312013-04-05 17:24:24 +020023#include <asm/arch/hardware.h>
Michal Simek80243522012-10-15 14:01:23 +020024#include <asm/arch/sys_proto.h>
Michal Simek185f7d92012-09-13 20:23:34 +000025
26#if !defined(CONFIG_PHYLIB)
27# error XILINX_GEM_ETHERNET requires PHYLIB
28#endif
29
30/* Bit/mask specification */
31#define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
32#define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */
33#define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */
34#define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */
35#define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */
36
37#define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */
38#define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */
39#define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */
40
41#define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */
42#define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */
43#define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */
44
45/* Wrap bit, last descriptor */
46#define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
47#define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
48
Michal Simek185f7d92012-09-13 20:23:34 +000049#define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
50#define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
51#define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
52#define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
53
Michal Simek80243522012-10-15 14:01:23 +020054#define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */
55#define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */
56#define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */
57#define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */
Michal Simek185f7d92012-09-13 20:23:34 +000058#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */
Michal Simek80243522012-10-15 14:01:23 +020059#define ZYNQ_GEM_NWCFG_MDCCLKDIV2 0x0000c0000 /* Div pclk by 48, 120MHz */
Michal Simek185f7d92012-09-13 20:23:34 +000060
Michal Simek80243522012-10-15 14:01:23 +020061#define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_NWCFG_FDEN | \
Michal Simek185f7d92012-09-13 20:23:34 +000062 ZYNQ_GEM_NWCFG_FSREM | \
63 ZYNQ_GEM_NWCFG_MDCCLKDIV)
64
65#define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */
66
67#define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */
68/* Use full configured addressable space (8 Kb) */
69#define ZYNQ_GEM_DMACR_RXSIZE 0x00000300
70/* Use full configured addressable space (4 Kb) */
71#define ZYNQ_GEM_DMACR_TXSIZE 0x00000400
72/* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
73#define ZYNQ_GEM_DMACR_RXBUF 0x00180000
74
75#define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \
76 ZYNQ_GEM_DMACR_RXSIZE | \
77 ZYNQ_GEM_DMACR_TXSIZE | \
78 ZYNQ_GEM_DMACR_RXBUF)
79
Michal Simekf97d7e82013-04-22 14:41:09 +020080/* Use MII register 1 (MII status register) to detect PHY */
81#define PHY_DETECT_REG 1
82
83/* Mask used to verify certain PHY features (or register contents)
84 * in the register above:
85 * 0x1000: 10Mbps full duplex support
86 * 0x0800: 10Mbps half duplex support
87 * 0x0008: Auto-negotiation support
88 */
89#define PHY_DETECT_MASK 0x1808
90
Srikanth Thokalaa5144232013-11-08 22:55:48 +053091/* TX BD status masks */
92#define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff
93#define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
94#define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000
95
Soren Brinkmann97598fc2013-11-21 13:39:01 -080096/* Clock frequencies for different speeds */
97#define ZYNQ_GEM_FREQUENCY_10 2500000UL
98#define ZYNQ_GEM_FREQUENCY_100 25000000UL
99#define ZYNQ_GEM_FREQUENCY_1000 125000000UL
100
Michal Simek185f7d92012-09-13 20:23:34 +0000101/* Device registers */
102struct zynq_gem_regs {
103 u32 nwctrl; /* Network Control reg */
104 u32 nwcfg; /* Network Config reg */
105 u32 nwsr; /* Network Status reg */
106 u32 reserved1;
107 u32 dmacr; /* DMA Control reg */
108 u32 txsr; /* TX Status reg */
109 u32 rxqbase; /* RX Q Base address reg */
110 u32 txqbase; /* TX Q Base address reg */
111 u32 rxsr; /* RX Status reg */
112 u32 reserved2[2];
113 u32 idr; /* Interrupt Disable reg */
114 u32 reserved3;
115 u32 phymntnc; /* Phy Maintaince reg */
116 u32 reserved4[18];
117 u32 hashl; /* Hash Low address reg */
118 u32 hashh; /* Hash High address reg */
119#define LADDR_LOW 0
120#define LADDR_HIGH 1
121 u32 laddr[4][LADDR_HIGH + 1]; /* Specific1 addr low/high reg */
122 u32 match[4]; /* Type ID1 Match reg */
123 u32 reserved6[18];
124 u32 stat[44]; /* Octects transmitted Low reg - stat start */
125};
126
127/* BD descriptors */
128struct emac_bd {
129 u32 addr; /* Next descriptor pointer */
130 u32 status;
131};
132
133#define RX_BUF 3
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530134/* Page table entries are set to 1MB, or multiples of 1MB
135 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
136 */
137#define BD_SPACE 0x100000
138/* BD separation space */
139#define BD_SEPRN_SPACE 64
Michal Simek185f7d92012-09-13 20:23:34 +0000140
141/* Initialized, rxbd_current, rx_first_buf must be 0 after init */
142struct zynq_gem_priv {
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530143 struct emac_bd *tx_bd;
144 struct emac_bd *rx_bd;
145 char *rxbuffers;
Michal Simek185f7d92012-09-13 20:23:34 +0000146 u32 rxbd_current;
147 u32 rx_first_buf;
148 int phyaddr;
David Andrey01fbf312013-04-05 17:24:24 +0200149 u32 emio;
Michal Simek05868752013-01-24 13:04:12 +0100150 int init;
Michal Simek185f7d92012-09-13 20:23:34 +0000151 struct phy_device *phydev;
152 struct mii_dev *bus;
153};
154
155static inline int mdio_wait(struct eth_device *dev)
156{
157 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
158 u32 timeout = 200;
159
160 /* Wait till MDIO interface is ready to accept a new transaction. */
161 while (--timeout) {
162 if (readl(&regs->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK)
163 break;
164 WATCHDOG_RESET();
165 }
166
167 if (!timeout) {
168 printf("%s: Timeout\n", __func__);
169 return 1;
170 }
171
172 return 0;
173}
174
175static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum,
176 u32 op, u16 *data)
177{
178 u32 mgtcr;
179 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
180
181 if (mdio_wait(dev))
182 return 1;
183
184 /* Construct mgtcr mask for the operation */
185 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
186 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
187 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
188
189 /* Write mgtcr and wait for completion */
190 writel(mgtcr, &regs->phymntnc);
191
192 if (mdio_wait(dev))
193 return 1;
194
195 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
196 *data = readl(&regs->phymntnc);
197
198 return 0;
199}
200
201static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val)
202{
203 return phy_setup_op(dev, phy_addr, regnum,
204 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
205}
206
207static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data)
208{
209 return phy_setup_op(dev, phy_addr, regnum,
210 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
211}
212
Michal Simekf97d7e82013-04-22 14:41:09 +0200213static void phy_detection(struct eth_device *dev)
214{
215 int i;
216 u16 phyreg;
217 struct zynq_gem_priv *priv = dev->priv;
218
219 if (priv->phyaddr != -1) {
220 phyread(dev, priv->phyaddr, PHY_DETECT_REG, &phyreg);
221 if ((phyreg != 0xFFFF) &&
222 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
223 /* Found a valid PHY address */
224 debug("Default phy address %d is valid\n",
225 priv->phyaddr);
226 return;
227 } else {
228 debug("PHY address is not setup correctly %d\n",
229 priv->phyaddr);
230 priv->phyaddr = -1;
231 }
232 }
233
234 debug("detecting phy address\n");
235 if (priv->phyaddr == -1) {
236 /* detect the PHY address */
237 for (i = 31; i >= 0; i--) {
238 phyread(dev, i, PHY_DETECT_REG, &phyreg);
239 if ((phyreg != 0xFFFF) &&
240 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
241 /* Found a valid PHY address */
242 priv->phyaddr = i;
243 debug("Found valid phy address, %d\n", i);
244 return;
245 }
246 }
247 }
248 printf("PHY is not detected\n");
249}
250
Michal Simek185f7d92012-09-13 20:23:34 +0000251static int zynq_gem_setup_mac(struct eth_device *dev)
252{
253 u32 i, macaddrlow, macaddrhigh;
254 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
255
256 /* Set the MAC bits [31:0] in BOT */
257 macaddrlow = dev->enetaddr[0];
258 macaddrlow |= dev->enetaddr[1] << 8;
259 macaddrlow |= dev->enetaddr[2] << 16;
260 macaddrlow |= dev->enetaddr[3] << 24;
261
262 /* Set MAC bits [47:32] in TOP */
263 macaddrhigh = dev->enetaddr[4];
264 macaddrhigh |= dev->enetaddr[5] << 8;
265
266 for (i = 0; i < 4; i++) {
267 writel(0, &regs->laddr[i][LADDR_LOW]);
268 writel(0, &regs->laddr[i][LADDR_HIGH]);
269 /* Do not use MATCHx register */
270 writel(0, &regs->match[i]);
271 }
272
273 writel(macaddrlow, &regs->laddr[0][LADDR_LOW]);
274 writel(macaddrhigh, &regs->laddr[0][LADDR_HIGH]);
275
276 return 0;
277}
278
279static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
280{
Soren Brinkmann97598fc2013-11-21 13:39:01 -0800281 u32 i;
282 unsigned long clk_rate = 0;
Michal Simek185f7d92012-09-13 20:23:34 +0000283 struct phy_device *phydev;
284 const u32 stat_size = (sizeof(struct zynq_gem_regs) -
285 offsetof(struct zynq_gem_regs, stat)) / 4;
286 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
287 struct zynq_gem_priv *priv = dev->priv;
288 const u32 supported = SUPPORTED_10baseT_Half |
289 SUPPORTED_10baseT_Full |
290 SUPPORTED_100baseT_Half |
291 SUPPORTED_100baseT_Full |
292 SUPPORTED_1000baseT_Half |
293 SUPPORTED_1000baseT_Full;
294
Michal Simek05868752013-01-24 13:04:12 +0100295 if (!priv->init) {
296 /* Disable all interrupts */
297 writel(0xFFFFFFFF, &regs->idr);
Michal Simek185f7d92012-09-13 20:23:34 +0000298
Michal Simek05868752013-01-24 13:04:12 +0100299 /* Disable the receiver & transmitter */
300 writel(0, &regs->nwctrl);
301 writel(0, &regs->txsr);
302 writel(0, &regs->rxsr);
303 writel(0, &regs->phymntnc);
Michal Simek185f7d92012-09-13 20:23:34 +0000304
Michal Simek05868752013-01-24 13:04:12 +0100305 /* Clear the Hash registers for the mac address
306 * pointed by AddressPtr
307 */
308 writel(0x0, &regs->hashl);
309 /* Write bits [63:32] in TOP */
310 writel(0x0, &regs->hashh);
Michal Simek185f7d92012-09-13 20:23:34 +0000311
Michal Simek05868752013-01-24 13:04:12 +0100312 /* Clear all counters */
313 for (i = 0; i <= stat_size; i++)
314 readl(&regs->stat[i]);
Michal Simek185f7d92012-09-13 20:23:34 +0000315
Michal Simek05868752013-01-24 13:04:12 +0100316 /* Setup RxBD space */
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530317 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
Michal Simek185f7d92012-09-13 20:23:34 +0000318
Michal Simek05868752013-01-24 13:04:12 +0100319 for (i = 0; i < RX_BUF; i++) {
320 priv->rx_bd[i].status = 0xF0000000;
321 priv->rx_bd[i].addr =
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530322 ((u32)(priv->rxbuffers) +
Michal Simek185f7d92012-09-13 20:23:34 +0000323 (i * PKTSIZE_ALIGN));
Michal Simek05868752013-01-24 13:04:12 +0100324 }
325 /* WRAP bit to last BD */
326 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
327 /* Write RxBDs to IP */
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530328 writel((u32)priv->rx_bd, &regs->rxqbase);
Michal Simek185f7d92012-09-13 20:23:34 +0000329
Michal Simek05868752013-01-24 13:04:12 +0100330 /* Setup for DMA Configuration register */
331 writel(ZYNQ_GEM_DMACR_INIT, &regs->dmacr);
Michal Simek185f7d92012-09-13 20:23:34 +0000332
Michal Simek05868752013-01-24 13:04:12 +0100333 /* Setup for Network Control register, MDIO, Rx and Tx enable */
Michal Simek80243522012-10-15 14:01:23 +0200334 setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
Michal Simek185f7d92012-09-13 20:23:34 +0000335
Michal Simek05868752013-01-24 13:04:12 +0100336 priv->init++;
337 }
338
Michal Simekf97d7e82013-04-22 14:41:09 +0200339 phy_detection(dev);
340
Michal Simek185f7d92012-09-13 20:23:34 +0000341 /* interface - look at tsec */
Michal Simekc1a9fa42014-02-25 10:25:38 +0100342 phydev = phy_connect(priv->bus, priv->phyaddr, dev,
343 PHY_INTERFACE_MODE_MII);
Michal Simek185f7d92012-09-13 20:23:34 +0000344
Michal Simek80243522012-10-15 14:01:23 +0200345 phydev->supported = supported | ADVERTISED_Pause |
346 ADVERTISED_Asym_Pause;
Michal Simek185f7d92012-09-13 20:23:34 +0000347 phydev->advertising = phydev->supported;
348 priv->phydev = phydev;
349 phy_config(phydev);
350 phy_startup(phydev);
351
Michal Simek4ed4aa22013-11-12 14:25:29 +0100352 if (!phydev->link) {
353 printf("%s: No link.\n", phydev->dev->name);
354 return -1;
355 }
356
Michal Simek80243522012-10-15 14:01:23 +0200357 switch (phydev->speed) {
358 case SPEED_1000:
359 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000,
360 &regs->nwcfg);
Soren Brinkmann97598fc2013-11-21 13:39:01 -0800361 clk_rate = ZYNQ_GEM_FREQUENCY_1000;
Michal Simek80243522012-10-15 14:01:23 +0200362 break;
363 case SPEED_100:
364 clrsetbits_le32(&regs->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000,
365 ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100);
Soren Brinkmann97598fc2013-11-21 13:39:01 -0800366 clk_rate = ZYNQ_GEM_FREQUENCY_100;
Michal Simek80243522012-10-15 14:01:23 +0200367 break;
368 case SPEED_10:
Soren Brinkmann97598fc2013-11-21 13:39:01 -0800369 clk_rate = ZYNQ_GEM_FREQUENCY_10;
Michal Simek80243522012-10-15 14:01:23 +0200370 break;
371 }
David Andrey01fbf312013-04-05 17:24:24 +0200372
373 /* Change the rclk and clk only not using EMIO interface */
374 if (!priv->emio)
375 zynq_slcr_gem_clk_setup(dev->iobase !=
Soren Brinkmann97598fc2013-11-21 13:39:01 -0800376 ZYNQ_GEM_BASEADDR0, clk_rate);
Michal Simek80243522012-10-15 14:01:23 +0200377
378 setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
379 ZYNQ_GEM_NWCTRL_TXEN_MASK);
380
Michal Simek185f7d92012-09-13 20:23:34 +0000381 return 0;
382}
383
384static int zynq_gem_send(struct eth_device *dev, void *ptr, int len)
385{
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530386 u32 addr, size;
Michal Simek185f7d92012-09-13 20:23:34 +0000387 struct zynq_gem_priv *priv = dev->priv;
388 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
Michal Simek185f7d92012-09-13 20:23:34 +0000389
390 /* setup BD */
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530391 writel((u32)priv->tx_bd, &regs->txqbase);
Michal Simek185f7d92012-09-13 20:23:34 +0000392
393 /* Setup Tx BD */
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530394 memset(priv->tx_bd, 0, sizeof(struct emac_bd));
Michal Simek185f7d92012-09-13 20:23:34 +0000395
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530396 priv->tx_bd->addr = (u32)ptr;
397 priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
398 ZYNQ_GEM_TXBUF_LAST_MASK;
399
400 addr = (u32) ptr;
401 addr &= ~(ARCH_DMA_MINALIGN - 1);
402 size = roundup(len, ARCH_DMA_MINALIGN);
403 flush_dcache_range(addr, addr + size);
404 barrier();
Michal Simek185f7d92012-09-13 20:23:34 +0000405
406 /* Start transmit */
407 setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
408
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530409 /* Read TX BD status */
410 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_UNDERRUN)
411 printf("TX underrun\n");
412 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
413 printf("TX buffers exhausted in mid frame\n");
Michal Simek185f7d92012-09-13 20:23:34 +0000414
Michal Simek185f7d92012-09-13 20:23:34 +0000415 return 0;
416}
417
418/* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
419static int zynq_gem_recv(struct eth_device *dev)
420{
421 int frame_len;
422 struct zynq_gem_priv *priv = dev->priv;
423 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
424 struct emac_bd *first_bd;
425
426 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
427 return 0;
428
429 if (!(current_bd->status &
430 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
431 printf("GEM: SOF or EOF not set for last buffer received!\n");
432 return 0;
433 }
434
435 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
436 if (frame_len) {
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530437 u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
438 addr &= ~(ARCH_DMA_MINALIGN - 1);
439 u32 size = roundup(frame_len, ARCH_DMA_MINALIGN);
440 invalidate_dcache_range(addr, addr + size);
441
442 NetReceive((u8 *)addr, frame_len);
Michal Simek185f7d92012-09-13 20:23:34 +0000443
444 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK)
445 priv->rx_first_buf = priv->rxbd_current;
446 else {
447 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
448 current_bd->status = 0xF0000000; /* FIXME */
449 }
450
451 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
452 first_bd = &priv->rx_bd[priv->rx_first_buf];
453 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
454 first_bd->status = 0xF0000000;
455 }
456
457 if ((++priv->rxbd_current) >= RX_BUF)
458 priv->rxbd_current = 0;
Michal Simek185f7d92012-09-13 20:23:34 +0000459 }
460
Michal Simek3b90d0a2013-01-25 08:24:18 +0100461 return frame_len;
Michal Simek185f7d92012-09-13 20:23:34 +0000462}
463
464static void zynq_gem_halt(struct eth_device *dev)
465{
466 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
467
Michal Simek80243522012-10-15 14:01:23 +0200468 clrsetbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
469 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
Michal Simek185f7d92012-09-13 20:23:34 +0000470}
471
472static int zynq_gem_miiphyread(const char *devname, uchar addr,
473 uchar reg, ushort *val)
474{
475 struct eth_device *dev = eth_get_dev();
476 int ret;
477
478 ret = phyread(dev, addr, reg, val);
479 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val);
480 return ret;
481}
482
483static int zynq_gem_miiphy_write(const char *devname, uchar addr,
484 uchar reg, ushort val)
485{
486 struct eth_device *dev = eth_get_dev();
487
488 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val);
489 return phywrite(dev, addr, reg, val);
490}
491
Michal Simek58405372015-01-14 15:44:21 +0100492int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr,
493 int phy_addr, u32 emio)
Michal Simek185f7d92012-09-13 20:23:34 +0000494{
495 struct eth_device *dev;
496 struct zynq_gem_priv *priv;
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530497 void *bd_space;
Michal Simek185f7d92012-09-13 20:23:34 +0000498
499 dev = calloc(1, sizeof(*dev));
500 if (dev == NULL)
501 return -1;
502
503 dev->priv = calloc(1, sizeof(struct zynq_gem_priv));
504 if (dev->priv == NULL) {
505 free(dev);
506 return -1;
507 }
508 priv = dev->priv;
509
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530510 /* Align rxbuffers to ARCH_DMA_MINALIGN */
511 priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
512 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
513
514 /* Align bd_space to 1MB */
515 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
516 mmu_set_region_dcache_behaviour((u32)bd_space, BD_SPACE, DCACHE_OFF);
517
518 /* Initialize the bd spaces for tx and rx bd's */
519 priv->tx_bd = (struct emac_bd *)bd_space;
520 priv->rx_bd = (struct emac_bd *)((u32)bd_space + BD_SEPRN_SPACE);
521
David Andrey117cd4c2013-04-04 19:13:07 +0200522 priv->phyaddr = phy_addr;
David Andrey01fbf312013-04-05 17:24:24 +0200523 priv->emio = emio;
Michal Simek185f7d92012-09-13 20:23:34 +0000524
Michal Simek58405372015-01-14 15:44:21 +0100525 sprintf(dev->name, "Gem.%lx", base_addr);
Michal Simek185f7d92012-09-13 20:23:34 +0000526
527 dev->iobase = base_addr;
528
529 dev->init = zynq_gem_init;
530 dev->halt = zynq_gem_halt;
531 dev->send = zynq_gem_send;
532 dev->recv = zynq_gem_recv;
533 dev->write_hwaddr = zynq_gem_setup_mac;
534
535 eth_register(dev);
536
537 miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write);
538 priv->bus = miiphy_get_dev_by_name(dev->name);
539
540 return 1;
541}
Michal Simekf88a6862014-02-24 11:16:30 +0100542
543#ifdef CONFIG_OF_CONTROL
544int zynq_gem_of_init(const void *blob)
545{
546 int offset = 0;
547 u32 ret = 0;
548 u32 reg, phy_reg;
549
550 debug("ZYNQ GEM: Initialization\n");
551
552 do {
553 offset = fdt_node_offset_by_compatible(blob, offset,
554 "xlnx,ps7-ethernet-1.00.a");
555 if (offset != -1) {
556 reg = fdtdec_get_addr(blob, offset, "reg");
557 if (reg != FDT_ADDR_T_NONE) {
558 offset = fdtdec_lookup_phandle(blob, offset,
559 "phy-handle");
560 if (offset != -1)
561 phy_reg = fdtdec_get_addr(blob, offset,
562 "reg");
563 else
564 phy_reg = 0;
565
566 debug("ZYNQ GEM: addr %x, phyaddr %x\n",
567 reg, phy_reg);
568
569 ret |= zynq_gem_initialize(NULL, reg,
570 phy_reg, 0);
571
572 } else {
573 debug("ZYNQ GEM: Can't get base address\n");
574 return -1;
575 }
576 }
577 } while (offset != -1);
578
579 return ret;
580}
581#endif