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Michal Simek194846f2012-09-14 00:55:24 +00001/*
2 * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Michal Simek194846f2012-09-14 00:55:24 +00006 */
7
8#include <common.h>
Michal Simekc9416b92014-02-24 11:16:33 +01009#include <fdtdec.h>
Michal Simek194846f2012-09-14 00:55:24 +000010#include <watchdog.h>
11#include <asm/io.h>
12#include <linux/compiler.h>
13#include <serial.h>
Soren Brinkmann19605e22013-11-21 13:38:55 -080014#include <asm/arch/clk.h>
Michal Simekbf834952013-12-19 23:38:58 +053015#include <asm/arch/hardware.h>
Michal Simek194846f2012-09-14 00:55:24 +000016
Michal Simekc9416b92014-02-24 11:16:33 +010017DECLARE_GLOBAL_DATA_PTR;
18
Michal Simek194846f2012-09-14 00:55:24 +000019#define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
20#define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
21
22#define ZYNQ_UART_CR_TX_EN 0x00000010 /* TX enabled */
23#define ZYNQ_UART_CR_RX_EN 0x00000004 /* RX enabled */
24#define ZYNQ_UART_CR_TXRST 0x00000002 /* TX logic reset */
25#define ZYNQ_UART_CR_RXRST 0x00000001 /* RX logic reset */
26
27#define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
28
Michal Simek194846f2012-09-14 00:55:24 +000029struct uart_zynq {
Michal Simeka2425e62015-01-07 15:00:47 +010030 u32 control; /* 0x0 - Control Register [8:0] */
31 u32 mode; /* 0x4 - Mode Register [10:0] */
Michal Simek194846f2012-09-14 00:55:24 +000032 u32 reserved1[4];
Michal Simeka2425e62015-01-07 15:00:47 +010033 u32 baud_rate_gen; /* 0x18 - Baud Rate Generator [15:0] */
Michal Simek194846f2012-09-14 00:55:24 +000034 u32 reserved2[4];
Michal Simeka2425e62015-01-07 15:00:47 +010035 u32 channel_sts; /* 0x2c - Channel Status [11:0] */
36 u32 tx_rx_fifo; /* 0x30 - FIFO [15:0] or [7:0] */
37 u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */
Michal Simek194846f2012-09-14 00:55:24 +000038};
39
40static struct uart_zynq *uart_zynq_ports[2] = {
Michal Simekbf834952013-12-19 23:38:58 +053041 [0] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR0,
42 [1] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR1,
Michal Simek194846f2012-09-14 00:55:24 +000043};
44
Michal Simek194846f2012-09-14 00:55:24 +000045/* Set up the baud rate in gd struct */
46static void uart_zynq_serial_setbrg(const int port)
47{
48 /* Calculation results. */
49 unsigned int calc_bauderror, bdiv, bgen;
50 unsigned long calc_baud = 0;
Michal Simek12c9e7d2014-12-02 13:52:00 +010051 unsigned long baud = gd->baudrate;
Soren Brinkmann19605e22013-11-21 13:38:55 -080052 unsigned long clock = get_uart_clk(port);
Michal Simek194846f2012-09-14 00:55:24 +000053 struct uart_zynq *regs = uart_zynq_ports[port];
54
55 /* master clock
56 * Baud rate = ------------------
57 * bgen * (bdiv + 1)
58 *
59 * Find acceptable values for baud generation.
60 */
61 for (bdiv = 4; bdiv < 255; bdiv++) {
62 bgen = clock / (baud * (bdiv + 1));
63 if (bgen < 2 || bgen > 65535)
64 continue;
65
66 calc_baud = clock / (bgen * (bdiv + 1));
67
68 /*
69 * Use first calculated baudrate with
70 * an acceptable (<3%) error
71 */
72 if (baud > calc_baud)
73 calc_bauderror = baud - calc_baud;
74 else
75 calc_bauderror = calc_baud - baud;
76 if (((calc_bauderror * 100) / baud) < 3)
77 break;
78 }
79
80 writel(bdiv, &regs->baud_rate_divider);
81 writel(bgen, &regs->baud_rate_gen);
82}
83
84/* Initialize the UART, with...some settings. */
85static int uart_zynq_serial_init(const int port)
86{
87 struct uart_zynq *regs = uart_zynq_ports[port];
88
89 if (!regs)
90 return -1;
91
92 /* RX/TX enabled & reset */
93 writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \
94 ZYNQ_UART_CR_RXRST, &regs->control);
95 writel(ZYNQ_UART_MR_PARITY_NONE, &regs->mode); /* 8 bit, no parity */
96 uart_zynq_serial_setbrg(port);
97
98 return 0;
99}
100
101static void uart_zynq_serial_putc(const char c, const int port)
102{
103 struct uart_zynq *regs = uart_zynq_ports[port];
104
105 while ((readl(&regs->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0)
106 WATCHDOG_RESET();
107
108 if (c == '\n') {
109 writel('\r', &regs->tx_rx_fifo);
110 while ((readl(&regs->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0)
111 WATCHDOG_RESET();
112 }
113 writel(c, &regs->tx_rx_fifo);
114}
115
116static void uart_zynq_serial_puts(const char *s, const int port)
117{
118 while (*s)
119 uart_zynq_serial_putc(*s++, port);
120}
121
122static int uart_zynq_serial_tstc(const int port)
123{
124 struct uart_zynq *regs = uart_zynq_ports[port];
125
126 return (readl(&regs->channel_sts) & ZYNQ_UART_SR_RXEMPTY) == 0;
127}
128
129static int uart_zynq_serial_getc(const int port)
130{
131 struct uart_zynq *regs = uart_zynq_ports[port];
132
133 while (!uart_zynq_serial_tstc(port))
134 WATCHDOG_RESET();
135 return readl(&regs->tx_rx_fifo);
136}
137
Michal Simek194846f2012-09-14 00:55:24 +0000138/* Multi serial device functions */
139#define DECLARE_PSSERIAL_FUNCTIONS(port) \
Michal Simek6c4da352014-04-25 13:45:08 +0200140 static int uart_zynq##port##_init(void) \
Michal Simek194846f2012-09-14 00:55:24 +0000141 { return uart_zynq_serial_init(port); } \
Michal Simek6c4da352014-04-25 13:45:08 +0200142 static void uart_zynq##port##_setbrg(void) \
Michal Simek194846f2012-09-14 00:55:24 +0000143 { return uart_zynq_serial_setbrg(port); } \
Michal Simek6c4da352014-04-25 13:45:08 +0200144 static int uart_zynq##port##_getc(void) \
Michal Simek194846f2012-09-14 00:55:24 +0000145 { return uart_zynq_serial_getc(port); } \
Michal Simek6c4da352014-04-25 13:45:08 +0200146 static int uart_zynq##port##_tstc(void) \
Michal Simek194846f2012-09-14 00:55:24 +0000147 { return uart_zynq_serial_tstc(port); } \
Michal Simek6c4da352014-04-25 13:45:08 +0200148 static void uart_zynq##port##_putc(const char c) \
Michal Simek194846f2012-09-14 00:55:24 +0000149 { uart_zynq_serial_putc(c, port); } \
Michal Simek6c4da352014-04-25 13:45:08 +0200150 static void uart_zynq##port##_puts(const char *s) \
Michal Simek194846f2012-09-14 00:55:24 +0000151 { uart_zynq_serial_puts(s, port); }
152
153/* Serial device descriptor */
154#define INIT_PSSERIAL_STRUCTURE(port, __name) { \
155 .name = __name, \
Marek Vasut89143fb2012-09-07 14:35:31 +0200156 .start = uart_zynq##port##_init, \
157 .stop = NULL, \
Michal Simek194846f2012-09-14 00:55:24 +0000158 .setbrg = uart_zynq##port##_setbrg, \
159 .getc = uart_zynq##port##_getc, \
160 .tstc = uart_zynq##port##_tstc, \
161 .putc = uart_zynq##port##_putc, \
162 .puts = uart_zynq##port##_puts, \
163}
164
165DECLARE_PSSERIAL_FUNCTIONS(0);
Michal Simek6c4da352014-04-25 13:45:08 +0200166static struct serial_device uart_zynq_serial0_device =
Michal Simek194846f2012-09-14 00:55:24 +0000167 INIT_PSSERIAL_STRUCTURE(0, "ttyPS0");
168DECLARE_PSSERIAL_FUNCTIONS(1);
Michal Simek6c4da352014-04-25 13:45:08 +0200169static struct serial_device uart_zynq_serial1_device =
Michal Simek194846f2012-09-14 00:55:24 +0000170 INIT_PSSERIAL_STRUCTURE(1, "ttyPS1");
171
Michal Simekc9416b92014-02-24 11:16:33 +0100172#ifdef CONFIG_OF_CONTROL
173__weak struct serial_device *default_serial_console(void)
174{
175 const void *blob = gd->fdt_blob;
176 int node;
177 unsigned int base_addr;
178
179 node = fdt_path_offset(blob, "serial0");
180 if (node < 0)
181 return NULL;
182
183 base_addr = fdtdec_get_addr(blob, node, "reg");
184 if (base_addr == FDT_ADDR_T_NONE)
185 return NULL;
186
187 if (base_addr == ZYNQ_SERIAL_BASEADDR0)
188 return &uart_zynq_serial0_device;
189
190 if (base_addr == ZYNQ_SERIAL_BASEADDR1)
191 return &uart_zynq_serial1_device;
192
193 return NULL;
194}
195#else
Michal Simek194846f2012-09-14 00:55:24 +0000196__weak struct serial_device *default_serial_console(void)
197{
Michal Simekbf834952013-12-19 23:38:58 +0530198#if defined(CONFIG_ZYNQ_SERIAL_UART0)
Michal Simek194846f2012-09-14 00:55:24 +0000199 if (uart_zynq_ports[0])
200 return &uart_zynq_serial0_device;
Michal Simekbf834952013-12-19 23:38:58 +0530201#endif
202#if defined(CONFIG_ZYNQ_SERIAL_UART1)
Michal Simek194846f2012-09-14 00:55:24 +0000203 if (uart_zynq_ports[1])
204 return &uart_zynq_serial1_device;
Michal Simekbf834952013-12-19 23:38:58 +0530205#endif
Michal Simek194846f2012-09-14 00:55:24 +0000206 return NULL;
207}
Michal Simekc9416b92014-02-24 11:16:33 +0100208#endif
Tom Rini51d81022012-10-08 14:46:23 -0700209
Michal Simek870e0bd2014-04-25 13:46:28 +0200210void zynq_serial_initialize(void)
Tom Rini51d81022012-10-08 14:46:23 -0700211{
Tom Rini51d81022012-10-08 14:46:23 -0700212 serial_register(&uart_zynq_serial0_device);
Tom Rini51d81022012-10-08 14:46:23 -0700213 serial_register(&uart_zynq_serial1_device);
Tom Rini51d81022012-10-08 14:46:23 -0700214}