Peng Fan | 52df705 | 2018-01-10 13:20:45 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (C) 2016 Freescale Semiconductor, Inc. |
| 3 | * Copyright 2017 NXP |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public License |
| 7 | * as published by the Free Software Foundation; either version 2 |
| 8 | * of the License, or (at your option) any later version. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include "fsl-imx8-ca53.dtsi" |
| 17 | #include <dt-bindings/clock/imx8mq-clock.h> |
| 18 | #include <dt-bindings/gpio/gpio.h> |
| 19 | #include <dt-bindings/input/input.h> |
| 20 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 21 | #include <dt-bindings/pinctrl/pins-imx8mq.h> |
| 22 | #include <dt-bindings/thermal/thermal.h> |
| 23 | |
| 24 | / { |
| 25 | compatible = "fsl,imx8mq"; |
| 26 | interrupt-parent = <&gpc>; |
| 27 | #address-cells = <2>; |
| 28 | #size-cells = <2>; |
| 29 | |
| 30 | aliases { |
| 31 | ethernet0 = &fec1; |
| 32 | mmc0 = &usdhc1; |
| 33 | mmc1 = &usdhc2; |
| 34 | gpio0 = &gpio1; |
| 35 | gpio1 = &gpio2; |
| 36 | gpio2 = &gpio3; |
| 37 | gpio3 = &gpio4; |
| 38 | gpio4 = &gpio5; |
| 39 | i2c0 = &i2c1; |
| 40 | i2c1 = &i2c2; |
| 41 | i2c2 = &i2c3; |
| 42 | i2c3 = &i2c4; |
| 43 | }; |
| 44 | |
| 45 | memory@40000000 { |
| 46 | device_type = "memory"; |
| 47 | reg = <0x00000000 0x40000000 0 0xc0000000>; |
| 48 | }; |
| 49 | |
| 50 | gic: interrupt-controller@38800000 { |
| 51 | compatible = "arm,gic-v3"; |
| 52 | reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ |
| 53 | <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ |
| 54 | #interrupt-cells = <3>; |
| 55 | interrupt-controller; |
| 56 | interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| 57 | interrupt-parent = <&gic>; |
| 58 | }; |
| 59 | |
| 60 | timer { |
| 61 | compatible = "arm,armv8-timer"; |
| 62 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | |
| 63 | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ |
| 64 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | |
| 65 | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ |
| 66 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | |
| 67 | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ |
| 68 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | |
| 69 | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ |
| 70 | clock-frequency = <8333333>; |
| 71 | interrupt-parent = <&gic>; |
| 72 | }; |
| 73 | |
| 74 | power: power-controller { |
| 75 | compatible = "fsl,imx8mq-pm-domain"; |
| 76 | num-domains = <11>; |
| 77 | #power-domain-cells = <1>; |
| 78 | }; |
| 79 | |
| 80 | pwm2: pwm@30670000 { |
| 81 | compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; |
| 82 | reg = <0x0 0x30670000 0x0 0x10000>; |
| 83 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
| 84 | clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>, |
| 85 | <&clk IMX8MQ_CLK_PWM2_ROOT>; |
| 86 | clock-names = "ipg", "per"; |
| 87 | #pwm-cells = <2>; |
| 88 | status = "disabled"; |
| 89 | }; |
| 90 | |
| 91 | gpio1: gpio@30200000 { |
| 92 | compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; |
| 93 | reg = <0x0 0x30200000 0x0 0x10000>; |
| 94 | interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, |
| 95 | <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
| 96 | gpio-controller; |
| 97 | #gpio-cells = <2>; |
| 98 | interrupt-controller; |
| 99 | #interrupt-cells = <2>; |
| 100 | }; |
| 101 | |
| 102 | gpio2: gpio@30210000 { |
| 103 | compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; |
| 104 | reg = <0x0 0x30210000 0x0 0x10000>; |
| 105 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, |
| 106 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; |
| 107 | gpio-controller; |
| 108 | #gpio-cells = <2>; |
| 109 | interrupt-controller; |
| 110 | #interrupt-cells = <2>; |
| 111 | }; |
| 112 | |
| 113 | gpio3: gpio@30220000 { |
| 114 | compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; |
| 115 | reg = <0x0 0x30220000 0x0 0x10000>; |
| 116 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, |
| 117 | <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
| 118 | gpio-controller; |
| 119 | #gpio-cells = <2>; |
| 120 | interrupt-controller; |
| 121 | #interrupt-cells = <2>; |
| 122 | }; |
| 123 | |
| 124 | gpio4: gpio@30230000 { |
| 125 | compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; |
| 126 | reg = <0x0 0x30230000 0x0 0x10000>; |
| 127 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, |
| 128 | <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
| 129 | gpio-controller; |
| 130 | #gpio-cells = <2>; |
| 131 | interrupt-controller; |
| 132 | #interrupt-cells = <2>; |
| 133 | }; |
| 134 | |
| 135 | gpio5: gpio@30240000 { |
| 136 | compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; |
| 137 | reg = <0x0 0x30240000 0x0 0x10000>; |
| 138 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, |
| 139 | <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
| 140 | gpio-controller; |
| 141 | #gpio-cells = <2>; |
| 142 | interrupt-controller; |
| 143 | #interrupt-cells = <2>; |
| 144 | }; |
| 145 | |
| 146 | tmu: tmu@30260000 { |
| 147 | compatible = "fsl,imx8mq-tmu"; |
| 148 | reg = <0x0 0x30260000 0x0 0x10000>; |
| 149 | interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; |
| 150 | little-endian; |
| 151 | u-boot,dm-pre-reloc; |
| 152 | fsl,tmu-range = <0xa0000 0x90026 0x8004a 0x1006a>; |
| 153 | fsl,tmu-calibration = <0x00000000 0x00000020 |
| 154 | 0x00000001 0x00000028 |
| 155 | 0x00000002 0x00000030 |
| 156 | 0x00000003 0x00000038 |
| 157 | 0x00000004 0x00000040 |
| 158 | 0x00000005 0x00000048 |
| 159 | 0x00000006 0x00000050 |
| 160 | 0x00000007 0x00000058 |
| 161 | 0x00000008 0x00000060 |
| 162 | 0x00000009 0x00000068 |
| 163 | 0x0000000a 0x00000070 |
| 164 | 0x0000000b 0x00000077 |
| 165 | |
| 166 | 0x00010000 0x00000057 |
| 167 | 0x00010001 0x0000005b |
| 168 | 0x00010002 0x0000005f |
| 169 | 0x00010003 0x00000063 |
| 170 | 0x00010004 0x00000067 |
| 171 | 0x00010005 0x0000006b |
| 172 | 0x00010006 0x0000006f |
| 173 | 0x00010007 0x00000073 |
| 174 | 0x00010008 0x00000077 |
| 175 | 0x00010009 0x0000007b |
| 176 | 0x0001000a 0x0000007f |
| 177 | |
| 178 | 0x00020000 0x00000002 |
| 179 | 0x00020001 0x0000000e |
| 180 | 0x00020002 0x0000001a |
| 181 | 0x00020003 0x00000026 |
| 182 | 0x00020004 0x00000032 |
| 183 | 0x00020005 0x0000003e |
| 184 | 0x00020006 0x0000004a |
| 185 | 0x00020007 0x00000056 |
| 186 | 0x00020008 0x00000062 |
| 187 | |
| 188 | 0x00030000 0x00000000 |
| 189 | 0x00030001 0x00000008 |
| 190 | 0x00030002 0x00000010 |
| 191 | 0x00030003 0x00000018 |
| 192 | 0x00030004 0x00000020 |
| 193 | 0x00030005 0x00000028 |
| 194 | 0x00030006 0x00000030 |
| 195 | 0x00030007 0x00000038>; |
| 196 | #thermal-sensor-cells = <0>; |
| 197 | }; |
| 198 | |
| 199 | thermal-zones { |
| 200 | /* cpu thermal */ |
| 201 | cpu-thermal { |
| 202 | polling-delay-passive = <250>; |
| 203 | polling-delay = <2000>; |
| 204 | thermal-sensors = <&tmu>; |
| 205 | trips { |
| 206 | cpu_alert0: trip0 { |
| 207 | temperature = <85000>; |
| 208 | hysteresis = <2000>; |
| 209 | type = "passive"; |
| 210 | }; |
| 211 | cpu_crit0: trip1 { |
| 212 | temperature = <125000>; |
| 213 | hysteresis = <2000>; |
| 214 | type = "critical"; |
| 215 | }; |
| 216 | }; |
| 217 | |
| 218 | cooling-maps { |
| 219 | map0 { |
| 220 | trip = <&cpu_alert0>; |
| 221 | cooling-device = |
| 222 | <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| 223 | }; |
| 224 | }; |
| 225 | }; |
| 226 | }; |
| 227 | |
| 228 | lcdif: lcdif@30320000 { |
| 229 | compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif"; |
| 230 | reg = <0x0 0x30320000 0x0 0x10000>; |
| 231 | clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_DIV>, |
| 232 | <&clk IMX8MQ_CLK_DUMMY>, |
| 233 | <&clk IMX8MQ_CLK_DUMMY>; |
| 234 | clock-names = "pix", "axi", "disp_axi"; |
| 235 | assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_SRC>; |
| 236 | assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>; |
| 237 | assigned-clock-rate = <594000000>; |
| 238 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
| 239 | status = "disabled"; |
| 240 | }; |
| 241 | |
| 242 | iomuxc: iomuxc@30330000 { |
| 243 | compatible = "fsl,imx8mq-iomuxc"; |
| 244 | reg = <0x0 0x30330000 0x0 0x10000>; |
| 245 | }; |
| 246 | |
| 247 | gpr: iomuxc-gpr@30340000 { |
| 248 | compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx7d-iomuxc-gpr", "syscon"; |
| 249 | reg = <0x0 0x30340000 0x0 0x10000>; |
| 250 | }; |
| 251 | |
| 252 | ocotp: ocotp-ctrl@30350000 { |
| 253 | compatible = "fsl,imx8mq-ocotp", "fsl,imx7d-ocotp", "syscon"; |
| 254 | reg = <0x0 0x30350000 0x0 0x10000>; |
| 255 | }; |
| 256 | |
| 257 | anatop: anatop@30360000 { |
| 258 | compatible = "fsl,imx8mq-anatop", "fsl,imx6q-anatop", |
| 259 | "syscon", "simple-bus"; |
| 260 | reg = <0x0 0x30360000 0x0 0x10000>; |
| 261 | interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; |
| 262 | }; |
| 263 | |
| 264 | clk: ccm@30380000 { |
| 265 | compatible = "fsl,imx8mq-ccm"; |
| 266 | reg = <0x0 0x30380000 0x0 0x10000>; |
| 267 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, |
| 268 | <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| 269 | #clock-cells = <1>; |
| 270 | }; |
| 271 | |
| 272 | gpc: gpc@303a0000 { |
| 273 | compatible = "fsl,imx8mq-gpc", "fsl,imx7d-gpc", "syscon"; |
| 274 | reg = <0x0 0x303a0000 0x0 0x10000>; |
| 275 | interrupt-controller; |
| 276 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; |
| 277 | #interrupt-cells = <3>; |
| 278 | interrupt-parent = <&gic>; |
| 279 | }; |
| 280 | |
| 281 | usdhc1: usdhc@30b40000 { |
| 282 | compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc"; |
| 283 | reg = <0x0 0x30b40000 0x0 0x10000>; |
| 284 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
| 285 | clocks = <&clk IMX8MQ_CLK_DUMMY>, |
| 286 | <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>, |
| 287 | <&clk IMX8MQ_CLK_USDHC1_ROOT>; |
| 288 | clock-names = "ipg", "ahb", "per"; |
| 289 | assigned-clocks = <&clk IMX8MQ_CLK_USDHC1_DIV>; |
| 290 | assigned-clock-rates = <400000000>; |
| 291 | fsl,tuning-start-tap = <20>; |
| 292 | fsl,tuning-step= <2>; |
| 293 | bus-width = <4>; |
| 294 | status = "disabled"; |
| 295 | }; |
| 296 | |
| 297 | usdhc2: usdhc@30b50000 { |
| 298 | compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc"; |
| 299 | reg = <0x0 0x30b50000 0x0 0x10000>; |
| 300 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
| 301 | clocks = <&clk IMX8MQ_CLK_DUMMY>, |
| 302 | <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>, |
| 303 | <&clk IMX8MQ_CLK_USDHC2_ROOT>; |
| 304 | clock-names = "ipg", "ahb", "per"; |
| 305 | fsl,tuning-start-tap = <20>; |
| 306 | fsl,tuning-step= <2>; |
| 307 | bus-width = <4>; |
| 308 | status = "disabled"; |
| 309 | }; |
| 310 | |
| 311 | fec1: ethernet@30be0000 { |
| 312 | compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec"; |
| 313 | reg = <0x0 0x30be0000 0x0 0x10000>; |
| 314 | interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, |
| 315 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, |
| 316 | <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
| 317 | clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>, |
| 318 | <&clk IMX8MQ_CLK_ENET1_ROOT>, |
| 319 | <&clk IMX8MQ_CLK_ENET_TIMER_DIV>, |
| 320 | <&clk IMX8MQ_CLK_ENET_REF_DIV>, |
| 321 | <&clk IMX8MQ_CLK_ENET_PHY_REF_DIV>; |
| 322 | clock-names = "ipg", "ahb", "ptp", |
| 323 | "enet_clk_ref", "enet_out"; |
| 324 | assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI_SRC>, |
| 325 | <&clk IMX8MQ_CLK_ENET_TIMER_SRC>, |
| 326 | <&clk IMX8MQ_CLK_ENET_REF_SRC>, |
| 327 | <&clk IMX8MQ_CLK_ENET_TIMER_DIV>; |
| 328 | assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, |
| 329 | <&clk IMX8MQ_SYS2_PLL_100M>, |
| 330 | <&clk IMX8MQ_SYS2_PLL_125M>; |
| 331 | assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; |
| 332 | stop-mode = <&gpr 0x10 3>; |
| 333 | fsl,num-tx-queues=<3>; |
| 334 | fsl,num-rx-queues=<3>; |
| 335 | fsl,wakeup_irq = <2>; |
| 336 | status = "disabled"; |
| 337 | }; |
| 338 | |
| 339 | imx_ion { |
| 340 | compatible = "fsl,mxc-ion"; |
| 341 | fsl,heap-id = <0>; |
| 342 | }; |
| 343 | |
| 344 | i2c1: i2c@30a20000 { |
| 345 | #address-cells = <1>; |
| 346 | #size-cells = <0>; |
| 347 | compatible = "fsl,imx21-i2c"; |
| 348 | reg = <0x0 0x30a20000 0x0 0x10000>; |
| 349 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
| 350 | clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>; |
| 351 | status = "disabled"; |
| 352 | }; |
| 353 | |
| 354 | i2c2: i2c@30a30000 { |
| 355 | #address-cells = <1>; |
| 356 | #size-cells = <0>; |
| 357 | compatible = "fsl,imx21-i2c"; |
| 358 | reg = <0x0 0x30a30000 0x0 0x10000>; |
| 359 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
| 360 | clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>; |
| 361 | status = "disabled"; |
| 362 | }; |
| 363 | |
| 364 | i2c3: i2c@30a40000 { |
| 365 | #address-cells = <1>; |
| 366 | #size-cells = <0>; |
| 367 | compatible = "fsl,imx21-i2c"; |
| 368 | reg = <0x0 0x30a40000 0x0 0x10000>; |
| 369 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
| 370 | clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>; |
| 371 | status = "disabled"; |
| 372 | }; |
| 373 | |
| 374 | i2c4: i2c@30a50000 { |
| 375 | #address-cells = <1>; |
| 376 | #size-cells = <0>; |
| 377 | compatible = "fsl,imx21-i2c"; |
| 378 | reg = <0x0 0x30a50000 0x0 0x10000>; |
| 379 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
| 380 | clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>; |
| 381 | status = "disabled"; |
| 382 | }; |
| 383 | |
| 384 | wdog1: wdog@30280000 { |
| 385 | compatible = "fsl,imx21-wdt"; |
| 386 | reg = <0 0x30280000 0 0x10000>; |
| 387 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; |
| 388 | clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>; |
| 389 | status = "disabled"; |
| 390 | }; |
| 391 | |
| 392 | wdog2: wdog@30290000 { |
| 393 | compatible = "fsl,imx21-wdt"; |
| 394 | reg = <0 0x30290000 0 0x10000>; |
| 395 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
| 396 | clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>; |
| 397 | status = "disabled"; |
| 398 | }; |
| 399 | |
| 400 | wdog3: wdog@302a0000 { |
| 401 | compatible = "fsl,imx21-wdt"; |
| 402 | reg = <0 0x302a0000 0 0x10000>; |
| 403 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| 404 | clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>; |
| 405 | status = "disabled"; |
| 406 | }; |
| 407 | |
| 408 | dma_cap: dma_cap { |
| 409 | compatible = "dma-capability"; |
| 410 | only-dma-mask32 = <1>; |
| 411 | }; |
| 412 | |
| 413 | qspi: qspi@30bb0000 { |
| 414 | #address-cells = <1>; |
| 415 | #size-cells = <0>; |
| 416 | compatible = "fsl,imx7d-qspi"; |
| 417 | reg = <0 0x30bb0000 0 0x10000>, <0 0x08000000 0 0x10000000>; |
| 418 | reg-names = "QuadSPI", "QuadSPI-memory"; |
| 419 | interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; |
| 420 | clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>, |
| 421 | <&clk IMX8MQ_CLK_QSPI_ROOT>; |
| 422 | clock-names = "qspi_en", "qspi"; |
| 423 | status = "disabled"; |
| 424 | }; |
| 425 | }; |
| 426 | |
| 427 | &A53_0 { |
| 428 | #cooling-cells = <2>; |
| 429 | }; |