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Kumar Gala9490a7f2008-07-25 13:31:05 -05001/*
ramneek mehresh3d7506f2012-04-18 19:39:53 +00002 * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc.
Kumar Gala9490a7f2008-07-25 13:31:05 -05003 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Kumar Gala9490a7f2008-07-25 13:31:05 -05005 */
6
7/*
8 * mpc8536ds board configuration file
9 *
10 */
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
Kumar Galac7e1a432010-05-21 04:14:49 -050014#include "../board/freescale/common/ics307_clk.h"
15
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020016#ifdef CONFIG_SDCARD
Mingkai Hue40ac482009-09-23 15:20:38 +080017#define CONFIG_RAMBOOT_SDCARD 1
Haijun.Zhange2c9bc52014-04-10 11:16:30 +080018#define CONFIG_SYS_TEXT_BASE 0xf8f40000
Kumar Gala7a577fd2011-01-12 02:48:53 -060019#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
Mingkai Hue40ac482009-09-23 15:20:38 +080020#endif
21
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020022#ifdef CONFIG_SPIFLASH
Mingkai Hue40ac482009-09-23 15:20:38 +080023#define CONFIG_RAMBOOT_SPIFLASH 1
Haijun.Zhange2c9bc52014-04-10 11:16:30 +080024#define CONFIG_SYS_TEXT_BASE 0xf8f40000
Kumar Gala7a577fd2011-01-12 02:48:53 -060025#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
Wolfgang Denk2ae18242010-10-06 09:05:45 +020026#endif
27
28#ifndef CONFIG_SYS_TEXT_BASE
Haijun.Zhangc6e8f492014-02-13 09:03:02 +080029#define CONFIG_SYS_TEXT_BASE 0xeff40000
Mingkai Hue40ac482009-09-23 15:20:38 +080030#endif
31
Kumar Gala7a577fd2011-01-12 02:48:53 -060032#ifndef CONFIG_RESET_VECTOR_ADDRESS
33#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
34#endif
35
Haiying Wang96196a12010-11-10 15:37:13 -050036#ifndef CONFIG_SYS_MONITOR_BASE
37#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
38#endif
39
Kumar Gala9490a7f2008-07-25 13:31:05 -050040#define CONFIG_PCI1 1 /* Enable PCI controller 1 */
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -040041#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
42#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
43#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
Kumar Gala9490a7f2008-07-25 13:31:05 -050044#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Gabor Juhos842033e2013-05-30 07:06:12 +000045#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
Kumar Gala9490a7f2008-07-25 13:31:05 -050046#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
Kumar Gala0151cba2008-10-21 11:33:58 -050047#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Kumar Gala9490a7f2008-07-25 13:31:05 -050048
Kumar Gala9490a7f2008-07-25 13:31:05 -050049
50#define CONFIG_TSEC_ENET /* tsec ethernet support */
51#define CONFIG_ENV_OVERWRITE
52
Kumar Galac7e1a432010-05-21 04:14:49 -050053#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
54#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
Kumar Gala9490a7f2008-07-25 13:31:05 -050055#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
Kumar Gala9490a7f2008-07-25 13:31:05 -050056
57/*
58 * These can be toggled for performance analysis, otherwise use default.
59 */
60#define CONFIG_L2_CACHE /* toggle L2 cache */
61#define CONFIG_BTB /* toggle branch predition */
Kumar Gala9490a7f2008-07-25 13:31:05 -050062
63#define CONFIG_ENABLE_36BIT_PHYS 1
64
Kumar Gala337f9fd2009-07-30 15:54:07 -050065#ifdef CONFIG_PHYS_64BIT
66#define CONFIG_ADDR_MAP 1
67#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
68#endif
69
Mingkai Hu07355702009-09-23 15:19:32 +080070#define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */
71#define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */
Kumar Gala9490a7f2008-07-25 13:31:05 -050072#define CONFIG_PANIC_HANG /* do not reset board on panic */
73
74/*
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +080075 * Config the L2 Cache as L2 SRAM
76 */
77#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
78#ifdef CONFIG_PHYS_64BIT
79#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
80#else
81#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
82#endif
83#define CONFIG_SYS_L2_SIZE (512 << 10)
84#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
85
Timur Tabie46fedf2011-08-04 18:03:41 -050086#define CONFIG_SYS_CCSRBAR 0xffe00000
87#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Kumar Gala9490a7f2008-07-25 13:31:05 -050088
Kumar Gala8d22ddc2011-11-09 09:10:49 -060089#if defined(CONFIG_NAND_SPL)
Timur Tabie46fedf2011-08-04 18:03:41 -050090#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +080091#endif
92
Kumar Gala9490a7f2008-07-25 13:31:05 -050093/* DDR Setup */
Kumar Gala337f9fd2009-07-30 15:54:07 -050094#define CONFIG_VERY_BIG_RAM
Kumar Gala9490a7f2008-07-25 13:31:05 -050095#undef CONFIG_FSL_DDR_INTERACTIVE
96#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
97#define CONFIG_DDR_SPD
Kumar Gala9490a7f2008-07-25 13:31:05 -050098
Dave Liu9b0ad1b2008-10-28 17:53:38 +080099#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500100#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
101
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
103#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Gala9490a7f2008-07-25 13:31:05 -0500104
Kumar Gala9490a7f2008-07-25 13:31:05 -0500105#define CONFIG_DIMM_SLOTS_PER_CTLR 1
106#define CONFIG_CHIP_SELECTS_PER_CTRL 2
107
108/* I2C addresses of SPD EEPROMs */
109#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_SPD_BUS_NUM 1
Kumar Gala9490a7f2008-07-25 13:31:05 -0500111
112/* These are used when DDR doesn't use SPD. */
Mingkai Hu07355702009-09-23 15:19:32 +0800113#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
Mingkai Hu07355702009-09-23 15:19:32 +0800115#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_DDR_TIMING_3 0x00000000
117#define CONFIG_SYS_DDR_TIMING_0 0x00260802
118#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
119#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
120#define CONFIG_SYS_DDR_MODE_1 0x00480432
121#define CONFIG_SYS_DDR_MODE_2 0x00000000
122#define CONFIG_SYS_DDR_INTERVAL 0x06180100
123#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
124#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
125#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
126#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
Mingkai Hu07355702009-09-23 15:19:32 +0800127#define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_DDR_CONTROL2 0x04400010
Kumar Gala9490a7f2008-07-25 13:31:05 -0500129
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
131#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
132#define CONFIG_SYS_DDR_SBE 0x00010000
Kumar Gala9490a7f2008-07-25 13:31:05 -0500133
Kumar Gala9490a7f2008-07-25 13:31:05 -0500134/* Make sure required options are set */
135#ifndef CONFIG_SPD_EEPROM
136#error ("CONFIG_SPD_EEPROM is required")
137#endif
138
139#undef CONFIG_CLOCKS_IN_MHZ
140
Kumar Gala9490a7f2008-07-25 13:31:05 -0500141/*
142 * Memory map -- xxx -this is wrong, needs updating
143 *
144 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
145 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
146 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
147 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
148 *
149 * Localbus cacheable (TBD)
150 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
151 *
152 * Localbus non-cacheable
Jason Jinc57fc282008-10-31 05:07:04 -0500153 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable
Kumar Gala9490a7f2008-07-25 13:31:05 -0500154 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
Jason Jinc57fc282008-10-31 05:07:04 -0500155 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
Kumar Gala9490a7f2008-07-25 13:31:05 -0500156 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
157 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
158 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
159 */
160
161/*
162 * Local Bus Definitions
163 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
Kumar Gala337f9fd2009-07-30 15:54:07 -0500165#ifdef CONFIG_PHYS_64BIT
166#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
167#else
Kumar Galac953ddf2008-12-02 14:19:34 -0600168#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
Kumar Gala337f9fd2009-07-30 15:54:07 -0500169#endif
Kumar Gala9490a7f2008-07-25 13:31:05 -0500170
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800171#define CONFIG_FLASH_BR_PRELIM \
Timur Tabi7ee41102012-07-06 07:39:26 +0000172 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800173#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
Kumar Gala9490a7f2008-07-25 13:31:05 -0500174
Mingkai Hu07355702009-09-23 15:19:32 +0800175#define CONFIG_SYS_BR1_PRELIM \
176 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
177 | BR_PS_16 | BR_V)
Kumar Galac953ddf2008-12-02 14:19:34 -0600178#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
Kumar Gala9490a7f2008-07-25 13:31:05 -0500179
Mingkai Hu07355702009-09-23 15:19:32 +0800180#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \
181 CONFIG_SYS_FLASH_BASE_PHYS }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_FLASH_QUIET_TEST
Kumar Gala9490a7f2008-07-25 13:31:05 -0500183#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
184
Mingkai Hu07355702009-09-23 15:19:32 +0800185#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
186#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#undef CONFIG_SYS_FLASH_CHECKSUM
Mingkai Hu07355702009-09-23 15:19:32 +0800188#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
189#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500190
Masahiro Yamada02344462014-06-04 10:26:50 +0900191#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800192#define CONFIG_SYS_RAMBOOT
Kumar Galaa55bb832010-11-29 14:32:11 -0600193#define CONFIG_SYS_EXTRA_ENV_RELOC
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800194#else
195#undef CONFIG_SYS_RAMBOOT
196#endif
197
Kumar Gala9490a7f2008-07-25 13:31:05 -0500198#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_FLASH_CFI
200#define CONFIG_SYS_FLASH_EMPTY_INFO
201#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
Kumar Gala9490a7f2008-07-25 13:31:05 -0500202
203#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
204
Ramneek Mehresh68d42302011-06-07 10:10:43 +0000205#define CONFIG_HWCONFIG /* enable hwconfig */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500206#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
207#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
Kumar Gala337f9fd2009-07-30 15:54:07 -0500208#ifdef CONFIG_PHYS_64BIT
209#define PIXIS_BASE_PHYS 0xfffdf0000ull
210#else
Kumar Gala52b565f2008-12-02 14:19:33 -0600211#define PIXIS_BASE_PHYS PIXIS_BASE
Kumar Gala337f9fd2009-07-30 15:54:07 -0500212#endif
Kumar Gala9490a7f2008-07-25 13:31:05 -0500213
Kumar Gala52b565f2008-12-02 14:19:33 -0600214#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
Mingkai Hu07355702009-09-23 15:19:32 +0800215#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500216
217#define PIXIS_ID 0x0 /* Board ID at offset 0 */
218#define PIXIS_VER 0x1 /* Board version at offset 1 */
219#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
220#define PIXIS_CSR 0x3 /* PIXIS General control/status register */
221#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
222#define PIXIS_PWR 0x5 /* PIXIS Power status register */
223#define PIXIS_AUX 0x6 /* Auxiliary 1 register */
224#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
225#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
226#define PIXIS_VCTL 0x10 /* VELA Control Register */
227#define PIXIS_VSTAT 0x11 /* VELA Status Register */
228#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
229#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
230#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
231#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
Kumar Gala6bb5b412009-07-14 22:42:01 -0500232#define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */
233#define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
234#define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */
235#define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */
236#define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */
237#define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */
238#define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500239#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
240#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
241#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
242#define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */
243#define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */
244#define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */
245#define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */
246#define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */
247#define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */
248#define PIXIS_VWATCH 0x24 /* Watchdog Register */
249#define PIXIS_LED 0x25 /* LED Register */
250
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800251#define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */
252
Kumar Gala9490a7f2008-07-25 13:31:05 -0500253/* old pixis referenced names */
254#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
255#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
Matthew McClintock509e19c2011-02-25 16:20:11 -0600256#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e
Kumar Gala9490a7f2008-07-25 13:31:05 -0500257
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_INIT_RAM_LOCK 1
259#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200260#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500261
Mingkai Hu07355702009-09-23 15:19:32 +0800262#define CONFIG_SYS_GBL_DATA_OFFSET \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200263 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Kumar Gala9490a7f2008-07-25 13:31:05 -0500265
Mingkai Hu07355702009-09-23 15:19:32 +0800266#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
267#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500268
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800269#ifndef CONFIG_NAND_SPL
Kumar Gala337f9fd2009-07-30 15:54:07 -0500270#define CONFIG_SYS_NAND_BASE 0xffa00000
271#ifdef CONFIG_PHYS_64BIT
272#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
273#else
274#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
275#endif
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800276#else
277#define CONFIG_SYS_NAND_BASE 0xfff00000
278#ifdef CONFIG_PHYS_64BIT
279#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
280#else
281#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
282#endif
283#endif
Jason Jinc57fc282008-10-31 05:07:04 -0500284#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
285 CONFIG_SYS_NAND_BASE + 0x40000, \
286 CONFIG_SYS_NAND_BASE + 0x80000, \
287 CONFIG_SYS_NAND_BASE + 0xC0000}
288#define CONFIG_SYS_MAX_NAND_DEVICE 4
Jason Jinc57fc282008-10-31 05:07:04 -0500289#define CONFIG_CMD_NAND 1
290#define CONFIG_NAND_FSL_ELBC 1
291#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
292
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800293/* NAND boot: 4K NAND loader config */
294#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
Haijun.Zhangc6e8f492014-02-13 09:03:02 +0800295#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800296#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
297#define CONFIG_SYS_NAND_U_BOOT_START \
298 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
299#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
300#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
301#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
302
Jason Jinc57fc282008-10-31 05:07:04 -0500303/* NAND flash config */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500304#define CONFIG_SYS_NAND_BR_PRELIM \
Mingkai Hu07355702009-09-23 15:19:32 +0800305 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
306 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
307 | BR_PS_8 /* Port Size = 8 bit */ \
308 | BR_MS_FCM /* MSEL = FCM */ \
309 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500310#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
Mingkai Hu07355702009-09-23 15:19:32 +0800311 | OR_FCM_PGS /* Large Page*/ \
312 | OR_FCM_CSCT \
313 | OR_FCM_CST \
314 | OR_FCM_CHT \
315 | OR_FCM_SCY_1 \
316 | OR_FCM_TRLX \
317 | OR_FCM_EHTR)
Jason Jinc57fc282008-10-31 05:07:04 -0500318
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800319#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
320#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500321#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
322#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Jason Jinc57fc282008-10-31 05:07:04 -0500323
Mingkai Hu07355702009-09-23 15:19:32 +0800324#define CONFIG_SYS_BR4_PRELIM \
Timur Tabi7ee41102012-07-06 07:39:26 +0000325 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
Mingkai Hu07355702009-09-23 15:19:32 +0800326 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
327 | BR_PS_8 /* Port Size = 8 bit */ \
328 | BR_MS_FCM /* MSEL = FCM */ \
329 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500330#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Mingkai Hu07355702009-09-23 15:19:32 +0800331#define CONFIG_SYS_BR5_PRELIM \
Timur Tabi7ee41102012-07-06 07:39:26 +0000332 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
Mingkai Hu07355702009-09-23 15:19:32 +0800333 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
334 | BR_PS_8 /* Port Size = 8 bit */ \
335 | BR_MS_FCM /* MSEL = FCM */ \
336 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500337#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Jason Jinc57fc282008-10-31 05:07:04 -0500338
Mingkai Hu07355702009-09-23 15:19:32 +0800339#define CONFIG_SYS_BR6_PRELIM \
Timur Tabi7ee41102012-07-06 07:39:26 +0000340 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
Mingkai Hu07355702009-09-23 15:19:32 +0800341 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
342 | BR_PS_8 /* Port Size = 8 bit */ \
343 | BR_MS_FCM /* MSEL = FCM */ \
344 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500345#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Jason Jinc57fc282008-10-31 05:07:04 -0500346
Kumar Gala9490a7f2008-07-25 13:31:05 -0500347/* Serial Port - controlled on board with jumper J8
348 * open - index 2
349 * shorted - index 1
350 */
351#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352#define CONFIG_SYS_NS16550_SERIAL
353#define CONFIG_SYS_NS16550_REG_SIZE 1
354#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Kumar Gala93341902010-04-07 01:34:11 -0500355#ifdef CONFIG_NAND_SPL
356#define CONFIG_NS16550_MIN_FUNCTIONS
357#endif
Kumar Gala9490a7f2008-07-25 13:31:05 -0500358
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359#define CONFIG_SYS_BAUDRATE_TABLE \
Kumar Gala9490a7f2008-07-25 13:31:05 -0500360 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
361
Mingkai Hu07355702009-09-23 15:19:32 +0800362#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
363#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
Kumar Gala9490a7f2008-07-25 13:31:05 -0500364
Kumar Gala9490a7f2008-07-25 13:31:05 -0500365/*
Kumar Gala9490a7f2008-07-25 13:31:05 -0500366 * I2C
367 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200368#define CONFIG_SYS_I2C
369#define CONFIG_SYS_I2C_FSL
370#define CONFIG_SYS_FSL_I2C_SPEED 400000
371#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
372#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
373#define CONFIG_SYS_FSL_I2C2_SPEED 400000
374#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
375#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
376#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
Kumar Gala9490a7f2008-07-25 13:31:05 -0500377
378/*
379 * I2C2 EEPROM
380 */
Jean-Christophe PLAGNIOL-VILLARD32628c52008-08-30 23:54:58 +0200381#define CONFIG_ID_EEPROM
382#ifdef CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383#define CONFIG_SYS_I2C_EEPROM_NXID
Kumar Gala9490a7f2008-07-25 13:31:05 -0500384#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200385#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
386#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
387#define CONFIG_SYS_EEPROM_BUS_NUM 1
Kumar Gala9490a7f2008-07-25 13:31:05 -0500388
389/*
Xie Xiaoboae2044d2011-10-03 12:18:39 -0700390 * eSPI - Enhanced SPI
391 */
392#define CONFIG_HARD_SPI
Xie Xiaoboae2044d2011-10-03 12:18:39 -0700393
394#if defined(CONFIG_SPI_FLASH)
Xie Xiaoboae2044d2011-10-03 12:18:39 -0700395#define CONFIG_SF_DEFAULT_SPEED 10000000
396#define CONFIG_SF_DEFAULT_MODE 0
397#endif
398
399/*
Kumar Gala9490a7f2008-07-25 13:31:05 -0500400 * General PCI
401 * Memory space is mapped 1-1, but I/O space must start from 0.
402 */
403
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600404#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500405#ifdef CONFIG_PHYS_64BIT
406#define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000
407#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
408#else
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600409#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
410#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500411#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200412#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
Kumar Gala337f9fd2009-07-30 15:54:07 -0500413#define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
414#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
415#ifdef CONFIG_PHYS_64BIT
416#define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull
417#else
418#define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000
419#endif
420#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500421
422/* controller 1, Slot 1, tgtid 1, Base address a000 */
Kumar Gala5f7b31b2010-12-17 15:14:54 -0600423#define CONFIG_SYS_PCIE1_NAME "Slot 1"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600424#define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500425#ifdef CONFIG_PHYS_64BIT
426#define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000
427#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull
428#else
Kumar Gala10795f42008-12-02 16:08:36 -0600429#define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600430#define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500431#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200432#define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600433#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500434#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
435#ifdef CONFIG_PHYS_64BIT
436#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull
437#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200438#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500439#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200440#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500441
442/* controller 2, Slot 2, tgtid 2, Base address 9000 */
Kumar Gala5f7b31b2010-12-17 15:14:54 -0600443#define CONFIG_SYS_PCIE2_NAME "Slot 2"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600444#define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500445#ifdef CONFIG_PHYS_64BIT
446#define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000
447#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull
448#else
Kumar Gala10795f42008-12-02 16:08:36 -0600449#define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600450#define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500451#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200452#define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600453#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500454#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
455#ifdef CONFIG_PHYS_64BIT
456#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull
457#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200458#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500459#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200460#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500461
462/* controller 3, direct to uli, tgtid 3, Base address 8000 */
Kumar Gala5f7b31b2010-12-17 15:14:54 -0600463#define CONFIG_SYS_PCIE3_NAME "Slot 3"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600464#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500465#ifdef CONFIG_PHYS_64BIT
466#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
467#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
468#else
Kumar Gala10795f42008-12-02 16:08:36 -0600469#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600470#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500471#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200472#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600473#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500474#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
475#ifdef CONFIG_PHYS_64BIT
476#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull
477#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200478#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500479#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200480#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500481
482#if defined(CONFIG_PCI)
Kumar Gala9490a7f2008-07-25 13:31:05 -0500483/*PCIE video card used*/
Kumar Galaaca5f012008-12-02 16:08:40 -0600484#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT
Kumar Gala9490a7f2008-07-25 13:31:05 -0500485
486/*PCI video card used*/
Kumar Galaaca5f012008-12-02 16:08:40 -0600487/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
Kumar Gala9490a7f2008-07-25 13:31:05 -0500488
489/* video */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500490
491#if defined(CONFIG_VIDEO)
492#define CONFIG_BIOSEMU
Kumar Gala9490a7f2008-07-25 13:31:05 -0500493#define CONFIG_ATI_RADEON_FB
494#define CONFIG_VIDEO_LOGO
Kumar Galaaca5f012008-12-02 16:08:40 -0600495#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
Kumar Gala9490a7f2008-07-25 13:31:05 -0500496#endif
497
498#undef CONFIG_EEPRO100
499#undef CONFIG_TULIP
Kumar Gala9490a7f2008-07-25 13:31:05 -0500500
Kumar Gala9490a7f2008-07-25 13:31:05 -0500501#ifndef CONFIG_PCI_PNP
Kumar Gala5f91ef62008-12-02 16:08:37 -0600502 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
503 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
Kumar Gala9490a7f2008-07-25 13:31:05 -0500504 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
505#endif
506
507#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
508
509#endif /* CONFIG_PCI */
510
511/* SATA */
512#define CONFIG_LIBATA
513#define CONFIG_FSL_SATA
514
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200515#define CONFIG_SYS_SATA_MAX_DEVICE 2
Kumar Gala9490a7f2008-07-25 13:31:05 -0500516#define CONFIG_SATA1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200517#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
518#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
Kumar Gala9490a7f2008-07-25 13:31:05 -0500519#define CONFIG_SATA2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200520#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
521#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
Kumar Gala9490a7f2008-07-25 13:31:05 -0500522
523#ifdef CONFIG_FSL_SATA
524#define CONFIG_LBA48
525#define CONFIG_CMD_SATA
Kumar Gala9490a7f2008-07-25 13:31:05 -0500526#endif
527
528#if defined(CONFIG_TSEC_ENET)
529
Kumar Gala9490a7f2008-07-25 13:31:05 -0500530#define CONFIG_MII 1 /* MII PHY management */
531#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
532#define CONFIG_TSEC1 1
533#define CONFIG_TSEC1_NAME "eTSEC1"
534#define CONFIG_TSEC3 1
535#define CONFIG_TSEC3_NAME "eTSEC3"
536
Jason Jin2e26d832008-10-10 11:41:00 +0800537#define CONFIG_FSL_SGMII_RISER 1
538#define SGMII_RISER_PHY_OFFSET 0x1c
539
Kumar Gala9490a7f2008-07-25 13:31:05 -0500540#define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */
541#define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */
542
543#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
544#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
545
546#define TSEC1_PHYIDX 0
547#define TSEC3_PHYIDX 0
548
549#define CONFIG_ETHPRIME "eTSEC1"
550
551#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
552
553#endif /* CONFIG_TSEC_ENET */
554
555/*
556 * Environment
557 */
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800558
559#if defined(CONFIG_SYS_RAMBOOT)
Masahiro Yamada02344462014-06-04 10:26:50 +0900560#if defined(CONFIG_RAMBOOT_SPIFLASH)
Xie Xiaobo2d4afd42011-10-03 12:54:21 -0700561#define CONFIG_ENV_IS_IN_SPI_FLASH
562#define CONFIG_ENV_SPI_BUS 0
563#define CONFIG_ENV_SPI_CS 0
564#define CONFIG_ENV_SPI_MAX_HZ 10000000
565#define CONFIG_ENV_SPI_MODE 0
566#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
567#define CONFIG_ENV_OFFSET 0xF0000
568#define CONFIG_ENV_SECT_SIZE 0x10000
569#elif defined(CONFIG_RAMBOOT_SDCARD)
570#define CONFIG_ENV_IS_IN_MMC
Fabio Estevam4394d0c2012-01-11 09:20:50 +0000571#define CONFIG_FSL_FIXED_MMC_LOCATION
Xie Xiaobo2d4afd42011-10-03 12:54:21 -0700572#define CONFIG_ENV_SIZE 0x2000
573#define CONFIG_SYS_MMC_ENV_DEV 0
574#else
Mingkai Hue40ac482009-09-23 15:20:38 +0800575 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
576 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
577 #define CONFIG_ENV_SIZE 0x2000
Kumar Gala9490a7f2008-07-25 13:31:05 -0500578#endif
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800579#else
580 #define CONFIG_ENV_IS_IN_FLASH 1
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800581 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800582 #define CONFIG_ENV_SIZE 0x2000
583 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
584#endif
Kumar Gala9490a7f2008-07-25 13:31:05 -0500585
586#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200587#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500588
589/*
590 * Command line configuration.
591 */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500592#define CONFIG_CMD_IRQ
Kumar Gala1c9aa762008-09-22 23:40:42 -0500593#define CONFIG_CMD_IRQ
Becky Bruce199e2622010-06-17 11:37:25 -0500594#define CONFIG_CMD_REGINFO
Kumar Gala9490a7f2008-07-25 13:31:05 -0500595
596#if defined(CONFIG_PCI)
597#define CONFIG_CMD_PCI
Kumar Gala9490a7f2008-07-25 13:31:05 -0500598#endif
599
600#undef CONFIG_WATCHDOG /* watchdog disabled */
601
Andy Fleming80522dc2008-10-30 16:51:33 -0500602#ifdef CONFIG_MMC
603#define CONFIG_FSL_ESDHC
604#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
Fanzc1116ebb2011-10-03 12:18:42 -0700605#endif
606
607/*
608 * USB
609 */
ramneek mehresh3d7506f2012-04-18 19:39:53 +0000610#define CONFIG_HAS_FSL_MPH_USB
611#ifdef CONFIG_HAS_FSL_MPH_USB
Fanzc1116ebb2011-10-03 12:18:42 -0700612#define CONFIG_USB_EHCI
613
614#ifdef CONFIG_USB_EHCI
Fanzc1116ebb2011-10-03 12:18:42 -0700615#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
616#define CONFIG_USB_EHCI_FSL
Fanzc1116ebb2011-10-03 12:18:42 -0700617#endif
ramneek mehresh3d7506f2012-04-18 19:39:53 +0000618#endif
Fanzc1116ebb2011-10-03 12:18:42 -0700619
Kumar Gala9490a7f2008-07-25 13:31:05 -0500620/*
621 * Miscellaneous configurable options
622 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200623#define CONFIG_SYS_LONGHELP /* undef to save memory */
Mingkai Hu07355702009-09-23 15:19:32 +0800624#define CONFIG_CMDLINE_EDITING /* Command-line editing */
Kim Phillips5be58f52010-07-14 19:47:18 -0500625#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200626#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500627#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200628#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500629#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200630#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500631#endif
Mingkai Hu07355702009-09-23 15:19:32 +0800632#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
633 + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200634#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
Mingkai Hu07355702009-09-23 15:19:32 +0800635#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500636
637/*
638 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500639 * have to be in the first 64 MB of memory, since this is
Kumar Gala9490a7f2008-07-25 13:31:05 -0500640 * the maximum mapped by the Linux kernel during initialization.
641 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500642#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
643#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500644
Kumar Gala9490a7f2008-07-25 13:31:05 -0500645#if defined(CONFIG_CMD_KGDB)
646#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500647#endif
648
649/*
650 * Environment Configuration
651 */
652
653/* The mac addresses for all ethernet interface */
654#if defined(CONFIG_TSEC_ENET)
655#define CONFIG_HAS_ETH0
Kumar Gala9490a7f2008-07-25 13:31:05 -0500656#define CONFIG_HAS_ETH1
Kumar Gala9490a7f2008-07-25 13:31:05 -0500657#define CONFIG_HAS_ETH2
Kumar Gala9490a7f2008-07-25 13:31:05 -0500658#define CONFIG_HAS_ETH3
Kumar Gala9490a7f2008-07-25 13:31:05 -0500659#endif
660
661#define CONFIG_IPADDR 192.168.1.254
662
663#define CONFIG_HOSTNAME unknown
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000664#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000665#define CONFIG_BOOTFILE "uImage"
Mingkai Hu07355702009-09-23 15:19:32 +0800666#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500667
668#define CONFIG_SERVERIP 192.168.1.1
669#define CONFIG_GATEWAYIP 192.168.1.1
670#define CONFIG_NETMASK 255.255.255.0
671
672/* default location for tftp and bootm */
673#define CONFIG_LOADADDR 1000000
674
Kumar Gala9490a7f2008-07-25 13:31:05 -0500675#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
676
Kumar Gala9490a7f2008-07-25 13:31:05 -0500677#define CONFIG_EXTRA_ENV_SETTINGS \
Marek Vasut5368c552012-09-23 17:41:24 +0200678"netdev=eth0\0" \
679"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
680"tftpflash=tftpboot $loadaddr $uboot; " \
681 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
682 " +$filesize; " \
683 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
684 " +$filesize; " \
685 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
686 " $filesize; " \
687 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
688 " +$filesize; " \
689 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
690 " $filesize\0" \
691"consoledev=ttyS0\0" \
692"ramdiskaddr=2000000\0" \
693"ramdiskfile=8536ds/ramdisk.uboot\0" \
Scott Woodb24a4f62016-07-19 17:52:06 -0500694"fdtaddr=1e00000\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200695"fdtfile=8536ds/mpc8536ds.dtb\0" \
696"bdev=sda3\0" \
697"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
Kumar Gala9490a7f2008-07-25 13:31:05 -0500698
699#define CONFIG_HDBOOT \
700 "setenv bootargs root=/dev/$bdev rw " \
701 "console=$consoledev,$baudrate $othbootargs;" \
702 "tftp $loadaddr $bootfile;" \
703 "tftp $fdtaddr $fdtfile;" \
704 "bootm $loadaddr - $fdtaddr"
705
706#define CONFIG_NFSBOOTCOMMAND \
707 "setenv bootargs root=/dev/nfs rw " \
708 "nfsroot=$serverip:$rootpath " \
709 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
710 "console=$consoledev,$baudrate $othbootargs;" \
711 "tftp $loadaddr $bootfile;" \
712 "tftp $fdtaddr $fdtfile;" \
713 "bootm $loadaddr - $fdtaddr"
714
715#define CONFIG_RAMBOOTCOMMAND \
716 "setenv bootargs root=/dev/ram rw " \
717 "console=$consoledev,$baudrate $othbootargs;" \
718 "tftp $ramdiskaddr $ramdiskfile;" \
719 "tftp $loadaddr $bootfile;" \
720 "tftp $fdtaddr $fdtfile;" \
721 "bootm $loadaddr $ramdiskaddr $fdtaddr"
722
723#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
724
725#endif /* __CONFIG_H */