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Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +00001/*
2 * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
3 * (C) Copyright 2010 DAVE Srl <www.dave.eu>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +00006 */
7
8/*
9 * ifm AC14xx (MPC5121e based) board configuration file
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15#define CONFIG_AC14XX 1
Anatolij Gustschin37cf49c2014-10-21 13:47:02 +020016
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +000017/*
18 * Memory map for the ifm AC14xx board:
19 *
20 * 0x0000_0000-0x0FFF_FFFF DDR RAM (256 MB)
21 * 0x3000_0000-0x3001_FFFF On Chip SRAM (128 KB)
22 * 0x8000_0000-0x803F_FFFF IMMR (4 MB)
23 * 0xE000_0000-0xEFFF_FFFF several LPB attached hardware (CSx)
24 * 0xFC00_0000-0xFFFF_FFFF NOR Boot FLASH (64 MB)
25 */
26
27/*
28 * High Level Configuration Options
29 */
30#define CONFIG_E300 1 /* E300 Family */
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +000031
32#define CONFIG_SYS_TEXT_BASE 0xFFF00000
33
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +000034#define CONFIG_SYS_MPC512X_CLKIN 25000000 /* in Hz */
35#define SCFR1_IPS_DIV 2
36#define SCFR1_LPC_DIV 2
37#define SCFR1_NFC_DIV 2
38#define SCFR1_DIU_DIV 240
39
40#define CONFIG_MISC_INIT_R
41
42#define CONFIG_SYS_IMMR 0x80000000
43#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR + 0x2100)
44
45/* more aggressive 'mtest' over a wider address range */
46#define CONFIG_SYS_ALT_MEMTEST
47#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest region */
48#define CONFIG_SYS_MEMTEST_END 0x0FE00000
49
50/*
51 * DDR Setup - manually set all parameters as there's no SPD etc.
52 */
53#define CONFIG_SYS_DDR_SIZE 256 /* MB */
54#define CONFIG_SYS_DDR_BASE 0x00000000
55#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
56#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
57
58/*
Gerhard Sittigb5992e72013-06-05 14:51:06 +020059 * DDR Controller Configuration
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +000060 *
61 * SYS_CFG:
62 * [31:31] MDDRC Soft Reset: Diabled
63 * [30:30] DRAM CKE pin: Enabled
64 * [29:29] DRAM CLK: Enabled
65 * [28:28] Command Mode: Enabled (For initialization only)
66 * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
67 * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
68 * [20:19] Read Test: DON'T USE
69 * [18:18] Self Refresh: Enabled
70 * [17:17] 16bit Mode: Disabled
71 * [16:13] Ready Delay: 2
72 * [12:12] Half DQS Delay: Disabled
73 * [11:11] Quarter DQS Delay: Disabled
74 * [10:08] Write Delay: 2
75 * [07:07] Early ODT: Disabled
76 * [06:06] On DIE Termination: Disabled
77 * [05:05] FIFO Overflow Clear: DON'T USE here
78 * [04:04] FIFO Underflow Clear: DON'T USE here
79 * [03:03] FIFO Overflow Pending: DON'T USE here
80 * [02:02] FIFO Underlfow Pending: DON'T USE here
81 * [01:01] FIFO Overlfow Enabled: Enabled
82 * [00:00] FIFO Underflow Enabled: Enabled
83 * TIME_CFG0
84 * [31:16] DRAM Refresh Time: 0 CSB clocks
85 * [15:8] DRAM Command Time: 0 CSB clocks
86 * [07:00] DRAM Precharge Time: 0 CSB clocks
87 * TIME_CFG1
88 * [31:26] DRAM tRFC:
89 * [25:21] DRAM tWR1:
90 * [20:17] DRAM tWRT1:
91 * [16:11] DRAM tDRR:
92 * [10:05] DRAM tRC:
93 * [04:00] DRAM tRAS:
94 * TIME_CFG2
95 * [31:28] DRAM tRCD:
96 * [27:23] DRAM tFAW:
97 * [22:19] DRAM tRTW1:
98 * [18:15] DRAM tCCD:
99 * [14:10] DRAM tRTP:
100 * [09:05] DRAM tRP:
101 * [04:00] DRAM tRPA
102 */
103
104/*
105 * NOTE: although this board uses DDR1 only, the common source brings defaults
106 * for DDR2 init sequences, that's why we have to keep those here as well
107 */
108
109/* DDR1 -- 32bit, drive strength (pad configuration) 3 for control and data */
110#define CONFIG_SYS_IOCTRL_MUX_DDR ((0 << 6) | (3 << 3) | (3 << 0))
111
112#define CONFIG_SYS_MDDRC_SYS_CFG (/* 0xEAA09100 */ 0 \
113 | (1 << 31) /* RST_B */ \
114 | (1 << 30) /* CKE */ \
115 | (1 << 29) /* CLK_ON */ \
116 | (0 << 28) /* CMD_MODE */ \
117 | (5 << 25) /* DRAM_ROW_SELECT */ \
118 | (5 << 21) /* DRAM_BANK_SELECT */ \
119 | (0 << 18) /* SELF_REF_EN */ \
120 | (0 << 17) /* 16BIT_MODE */ \
121 | (4 << 13) /* RDLY */ \
122 | (1 << 12) /* HALF_DQS_DLY */ \
123 | (0 << 11) /* QUART_DQS_DLY */ \
124 | (1 << 8) /* WDLY */ \
125 | (0 << 7) /* EARLY_ODT */ \
126 | (0 << 6) /* ON_DIE_TERMINATE */ \
127 | (0 << 5) /* FIFO_OV_CLEAR */ \
128 | (0 << 4) /* FIFO_UV_CLEAR */ \
129 | (0 << 1) /* FIFO_OV_EN */ \
130 | (0 << 0) /* FIFO_UV_EN */ \
131 )
132
133#define CONFIG_SYS_MDDRC_TIME_CFG0 0x04E03124
134#define CONFIG_SYS_MDDRC_TIME_CFG1 0x30CA1147
135#define CONFIG_SYS_MDDRC_TIME_CFG2 0x32B10864
136
137/* register address only, i.e. template without values */
138#define CONFIG_SYS_MICRON_BMODE 0x01000000
139#define CONFIG_SYS_MICRON_EMODE 0x01010000
140#define CONFIG_SYS_MICRON_EMODE2 0x01020000
141#define CONFIG_SYS_MICRON_EMODE3 0x01030000
142/*
143 * values for mode registers (without mode register address)
144 */
145/* CAS 2.5 (6), burst seq (0) and length 4 (2) */
146#define CONFIG_SYS_MICRON_BMODE_PARAM 0x00000062
147#define CONFIG_SYS_MICRON_BMODE_RSTDLL 0x00000100
148/* DLL enable, reduced drive strength */
149#define CONFIG_SYS_MICRON_EMODE_PARAM 0x00000002
150
151#define CONFIG_SYS_DDRCMD_NOP 0x01380000
152#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
153#define CONFIG_SYS_MICRON_EMR ((1 << 24) | /* CMD_REQ */ \
154 (0 << 22) | /* DRAM_CS */ \
155 (0 << 21) | /* DRAM_RAS */ \
156 (0 << 20) | /* DRAM_CAS */ \
157 (0 << 19) | /* DRAM_WEB */ \
158 (1 << 16) | /* DRAM_BS[2:0] */ \
159 (0 << 15) | /* */ \
160 (0 << 12) | /* A12->out */ \
161 (0 << 11) | /* A11->RDQS */ \
162 (0 << 10) | /* A10->DQS# */ \
163 (0 << 7) | /* OCD program */ \
164 (0 << 6) | /* Rtt1 */ \
165 (0 << 3) | /* posted CAS# */ \
166 (0 << 2) | /* Rtt0 */ \
167 (1 << 1) | /* ODS */ \
168 (0 << 0) /* DLL */ \
169 )
170#define CONFIG_SYS_MICRON_EMR2 0x01020000
171#define CONFIG_SYS_MICRON_EMR3 0x01030000
172#define CONFIG_SYS_DDRCMD_RFSH 0x01080000
173#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
174#define CONFIG_SYS_MICRON_EMR_OCD ((1 << 24) | /* CMD_REQ */ \
175 (0 << 22) | /* DRAM_CS */ \
176 (0 << 21) | /* DRAM_RAS */ \
177 (0 << 20) | /* DRAM_CAS */ \
178 (0 << 19) | /* DRAM_WEB */ \
179 (1 << 16) | /* DRAM_BS[2:0] */ \
180 (0 << 15) | /* */ \
181 (0 << 12) | /* A12->out */ \
182 (0 << 11) | /* A11->RDQS */ \
183 (1 << 10) | /* A10->DQS# */ \
184 (7 << 7) | /* OCD program */ \
185 (0 << 6) | /* Rtt1 */ \
186 (0 << 3) | /* posted CAS# */ \
187 (1 << 2) | /* Rtt0 */ \
188 (0 << 1) | /* ODS */ \
189 (0 << 0) /* DLL */ \
190 )
191
192/*
193 * Backward compatible definitions,
194 * so we do not have to change arch/powerpc/cpu/mpc512x/fixed_sdram.c
195 */
196#define CONFIG_SYS_DDRCMD_EM2 (CONFIG_SYS_MICRON_EMR2)
197#define CONFIG_SYS_DDRCMD_EM3 (CONFIG_SYS_MICRON_EMR3)
198#define CONFIG_SYS_DDRCMD_EN_DLL (CONFIG_SYS_MICRON_EMR)
199#define CONFIG_SYS_DDRCMD_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD)
200
201/* DDR Priority Manager Configuration */
202#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
203#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000
204#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001
205#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC
206#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA
207#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666
208#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555
209#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444
210#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444
211#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555
212#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558
213#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111
214#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122
215#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa
216#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa
217#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666
218#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666
219#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111
220#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111
221#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111
222#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111
223#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111
224#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111
225
226/*
227 * NOR FLASH on the Local Bus
228 */
229#define CONFIG_SYS_FLASH_CFI /* use the CFI code */
230#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
231#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of FLASH */
232#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* max flash size */
233
234#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
235#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
236#define CONFIG_SYS_FLASH_BANKS_LIST { \
237 CONFIG_SYS_FLASH_BASE + 0 * CONFIG_SYS_FLASH_SIZE, \
238 }
239#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
240
241#undef CONFIG_SYS_FLASH_CHECKSUM
242#define CONFIG_SYS_FLASH_PROTECTION
243
244/*
245 * SRAM support
246 */
247#define CONFIG_SYS_SRAM_BASE 0x30000000
248#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */
249
250/*
251 * CS related parameters
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000252 */
253/* CS0 Flash */
254#define CONFIG_SYS_CS0_CFG 0x00031110
255#define CONFIG_SYS_CS0_START 0xFC000000
256#define CONFIG_SYS_CS0_SIZE 0x04000000
257/* CS1 FRAM */
258#define CONFIG_SYS_CS1_CFG 0x00011000
259#define CONFIG_SYS_CS1_START 0xE0000000
260#define CONFIG_SYS_CS1_SIZE 0x00010000
261/* CS2 AS-i 1 */
262#define CONFIG_SYS_CS2_CFG 0x00009100
263#define CONFIG_SYS_CS2_START 0xE0100000
264#define CONFIG_SYS_CS2_SIZE 0x00080000
265/* CS3 netX */
266#define CONFIG_SYS_CS3_CFG 0x000A1140
267#define CONFIG_SYS_CS3_START 0xE0300000
268#define CONFIG_SYS_CS3_SIZE 0x00020000
269/* CS5 safety */
270#define CONFIG_SYS_CS5_CFG 0x0011F000
271#define CONFIG_SYS_CS5_START 0xE0400000
272#define CONFIG_SYS_CS5_SIZE 0x00010000
273/* CS6 AS-i 2 */
274#define CONFIG_SYS_CS6_CFG 0x00009100
275#define CONFIG_SYS_CS6_START 0xE0200000
276#define CONFIG_SYS_CS6_SIZE 0x00080000
277
278/* Don't use alternative CS timing for any CS */
279#define CONFIG_SYS_CS_ALETIMING 0x00000000
280#define CONFIG_SYS_CS_BURST 0x00000000
281#define CONFIG_SYS_CS_DEADCYCLE 0x00000020
282#define CONFIG_SYS_CS_HOLDCYCLE 0x00000020
283
284/* Use SRAM for initial stack */
285#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE
York Sunb39d1212016-04-06 13:22:10 -0700286#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000287
York Sunb39d1212016-04-06 13:22:10 -0700288#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
Masahiro Yamada627b73e2014-02-07 09:23:03 +0900289 GENERATED_GBL_DATA_SIZE)
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000290#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
291
292#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
293#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
294
295#ifdef CONFIG_FSL_DIU_FB
296#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024)
297#else
298#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
299#endif
300
301/*
302 * Serial Port
303 */
304#define CONFIG_CONS_INDEX 1
305
306/*
307 * Serial console configuration
308 */
309#define CONFIG_PSC_CONSOLE 3 /* console on PSC3 */
310#define CONFIG_SYS_PSC3
311#if CONFIG_PSC_CONSOLE != 3
312#error CONFIG_PSC_CONSOLE must be 3
313#endif
314
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000315#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE
316#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR
317#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
318#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
319
320/*
321 * Clocks in use
322 */
323#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
324 CLOCK_SCCR1_LPC_EN | \
325 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
326 CLOCK_SCCR1_PSC_EN(7) | \
327 CLOCK_SCCR1_PSCFIFO_EN | \
328 CLOCK_SCCR1_DDR_EN | \
329 CLOCK_SCCR1_FEC_EN | \
330 CLOCK_SCCR1_TPR_EN)
331
332#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
333 CLOCK_SCCR2_SPDIF_EN | \
334 CLOCK_SCCR2_DIU_EN | \
335 CLOCK_SCCR2_I2C_EN)
336
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000337#define CONFIG_CMDLINE_EDITING 1 /* command line history */
338
339/* I2C */
340#define CONFIG_HARD_I2C /* I2C with hardware support */
341#define CONFIG_I2C_MULTI_BUS
342
343/* I2C speed and slave address */
344#define CONFIG_SYS_I2C_SPEED 100000
345#define CONFIG_SYS_I2C_SLAVE 0x7F
346
347/*
Benoît Thébaudeau83306922013-04-23 10:17:42 +0000348 * IIM - IC Identification Module
349 */
350#undef CONFIG_FSL_IIM
351
352/*
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000353 * EEPROM configuration for Atmel AT24C01:
354 * 8-bit addresses, 30ms write delay, 32-Byte Page Write Mode
355 */
356#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
357#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
358#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 30
359#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
360
361/*
362 * Ethernet configuration
363 */
364#define CONFIG_MPC512x_FEC 1
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000365#define CONFIG_PHY_ADDR 0x1F
366#define CONFIG_MII 1 /* MII PHY management */
367#define CONFIG_FEC_AN_TIMEOUT 1
368#define CONFIG_HAS_ETH0
369
370/*
371 * Environment
372 */
373#define CONFIG_ENV_IS_IN_FLASH 1
374/* This has to be a multiple of the flash sector size */
375#define CONFIG_ENV_ADDR 0xFFF40000
376#define CONFIG_ENV_SIZE 0x2000
377#define CONFIG_ENV_SECT_SIZE 0x20000
378
379/* Address and size of Redundant Environment Sector */
380#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
381 CONFIG_ENV_SECT_SIZE)
382#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
383
384#define CONFIG_LOADS_ECHO 1
385#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
386
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000387#define CONFIG_CMD_EEPROM
388#undef CONFIG_CMD_FUSE
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000389#undef CONFIG_CMD_IDE
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000390#define CONFIG_CMD_JFFS2
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000391#define CONFIG_CMD_REGINFO
392
393#if defined(CONFIG_PCI)
394#define CONFIG_CMD_PCI
395#endif
396
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000397/*
398 * Miscellaneous configurable options
399 */
400#define CONFIG_SYS_LONGHELP /* undef to save memory */
401#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000402
403#ifdef CONFIG_CMD_KGDB
404# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
405#else
406# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
407#endif
408
409/* Print Buffer Size */
410#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
411 sizeof(CONFIG_SYS_PROMPT) + 16)
412/* max number of command args */
413#define CONFIG_SYS_MAXARGS 32
414/* Boot Argument Buffer Size */
415#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
416
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000417/*
418 * For booting Linux, the board info and command line data
419 * have to be in the first 8 MB of memory, since this is
420 * the maximum mapped by the Linux kernel during initialization.
421 */
422#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
423
424/* Cache Configuration */
425#define CONFIG_SYS_DCACHE_SIZE 32768
426#define CONFIG_SYS_CACHELINE_SIZE 32
427#ifdef CONFIG_CMD_KGDB
428#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of 32 */
429#endif
430
431#define CONFIG_SYS_HID0_INIT 0x000000000
432#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
433 HID0_ICE)
434#define CONFIG_SYS_HID2 HID2_HBE
435
436#define CONFIG_HIGH_BATS 1 /* High BATs supported */
437
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000438#ifdef CONFIG_CMD_KGDB
439#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000440#endif
441
442/*
443 * Environment Configuration
444 */
445#define CONFIG_ENV_OVERWRITE
446#define CONFIG_TIMESTAMP
447
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000448/* default load addr for tftp and bootm */
449#define CONFIG_LOADADDR 400000
450
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000451
Gerhard Sittigb5992e72013-06-05 14:51:06 +0200452/* the builtin environment and standard greeting */
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000453#define CONFIG_PREBOOT "echo;" \
454 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
455 "echo"
456
457#define CONFIG_EXTRA_ENV_SETTINGS_DEVEL \
Gerhard Sittig6c5001d2013-06-05 14:51:11 +0200458 "muster_nr=-00\0" \
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000459 "fromram=run ramargs addip addtty; " \
Gerhard Sittig6c5001d2013-06-05 14:51:11 +0200460 "tftp ${fdt_addr_r} ac14xx/ac14xx.dtb${muster_nr}; " \
461 "tftp ${kernel_addr_r} ac14xx/uImage${muster_nr}; " \
462 "tftp ${ramdisk_addr_r} ac14xx/uFS${muster_nr}; " \
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000463 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
464 "fromnfs=run nfsargs addip addtty; " \
Gerhard Sittig6c5001d2013-06-05 14:51:11 +0200465 "tftp ${fdt_addr_r} ac14xx/ac14xx.dtb${muster_nr}; " \
466 "tftp ${kernel_addr_r} ac14xx/uImage${muster_nr}; " \
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000467 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
468 "fromflash=run nfsargs addip addtty; " \
469 "bootm fc020000 - fc000000\0" \
470 "mtdargsrec=setenv bootargs root=/dev/mtdblock1 ro\0" \
471 "recovery=run mtdargsrec addip addtty; " \
472 "bootm ffd20000 - ffee0000\0" \
473 "production=run ramargs addip addtty; " \
474 "bootm fc020000 fc400000 fc000000\0" \
475 "mtdargs=setenv bootargs root=/dev/mtdblock1 ro\0" \
476 "prodmtd=run mtdargs addip addtty; " \
477 "bootm fc020000 - fc000000\0" \
478 ""
479
480#define CONFIG_EXTRA_ENV_SETTINGS \
481 "u-boot_addr_r=200000\0" \
482 "kernel_addr_r=600000\0" \
483 "fdt_addr_r=a00000\0" \
484 "ramdisk_addr_r=b00000\0" \
485 "u-boot_addr=FFF00000\0" \
486 "kernel_addr=FC020000\0" \
487 "fdt_addr=FC000000\0" \
488 "ramdisk_addr=FC400000\0" \
489 "verify=n\0" \
490 "ramdiskfile=ac14xx/uRamdisk\0" \
491 "u-boot=ac14xx/u-boot.bin\0" \
492 "bootfile=ac14xx/uImage\0" \
493 "fdtfile=ac14xx/ac14xx.dtb\0" \
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000494 "netdev=eth0\0" \
495 "consdev=ttyPSC0\0" \
496 "hostname=ac14xx\0" \
497 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Gerhard Sittig6c5001d2013-06-05 14:51:11 +0200498 "nfsroot=${serverip}:${rootpath}${muster_nr}\0" \
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000499 "ramargs=setenv bootargs root=/dev/ram rw\0" \
500 "addip=setenv bootargs ${bootargs} " \
501 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
502 ":${hostname}:${netdev}:off panic=1\0" \
503 "addtty=setenv bootargs ${bootargs} " \
504 "console=${consdev},${baudrate}\0" \
505 "flash_nfs=run nfsargs addip addtty;" \
506 "bootm ${kernel_addr} - ${fdt_addr}\0" \
507 "flash_self=run ramargs addip addtty;" \
508 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
509 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
510 "tftp ${fdt_addr_r} ${fdtfile};" \
511 "run nfsargs addip addtty;" \
512 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
513 "net_self=tftp ${kernel_addr_r} ${bootfile};" \
514 "tftp ${ramdisk_addr_r} ${ramdiskfile};" \
515 "tftp ${fdt_addr_r} ${fdtfile};" \
516 "run ramargs addip addtty;" \
517 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
518 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
519 "update=protect off ${u-boot_addr} +${filesize};" \
520 "era ${u-boot_addr} +${filesize};" \
521 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
522 CONFIG_EXTRA_ENV_SETTINGS_DEVEL \
523 "upd=run load update\0" \
524 ""
525
526#define CONFIG_BOOTCOMMAND "run production"
527
Gerhard Sittig6c5001d2013-06-05 14:51:11 +0200528#define CONFIG_ARP_TIMEOUT 200UL
529
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000530#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
531
532#define OF_CPU "PowerPC,5121@0"
533#define OF_SOC_COMPAT "fsl,mpc5121-immr"
534#define OF_TBCLK (bd->bi_busfreq / 4)
535#define OF_STDOUT_PATH "/soc@80000000/serial@11300"
536
537#endif /* __CONFIG_H */