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Mark Jonas3313e0e2008-03-10 11:37:10 +01001/*
2 * Configuation settings for MPR2
3 *
4 * Copyright (C) 2008
5 * Mark Jonas <mark.jonas@de.bosch.com>
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Mark Jonas3313e0e2008-03-10 11:37:10 +01008 */
9
10#ifndef __MPR2_H
11#define __MPR2_H
12
13/* Supported commands */
Mark Jonas3313e0e2008-03-10 11:37:10 +010014
15/* Default environment variables */
Mark Jonas3313e0e2008-03-10 11:37:10 +010016#define CONFIG_BOOTARGS "console=ttySC0,115200"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +000017#define CONFIG_BOOTFILE "/boot/zImage"
Mark Jonas3313e0e2008-03-10 11:37:10 +010018#define CONFIG_LOADADDR 0x8E000000
Mark Jonas3313e0e2008-03-10 11:37:10 +010019
20/* CPU and platform */
Mark Jonas3313e0e2008-03-10 11:37:10 +010021#define CONFIG_CPU_SH7720 1
22#define CONFIG_MPR2 1
23
Vladimir Zapolskiy18a40e82016-11-28 00:15:30 +020024#define CONFIG_DISPLAY_BOARDINFO
25
Mark Jonas3313e0e2008-03-10 11:37:10 +010026/* U-Boot internals */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020027#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020028#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
29#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
30#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */
31#define CONFIG_SYS_BARGSIZE 512 /* Buffer size for Boot Arguments passed to kernel */
32#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
33#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
34#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
35#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
36#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
Mark Jonas3313e0e2008-03-10 11:37:10 +010037
Nobuhiro Iwamatsub8256962011-01-17 21:13:49 +090038#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
39
Mark Jonas3313e0e2008-03-10 11:37:10 +010040/* Memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041#define CONFIG_SYS_SDRAM_BASE 0x8C000000
42#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
43#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
44#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
Mark Jonas3313e0e2008-03-10 11:37:10 +010045
46/* Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +020048#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049#define CONFIG_SYS_FLASH_EMPTY_INFO
50#define CONFIG_SYS_FLASH_BASE 0xA0000000
51#define CONFIG_SYS_MAX_FLASH_SECT 256
52#define CONFIG_SYS_MAX_FLASH_BANKS 1
53#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020054#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020055#define CONFIG_ENV_SECT_SIZE (128 * 1024)
56#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
58#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
59#define CONFIG_SYS_FLASH_WRITE_TOUT 500
Mark Jonas3313e0e2008-03-10 11:37:10 +010060
61/* Clocks */
62#define CONFIG_SYS_CLK_FREQ 24000000
Nobuhiro Iwamatsu684a5012013-08-21 16:11:21 +090063#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
64#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Jean-Christophe PLAGNIOL-VILLARDbe45c632009-06-04 12:06:48 +020065#define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */
Mark Jonas3313e0e2008-03-10 11:37:10 +010066
67/* UART */
Jean-Christophe PLAGNIOL-VILLARD6c58a032008-08-13 01:40:38 +020068#define CONFIG_SCIF_CONSOLE 1
Mark Jonas3313e0e2008-03-10 11:37:10 +010069#define CONFIG_CONS_SCIF0 1
70
71#endif /* __MPR2_H */