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Heiko Schocherc0dcece2013-08-19 16:39:01 +02001/*
2 * siemens rut
3 * (C) Copyright 2013 Siemens Schweiz AG
4 * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 *
6 * Based on:
7 * U-Boot file:/include/configs/am335x_evm.h
8 *
9 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
10 *
11 * SPDX-License-Identifier: GPL-2.0+
12 */
13
14#ifndef __CONFIG_RUT_H
15#define __CONFIG_RUT_H
16
17#define CONFIG_SIEMENS_RUT
Heiko Schocherc0dcece2013-08-19 16:39:01 +020018#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_RUT
19
20#include "siemens-am33x-common.h"
21
22#define CONFIG_SYS_MPUCLK 600
23#define RUT_IOCTRL_VAL 0x18b
24#define DDR_PLL_FREQ 303
25
26 /* Physical Memory Map */
27#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MiB */
28
29/* I2C Configuration */
30#define CONFIG_SYS_I2C_SPEED 100000
31
32#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
33#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
34#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
35#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
36
Heiko Schocherc0dcece2013-08-19 16:39:01 +020037#define CONFIG_PHY_NATSEMI
38
39#define CONFIG_FACTORYSET
40
Heiko Schocherc0dcece2013-08-19 16:39:01 +020041/* Watchdog */
42#define WATCHDOG_TRIGGER_GPIO 14
43
44#ifndef CONFIG_SPL_BUILD
45
Heiko Schocher61159b72015-06-16 14:59:34 +020046/* Use common default */
47#define MTDPARTS_DEFAULT MTDPARTS_DEFAULT_V1
48
Heiko Schocherc0dcece2013-08-19 16:39:01 +020049/* Default env settings */
50#define CONFIG_EXTRA_ENV_SETTINGS \
51 "hostname=rut\0" \
Heiko Schocher6b3943f2016-06-07 08:55:45 +020052 "ubi_off=2048\0"\
Samuel Egli56eb3da2013-11-04 14:05:03 +010053 "nand_img_size=0x500000\0" \
54 "splashpos=m,m\0" \
Heiko Schocherc0dcece2013-08-19 16:39:01 +020055 "optargs=fixrtc --no-log consoleblank=0 \0" \
Heiko Schocher61159b72015-06-16 14:59:34 +020056 CONFIG_ENV_SETTINGS_V1 \
57 CONFIG_ENV_SETTINGS_NAND_V1 \
Heiko Schocherc0dcece2013-08-19 16:39:01 +020058 "mmc_dev=0\0" \
59 "mmc_root=/dev/mmcblk0p2 rw\0" \
60 "mmc_root_fs_type=ext4 rootwait\0" \
61 "mmc_load_uimage=" \
62 "mmc rescan; " \
63 "setenv bootfile uImage;" \
64 "fatload mmc ${mmc_dev} ${kloadaddr} ${bootfile}\0" \
65 "loadbootenv=fatload mmc ${mmc_dev} ${loadaddr} ${bootenv}\0" \
66 "importbootenv=echo Importing environment from mmc ...; " \
67 "env import -t $loadaddr $filesize\0" \
68 "mmc_args=run bootargs_defaults;" \
69 "mtdparts default;" \
70 "setenv bootargs ${bootargs} " \
71 "root=${mmc_root} ${mtdparts}" \
72 "rootfstype=${mmc_root_fs_type} ip=${ip_method} " \
73 "eth=${ethaddr} " \
74 "\0" \
75 "mmc_boot=run mmc_args; " \
76 "run mmc_load_uimage; " \
77 "bootm ${kloadaddr}\0" \
78 ""
79
80#ifndef CONFIG_RESTORE_FLASH
81/* set to negative value for no autoboot */
Heiko Schocherc0dcece2013-08-19 16:39:01 +020082
83#define CONFIG_BOOTCOMMAND \
84 "if mmc rescan; then " \
85 "echo SD/MMC found on device ${mmc_dev};" \
86 "if run loadbootenv; then " \
87 "echo Loaded environment from ${bootenv};" \
88 "run importbootenv;" \
89 "fi;" \
90 "if test -n $uenvcmd; then " \
91 "echo Running uenvcmd ...;" \
92 "run uenvcmd;" \
93 "fi;" \
94 "if run mmc_load_uimage; then " \
95 "run mmc_args;" \
96 "bootm ${kloadaddr};" \
97 "fi;" \
98 "fi;" \
99 "run nand_boot;" \
Samuel Egli56eb3da2013-11-04 14:05:03 +0100100 "reset;"
Heiko Schocherc0dcece2013-08-19 16:39:01 +0200101
102#else
Heiko Schocherc0dcece2013-08-19 16:39:01 +0200103
104#define CONFIG_BOOTCOMMAND \
105 "setenv autoload no; " \
106 "dhcp; " \
107 "if tftp 80000000 debrick.scr; then " \
108 "source 80000000; " \
109 "fi"
110#endif
111
112#endif /* CONFIG_SPL_BUILD */
113
114#ifdef CONFIG_SPL_BUILD
115#undef CONFIG_HW_WATCHDOG
116#endif
117
Heiko Schocherc0dcece2013-08-19 16:39:01 +0200118#if defined(CONFIG_VIDEO)
119#define CONFIG_VIDEO_DA8XX
Heiko Schocherc0dcece2013-08-19 16:39:01 +0200120#define CONFIG_SPLASH_SCREEN
121#define CONFIG_SPLASH_SCREEN_ALIGN
122#define CONFIG_VIDEO_LOGO
123#define CONFIG_VIDEO_BMP_RLE8
124#define CONFIG_VIDEO_BMP_LOGO
Heiko Schocherc0dcece2013-08-19 16:39:01 +0200125#define DA8XX_LCD_CNTL_BASE LCD_CNTL_BASE
126
127#define CONFIG_SPI
128#define CONFIG_OMAP3_SPI
129
130#define BOARD_LCD_RESET 115 /* Bank 3 pin 19 */
Heiko Schocherc0dcece2013-08-19 16:39:01 +0200131#define CONFIG_FORMIKE
Samuel Egli56eb3da2013-11-04 14:05:03 +0100132#define DISPL_PLL_SPREAD_SPECTRUM
Heiko Schocherc0dcece2013-08-19 16:39:01 +0200133#endif
134
Heiko Schocherc0dcece2013-08-19 16:39:01 +0200135#endif /* ! __CONFIG_RUT_H */